Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17766	1		T279	2449		T307	2585		T308	10135
rd_lvl[2]	31707	1		T309	4538		T310	5864		T279	1764
rd_lvl[3]	19003	1		T239	1340		T309	343		T311	2989
rd_lvl[4]	30364	1		T239	2831		T275	3363		T311	1826
rd_lvl[5]	12493	1		T239	204		T275	1390		T312	396
rd_lvl[6]	8408	1		T239	161		T313	1078		T314	899
rd_lvl[7]	17271	1		T239	71		T276	1019		T313	752
rd_lvl[8]	22106	1		T239	31		T276	833		T315	1270
rd_lvl[9]	10617	1		T276	183		T315	282		T316	560
rd_lvl[10]	8238	1		T239	2		T276	100		T317	635
rd_lvl[11]	6161	1		T14	549		T317	441		T318	715
rd_lvl[12]	2943	1		T14	501		T15	511		T142	521
rd_lvl[13]	4253	1		T15	317		T142	265		T144	404
rd_lvl[14]	4751	1		T4	196		T14	21		T144	237
rd_lvl[15]	5862	1		T4	927		T76	456		T319	431