Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	275948	1		T1	2		T2	1		T23	1
all_pins[1]	275948	1		T1	2		T2	1		T23	1
all_pins[2]	275948	1		T1	2		T2	1		T23	1
all_pins[3]	275948	1		T1	2		T2	1		T23	1
all_pins[4]	275948	1		T1	2		T2	1		T23	1
all_pins[5]	275948	1		T1	2		T2	1		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1370743	1		T1	12		T2	6		T23	6
values[0x1]	284945	1		T4	2692		T14	2142		T15	1656
transitions[0x0=>0x1]	258085	1		T4	2470		T14	2142		T15	1656
transitions[0x1=>0x0]	258061	1		T4	2470		T14	2142		T15	1656

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	275792	1		T1	2		T2	1		T23	1
all_pins[0]	values[0x1]	156	1		T256	3		T257	3		T258	3
all_pins[0]	transitions[0x0=>0x1]	71	1		T256	1		T257	2		T258	1
all_pins[0]	transitions[0x1=>0x0]	84	1		T256	5		T257	1		T258	3
all_pins[1]	values[0x0]	275779	1		T1	2		T2	1		T23	1
all_pins[1]	values[0x1]	169	1		T256	7		T257	2		T258	5
all_pins[1]	transitions[0x0=>0x1]	142	1		T256	5		T257	1		T258	4
all_pins[1]	transitions[0x1=>0x0]	1412	1		T4	111		T76	212		T319	335
all_pins[2]	values[0x0]	274509	1		T1	2		T2	1		T23	1
all_pins[2]	values[0x1]	1439	1		T4	111		T76	212		T319	335
all_pins[2]	transitions[0x0=>0x1]	35	1		T256	2		T257	1		T258	2
all_pins[2]	transitions[0x1=>0x0]	202063	1		T4	1124		T14	1071		T15	828
all_pins[3]	values[0x0]	72481	1		T1	2		T2	1		T23	1
all_pins[3]	values[0x1]	203467	1		T4	1235		T14	1071		T15	828
all_pins[3]	transitions[0x0=>0x1]	178162	1		T4	1124		T14	1071		T15	828
all_pins[3]	transitions[0x1=>0x0]	54357	1		T4	1235		T14	1071		T15	828
all_pins[4]	values[0x0]	196286	1		T1	2		T2	1		T23	1
all_pins[4]	values[0x1]	79662	1		T4	1346		T14	1071		T15	828
all_pins[4]	transitions[0x0=>0x1]	79651	1		T4	1346		T14	1071		T15	828
all_pins[4]	transitions[0x1=>0x0]	41	1		T256	2		T258	2		T301	1
all_pins[5]	values[0x0]	275896	1		T1	2		T2	1		T23	1
all_pins[5]	values[0x1]	52	1		T256	2		T258	2		T301	1
all_pins[5]	transitions[0x0=>0x1]	24	1		T256	1		T302	1		T303	1
all_pins[5]	transitions[0x1=>0x0]	104	1		T256	2		T257	2		T258	1