Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T256	7		T257	4		T258	7
all_values[1]	278	1		T256	7		T257	4		T258	7
all_values[2]	278	1		T256	7		T257	4		T258	7
all_values[3]	278	1		T256	7		T257	4		T258	7
all_values[4]	278	1		T256	7		T257	4		T258	7
all_values[5]	278	1		T256	7		T257	4		T258	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	922	1		T256	27		T257	5		T258	25
auto[1]	746	1		T256	15		T257	19		T258	17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	581	1		T256	14		T257	10		T258	10
auto[1]	1087	1		T256	28		T257	14		T258	32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	999	1		T256	22		T257	17		T258	21
auto[1]	669	1		T256	20		T257	7		T258	21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	83	1		T256	3		T258	5		T301	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1		T256	1		T257	2		T258	1
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T256	1		T257	1		T258	1
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T256	2		T257	1		T302	3
all_values[1]	auto[0]	auto[0]	auto[1]	78	1		T257	1		T258	2		T302	1
all_values[1]	auto[0]	auto[1]	auto[1]	87	1		T256	2		T257	3		T258	1
all_values[1]	auto[1]	auto[0]	auto[1]	57	1		T256	2		T258	2		T302	2
all_values[1]	auto[1]	auto[1]	auto[1]	56	1		T256	3		T258	2		T301	2
all_values[2]	auto[0]	auto[0]	auto[0]	106	1		T256	2		T257	2		T258	1
all_values[2]	auto[0]	auto[1]	auto[0]	62	1		T258	1		T303	2		T304	1
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T256	4		T258	4		T301	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T256	1		T257	2		T258	1
all_values[3]	auto[0]	auto[0]	auto[0]	98	1		T256	6		T301	2		T302	4
all_values[3]	auto[0]	auto[1]	auto[0]	73	1		T257	3		T258	3		T301	1
all_values[3]	auto[1]	auto[0]	auto[1]	54	1		T256	1		T258	1		T301	1
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T257	1		T258	3		T302	1
all_values[4]	auto[0]	auto[0]	auto[0]	59	1		T256	2		T258	2		T303	1
all_values[4]	auto[0]	auto[0]	auto[1]	22	1		T256	1		T258	1		T303	1
all_values[4]	auto[0]	auto[1]	auto[0]	55	1		T256	1		T257	2		T258	1
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T257	1		T302	3		T303	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1		T256	2		T258	3		T303	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T256	1		T257	1		T301	2
all_values[5]	auto[0]	auto[0]	auto[0]	72	1		T256	1		T257	1		T258	1
all_values[5]	auto[0]	auto[0]	auto[1]	20	1		T304	2		T305	1		T306	1
all_values[5]	auto[0]	auto[1]	auto[0]	56	1		T256	2		T257	2		T258	1
all_values[5]	auto[0]	auto[1]	auto[1]	22	1		T256	1		T258	1		T303	2
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T256	2		T258	2		T302	2
all_values[5]	auto[1]	auto[1]	auto[1]	36	1		T256	1		T257	1		T258	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal