Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	260437	1		T1	1		T2	1		T3	2
all_values[1]	260437	1		T1	1		T2	1		T3	2
all_values[2]	260437	1		T1	1		T2	1		T3	2
all_values[3]	260437	1		T1	1		T2	1		T3	2
all_values[4]	260437	1		T1	1		T2	1		T3	2
all_values[5]	260437	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	526219	1		T1	6		T2	6		T3	12
auto[1]	1036403	1		T5	18768		T13	17408		T14	5904

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	760511	1		T1	4		T2	4		T3	7
auto[1]	802111	1		T1	2		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	260276	1		T1	1		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	161	1		T247	7		T248	7		T249	2
all_values[1]	auto[0]	auto[1]	260279	1		T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	158	1		T247	4		T248	2		T249	6
all_values[2]	auto[0]	auto[0]	1349	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	56	1		T248	1		T249	2		T306	1
all_values[2]	auto[1]	auto[0]	258971	1		T5	4692		T13	4352		T14	1476
all_values[2]	auto[1]	auto[1]	61	1		T247	3		T248	3		T249	1
all_values[3]	auto[0]	auto[0]	1361	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	56	1		T247	2		T306	1		T307	2
all_values[3]	auto[1]	auto[0]	54104	1		T5	782		T13	51		T14	738
all_values[3]	auto[1]	auto[1]	204916	1		T5	3910		T13	4301		T14	738
all_values[4]	auto[0]	auto[0]	977	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	435	1		T3	1		T6	1		T7	1
all_values[4]	auto[1]	auto[0]	183473	1		T5	3910		T13	3271		T14	738
all_values[4]	auto[1]	auto[1]	75552	1		T5	782		T13	1081		T14	738
all_values[5]	auto[0]	auto[0]	1336	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	94	1		T45	1		T46	1		T89	1
all_values[5]	auto[1]	auto[0]	258940	1		T5	4692		T13	4352		T14	1476
all_values[5]	auto[1]	auto[1]	67	1		T247	4		T248	1		T307	2