Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275948	1		T1	2		T2	1		T23	1
all_values[1]	275948	1		T1	2		T2	1		T23	1
all_values[2]	275948	1		T1	2		T2	1		T23	1
all_values[3]	275948	1		T1	2		T2	1		T23	1
all_values[4]	275948	1		T1	2		T2	1		T23	1
all_values[5]	275948	1		T1	2		T2	1		T23	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	557334	1		T1	12		T2	6		T23	6
auto[1]	1098354	1		T4	9880		T14	8568		T15	6624

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	806467	1		T1	7		T2	4		T23	4
auto[1]	849221	1		T1	5		T2	2		T23	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	275792	1		T1	2		T2	1		T23	1
all_values[0]	auto[1]	auto[1]	156	1		T256	3		T257	3		T258	3
all_values[1]	auto[0]	auto[1]	275779	1		T1	2		T2	1		T23	1
all_values[1]	auto[1]	auto[1]	169	1		T256	7		T257	2		T258	5
all_values[2]	auto[0]	auto[0]	1400	1		T1	2		T2	1		T23	1
all_values[2]	auto[0]	auto[1]	59	1		T256	3		T257	1		T258	3
all_values[2]	auto[1]	auto[0]	274438	1		T4	2470		T14	2142		T15	1656
all_values[2]	auto[1]	auto[1]	51	1		T256	2		T257	1		T258	2
all_values[3]	auto[0]	auto[0]	1391	1		T1	2		T2	1		T23	1
all_values[3]	auto[0]	auto[1]	47	1		T258	1		T301	1		T303	3
all_values[3]	auto[1]	auto[0]	54167	1		T4	1235		T14	1071		T15	828
all_values[3]	auto[1]	auto[1]	220343	1		T4	1235		T14	1071		T15	828
all_values[4]	auto[0]	auto[0]	975	1		T1	1		T2	1		T23	1
all_values[4]	auto[0]	auto[1]	448	1		T1	1		T5	1		T9	1
all_values[4]	auto[1]	auto[0]	198288	1		T4	1235		T14	1071		T15	828
all_values[4]	auto[1]	auto[1]	76237	1		T4	1235		T14	1071		T15	828
all_values[5]	auto[0]	auto[0]	1355	1		T1	2		T2	1		T23	1
all_values[5]	auto[0]	auto[1]	88	1		T49	1		T50	1		T81	1
all_values[5]	auto[1]	auto[0]	274453	1		T4	2470		T14	2142		T15	1656
all_values[5]	auto[1]	auto[1]	52	1		T256	2		T258	2		T301	1