Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	362500815	0	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	362500815	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	362500815	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	362500815	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	362500815	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	362500815	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	362500815	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	362500815	0	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	362500815	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	362500815	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	362500815	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	362500815	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	362500815	0	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	362500815	0	0	868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	362500815	0	0	868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	362500815	0	0	868
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	362500815	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	362500815	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	362500815	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	362500815	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	362500815	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	362500815	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	362500815	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	362500815	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	873	873	0	0
tb.dut.FlashAddrKnown_A	0	0	362500815	251510380	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	362500815	361744231	0	0
tb.dut.FlashKnownO_A	0	0	362500815	361744231	0	0
tb.dut.FlashProgKnown_A	0	0	362500815	135740757	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	362500815	361744231	0	0
tb.dut.IntrErrO_A	0	0	362500815	361744231	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	362500815	361744231	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	362500815	361744231	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	362500815	361744231	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	362500815	361744231	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	362500815	361744231	0	0
tb.dut.MemRspPayLoad_A	0	0	362500815	4555904	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	362500815	361744231	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	362500815	361744231	0	0
tb.dut.MemTlDValidKnownO_A	0	0	362500815	361744231	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	362500815	361744231	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	362500815	361744231	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	362500815	361744231	0	0
tb.dut.RspPayLoad_A	0	0	362500815	37862353	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	362500815	361744231	0	0
tb.dut.TdoEnIsOne_A	0	0	362500815	361744231	0	0
tb.dut.TdoKnown_A	0	0	362500815	361744231	0	0
tb.dut.TlAReadyKnownO_A	0	0	362500815	361744231	0	0
tb.dut.TlDValidKnownO_A	0	0	362500815	361744231	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	365104847	4214	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	365104847	2017	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	365104847	2712	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	365104847	2530	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	365104847	2561	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	365104847	2611	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	365104847	2662	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	365104847	2689	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	365104847	2157	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	365104847	2643	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	365104847	1741	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	365104847	2187	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	365104847	1944	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	365104847	1041	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	365104847	1945	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	365104847	1971	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	365104847	1577	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	365104847	1388	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	365104847	2057	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	365104847	1831	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	365104847	1507	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	365104847	1435	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	365104847	2720	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	365104847	1871	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	365104847	2251	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	365104847	2527	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	365104847	2028	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	365104847	1377	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	365104847	2663	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	365104847	1672	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	365104847	1765	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	365104847	2179	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	365104847	1260	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	365104847	2860	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	365104847	2757	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	365104847	2663	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	365104847	2774	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	365104847	2221	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	365104847	986	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	365104847	1493	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	365104847	1944	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	365104847	1552	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	365104847	1905	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	365104847	1891	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	365104847	1844	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	365104847	1433	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	365104847	1479	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	365104847	1467	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	365104847	2237	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	365104847	1495	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	365104847	2126	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	365104847	1600	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	365104847	1485	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	365104847	1479	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	365104847	1952	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	365104847	1866	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	365104847	1452	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	365104847	1069	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	365104847	1450	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	365104847	2104	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	365104847	2735	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	365104847	2069	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	365104847	1132	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	365104847	2089	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	365104847	1166	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	365104847	2101	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	365104847	1576	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	365104847	1769	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	365104847	2208	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	365104847	2080	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	365104847	2625	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	365104847	2485	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	365104847	2617	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	365104847	2793	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	365104847	1603	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	365104847	2694	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	365104847	1843	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	365104847	1722	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	365104847	987	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	365104847	1558	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	365104847	1956	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	365104847	1509	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	365104847	1421	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	365104847	974	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	365104847	1606	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	365104847	1938	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	365104847	1643	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	365104813	31792969	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	365104813	364256178	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	365104813	364256178	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	365104813	38559012	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	365104813	364256178	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	365104813	364256178	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	992	0	10
Category 0	992	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	992	0	10
Severity 0	992	0	10

	NUMBER	PERCENT
Total Number	992	100.00
Uncovered	50	5.04
Success	942	94.96
Failure	0	0.00
Incomplete	15	1.51
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	3	30.00
All Matches	7	70.00
First Matches	7	70.00