Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T17 |
1 |
|
T39 |
9 |
|
T69 |
1 |
| others[1] |
209 |
1 |
|
T7 |
1 |
|
T39 |
8 |
|
T45 |
1 |
| others[2] |
223 |
1 |
|
T16 |
1 |
|
T39 |
12 |
|
T32 |
1 |
| others[3] |
330 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T39 |
14 |
| false |
126 |
1 |
|
T39 |
3 |
|
T146 |
4 |
|
T354 |
1 |
| true |
13705 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9435 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T15 |
1 |
| others[1] |
1191 |
1 |
|
T5 |
1 |
|
T39 |
21 |
|
T40 |
3 |
| others[2] |
1179 |
1 |
|
T2 |
6 |
|
T4 |
1 |
|
T39 |
23 |
| others[3] |
2043 |
1 |
|
T2 |
2 |
|
T11 |
2 |
|
T16 |
2 |
| false |
632 |
1 |
|
T2 |
3 |
|
T39 |
7 |
|
T40 |
2 |
| true |
326 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9419 |
1 |
|
T2 |
2 |
|
T33 |
1 |
|
T22 |
2 |
| others[1] |
1221 |
1 |
|
T2 |
4 |
|
T8 |
1 |
|
T39 |
24 |
| others[2] |
1230 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| others[3] |
2038 |
1 |
|
T2 |
3 |
|
T16 |
1 |
|
T39 |
33 |
| false |
616 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T16 |
1 |
| true |
282 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| others[1] |
101 |
1 |
|
T39 |
5 |
|
T355 |
1 |
|
T146 |
5 |
| others[2] |
115 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T39 |
6 |
| others[3] |
190 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| false |
39 |
1 |
|
T146 |
1 |
|
T89 |
1 |
|
T108 |
2 |
| true |
14251 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T39 |
12 |
|
T59 |
1 |
|
T206 |
1 |
| others[1] |
222 |
1 |
|
T39 |
10 |
|
T69 |
1 |
|
T85 |
1 |
| others[2] |
216 |
1 |
|
T39 |
14 |
|
T12 |
1 |
|
T355 |
1 |
| others[3] |
378 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T39 |
12 |
| false |
106 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T146 |
9 |
| true |
13641 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9208 |
1 |
|
T2 |
5 |
|
T6 |
1 |
|
T22 |
2 |
| others[1] |
1030 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T16 |
1 |
| others[2] |
1033 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T8 |
1 |
| others[3] |
1698 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T33 |
1 |
| false |
533 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T39 |
9 |
| true |
1304 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T39 |
15 |
|
T59 |
1 |
|
T224 |
1 |
| others[1] |
222 |
1 |
|
T7 |
1 |
|
T39 |
6 |
|
T45 |
1 |
| others[2] |
194 |
1 |
|
T15 |
1 |
|
T39 |
10 |
|
T84 |
1 |
| others[3] |
385 |
1 |
|
T3 |
1 |
|
T39 |
19 |
|
T85 |
1 |
| false |
120 |
1 |
|
T39 |
4 |
|
T146 |
9 |
|
T108 |
1 |
| true |
13674 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T39 |
8 |
| others[1] |
219 |
1 |
|
T16 |
1 |
|
T39 |
8 |
|
T206 |
1 |
| others[2] |
196 |
1 |
|
T11 |
1 |
|
T39 |
11 |
|
T45 |
1 |
| others[3] |
352 |
1 |
|
T3 |
1 |
|
T39 |
14 |
|
T268 |
1 |
| false |
111 |
1 |
|
T39 |
5 |
|
T69 |
1 |
|
T146 |
7 |
| true |
13689 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9373 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T16 |
1 |
| others[1] |
1210 |
1 |
|
T2 |
4 |
|
T16 |
1 |
|
T39 |
16 |
| others[2] |
1202 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T39 |
19 |
| others[3] |
2065 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T15 |
1 |
| false |
633 |
1 |
|
T39 |
11 |
|
T40 |
1 |
|
T96 |
13 |
| true |
323 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T2 |
4 |
|
T39 |
21 |
|
T40 |
4 |
| others[1] |
1222 |
1 |
|
T2 |
3 |
|
T16 |
1 |
|
T39 |
18 |
| others[2] |
1177 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T15 |
1 |
| others[3] |
2043 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T11 |
1 |
| false |
636 |
1 |
|
T2 |
2 |
|
T39 |
4 |
|
T40 |
3 |
| true |
297 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T39 |
1 |
| others[1] |
105 |
1 |
|
T39 |
9 |
|
T355 |
1 |
|
T146 |
2 |
| others[2] |
110 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T39 |
5 |
| others[3] |
161 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T33 |
1 |
| false |
54 |
1 |
|
T146 |
3 |
|
T89 |
1 |
|
T108 |
2 |
| true |
6099 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T13 |
1 |
| others[1] |
234 |
1 |
|
T39 |
12 |
|
T85 |
1 |
|
T222 |
1 |
| others[2] |
226 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T39 |
7 |
| others[3] |
361 |
1 |
|
T16 |
1 |
|
T39 |
17 |
|
T32 |
1 |
| false |
109 |
1 |
|
T39 |
5 |
|
T59 |
1 |
|
T146 |
5 |
| true |
5449 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1053 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T16 |
1 |
| others[1] |
1022 |
1 |
|
T2 |
3 |
|
T4 |
1 |
|
T33 |
1 |
| others[2] |
1022 |
1 |
|
T2 |
2 |
|
T11 |
2 |
|
T5 |
1 |
| others[3] |
1738 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T7 |
1 |
| false |
499 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T39 |
9 |
| true |
1297 |
1 |
|
T17 |
1 |
|
T13 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T39 |
13 |
|
T146 |
5 |
|
T159 |
1 |
| others[1] |
212 |
1 |
|
T39 |
10 |
|
T45 |
1 |
|
T146 |
10 |
| others[2] |
223 |
1 |
|
T6 |
1 |
|
T11 |
2 |
|
T15 |
1 |
| others[3] |
385 |
1 |
|
T33 |
1 |
|
T13 |
1 |
|
T39 |
20 |
| false |
99 |
1 |
|
T39 |
3 |
|
T146 |
2 |
|
T79 |
1 |
| true |
5480 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T16 |
1 |
|
T39 |
6 |
|
T146 |
8 |
| others[1] |
235 |
1 |
|
T39 |
19 |
|
T355 |
1 |
|
T222 |
1 |
| others[2] |
216 |
1 |
|
T39 |
13 |
|
T268 |
1 |
|
T222 |
1 |
| others[3] |
370 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| false |
102 |
1 |
|
T39 |
3 |
|
T146 |
6 |
|
T149 |
7 |
| true |
5510 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1198 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T15 |
1 |
| others[1] |
1308 |
1 |
|
T2 |
3 |
|
T16 |
1 |
|
T39 |
20 |
| others[2] |
1165 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T39 |
23 |
| others[3] |
2064 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| false |
578 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T5 |
1 |
| true |
318 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T33 |
1 |
| others[1] |
1222 |
1 |
|
T2 |
4 |
|
T39 |
12 |
|
T9 |
1 |
| others[2] |
1184 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| others[3] |
2096 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T16 |
1 |
| false |
626 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T39 |
10 |
| true |
292 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T39 |
6 |
|
T146 |
5 |
|
T108 |
1 |
| others[1] |
116 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
2 |
| others[2] |
107 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| others[3] |
186 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| false |
60 |
1 |
|
T39 |
2 |
|
T146 |
4 |
|
T108 |
2 |
| true |
6065 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T3 |
1 |
|
T39 |
10 |
|
T146 |
10 |
| others[1] |
221 |
1 |
|
T17 |
1 |
|
T16 |
1 |
|
T39 |
11 |
| others[2] |
241 |
1 |
|
T39 |
8 |
|
T32 |
1 |
|
T222 |
1 |
| others[3] |
398 |
1 |
|
T11 |
2 |
|
T39 |
15 |
|
T46 |
1 |
| false |
108 |
1 |
|
T39 |
3 |
|
T12 |
1 |
|
T355 |
1 |
| true |
5451 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T8 |
1 |
| others[1] |
1002 |
1 |
|
T2 |
2 |
|
T11 |
2 |
|
T15 |
1 |
| others[2] |
1087 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T39 |
19 |
| others[3] |
1691 |
1 |
|
T2 |
7 |
|
T33 |
1 |
|
T39 |
28 |
| false |
552 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T39 |
7 |
| true |
1280 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T13 |
1 |
|
T39 |
7 |
|
T355 |
1 |
| others[1] |
222 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T39 |
8 |
| others[2] |
217 |
1 |
|
T39 |
11 |
|
T69 |
1 |
|
T224 |
1 |
| others[3] |
389 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| false |
103 |
1 |
|
T39 |
6 |
|
T59 |
1 |
|
T222 |
1 |
| true |
5456 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T39 |
12 |
| others[1] |
195 |
1 |
|
T39 |
6 |
|
T84 |
1 |
|
T146 |
5 |
| others[2] |
194 |
1 |
|
T11 |
1 |
|
T39 |
9 |
|
T355 |
2 |
| others[3] |
377 |
1 |
|
T3 |
1 |
|
T39 |
15 |
|
T32 |
1 |
| false |
119 |
1 |
|
T39 |
5 |
|
T85 |
1 |
|
T146 |
3 |
| true |
5516 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| others[1] |
1197 |
1 |
|
T2 |
3 |
|
T7 |
1 |
|
T11 |
1 |
| others[2] |
1241 |
1 |
|
T2 |
2 |
|
T39 |
22 |
|
T75 |
1 |
| others[3] |
2006 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
1 |
| false |
624 |
1 |
|
T2 |
3 |
|
T39 |
5 |
|
T40 |
1 |
| true |
318 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| others[1] |
1278 |
1 |
|
T2 |
5 |
|
T16 |
1 |
|
T8 |
1 |
| others[2] |
1179 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
2 |
| others[3] |
2022 |
1 |
|
T2 |
4 |
|
T33 |
1 |
|
T39 |
36 |
| false |
645 |
1 |
|
T16 |
1 |
|
T39 |
11 |
|
T40 |
2 |
| true |
296 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| others[1] |
100 |
1 |
|
T39 |
3 |
|
T355 |
1 |
|
T146 |
1 |
| others[2] |
89 |
1 |
|
T11 |
1 |
|
T39 |
2 |
|
T45 |
1 |
| others[3] |
147 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
2 |
| false |
39 |
1 |
|
T33 |
1 |
|
T39 |
4 |
|
T146 |
1 |
| true |
6153 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T39 |
11 |
|
T75 |
1 |
|
T45 |
1 |
| others[1] |
220 |
1 |
|
T11 |
1 |
|
T39 |
11 |
|
T85 |
1 |
| others[2] |
234 |
1 |
|
T33 |
1 |
|
T16 |
1 |
|
T39 |
14 |
| others[3] |
344 |
1 |
|
T17 |
1 |
|
T39 |
16 |
|
T12 |
1 |
| false |
107 |
1 |
|
T39 |
4 |
|
T146 |
2 |
|
T199 |
1 |
| true |
5484 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
999 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T15 |
1 |
| others[1] |
1013 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T16 |
1 |
| others[2] |
1068 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T16 |
1 |
| others[3] |
1713 |
1 |
|
T2 |
6 |
|
T33 |
1 |
|
T8 |
1 |
| false |
535 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T11 |
1 |
| true |
1303 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T3 |
1 |
|
T39 |
10 |
|
T69 |
1 |
| others[1] |
225 |
1 |
|
T33 |
1 |
|
T39 |
11 |
|
T85 |
1 |
| others[2] |
221 |
1 |
|
T17 |
1 |
|
T39 |
11 |
|
T355 |
1 |
| others[3] |
381 |
1 |
|
T7 |
1 |
|
T39 |
19 |
|
T84 |
1 |
| false |
131 |
1 |
|
T39 |
6 |
|
T146 |
5 |
|
T149 |
4 |
| true |
5439 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T39 |
12 |
|
T46 |
1 |
|
T146 |
8 |
| others[1] |
218 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T15 |
1 |
| others[2] |
209 |
1 |
|
T11 |
1 |
|
T39 |
9 |
|
T206 |
1 |
| others[3] |
335 |
1 |
|
T39 |
12 |
|
T146 |
13 |
|
T159 |
1 |
| false |
104 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T39 |
8 |
| true |
5540 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T39 |
14 |
| others[1] |
1181 |
1 |
|
T2 |
2 |
|
T39 |
21 |
|
T40 |
3 |
| others[2] |
1267 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| others[3] |
2007 |
1 |
|
T2 |
8 |
|
T11 |
1 |
|
T15 |
1 |
| false |
614 |
1 |
|
T39 |
14 |
|
T40 |
2 |
|
T96 |
5 |
| true |
316 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T39 |
17 |
| others[1] |
1243 |
1 |
|
T2 |
2 |
|
T8 |
1 |
|
T39 |
17 |
| others[2] |
1157 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T11 |
1 |
| others[3] |
2040 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
1 |
| false |
642 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T39 |
8 |
| true |
290 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T13 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |