Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T39 |
4 |
|
T355 |
1 |
|
T146 |
3 |
| others[1] |
97 |
1 |
|
T15 |
1 |
|
T39 |
1 |
|
T222 |
1 |
| others[2] |
86 |
1 |
|
T11 |
1 |
|
T39 |
3 |
|
T146 |
2 |
| others[3] |
179 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T16 |
2 |
| false |
56 |
1 |
|
T3 |
1 |
|
T39 |
1 |
|
T355 |
1 |
| true |
6121 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T3 |
1 |
|
T39 |
16 |
|
T84 |
1 |
| others[1] |
231 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T146 |
17 |
| others[2] |
226 |
1 |
|
T39 |
9 |
|
T146 |
8 |
|
T159 |
1 |
| others[3] |
372 |
1 |
|
T11 |
1 |
|
T39 |
16 |
|
T85 |
1 |
| false |
115 |
1 |
|
T13 |
1 |
|
T39 |
5 |
|
T45 |
1 |
| true |
5459 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1048 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| others[1] |
1082 |
1 |
|
T2 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
1040 |
1 |
|
T2 |
4 |
|
T33 |
1 |
|
T16 |
1 |
| others[3] |
1634 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T11 |
1 |
| false |
506 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T39 |
10 |
| true |
1321 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T69 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| others[1] |
233 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T355 |
1 |
| others[2] |
212 |
1 |
|
T39 |
9 |
|
T355 |
1 |
|
T146 |
10 |
| others[3] |
364 |
1 |
|
T17 |
1 |
|
T16 |
1 |
|
T39 |
20 |
| false |
109 |
1 |
|
T7 |
1 |
|
T39 |
6 |
|
T69 |
1 |
| true |
5468 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T11 |
1 |
|
T39 |
12 |
|
T84 |
1 |
| others[1] |
206 |
1 |
|
T16 |
1 |
|
T39 |
6 |
|
T46 |
1 |
| others[2] |
211 |
1 |
|
T16 |
1 |
|
T39 |
10 |
|
T146 |
9 |
| others[3] |
359 |
1 |
|
T17 |
1 |
|
T39 |
16 |
|
T69 |
1 |
| false |
121 |
1 |
|
T39 |
3 |
|
T32 |
1 |
|
T355 |
1 |
| true |
5505 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1158 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T16 |
1 |
| others[1] |
1234 |
1 |
|
T2 |
1 |
|
T39 |
17 |
|
T40 |
2 |
| others[2] |
1213 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T33 |
1 |
| others[3] |
2035 |
1 |
|
T2 |
5 |
|
T11 |
2 |
|
T39 |
32 |
| false |
673 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T8 |
1 |
| true |
318 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T2 |
3 |
|
T39 |
21 |
|
T40 |
3 |
| others[1] |
1205 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T11 |
1 |
| others[2] |
1195 |
1 |
|
T2 |
4 |
|
T16 |
1 |
|
T39 |
23 |
| others[3] |
2101 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T39 |
19 |
| false |
626 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| true |
292 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T11 |
1 |
|
T39 |
6 |
|
T146 |
2 |
| others[1] |
88 |
1 |
|
T33 |
1 |
|
T16 |
1 |
|
T39 |
4 |
| others[2] |
102 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T39 |
3 |
| others[3] |
152 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T39 |
3 |
| false |
49 |
1 |
|
T39 |
3 |
|
T146 |
1 |
|
T108 |
1 |
| true |
6130 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T39 |
11 |
|
T268 |
1 |
|
T32 |
1 |
| others[1] |
220 |
1 |
|
T17 |
1 |
|
T39 |
8 |
|
T206 |
1 |
| others[2] |
221 |
1 |
|
T15 |
1 |
|
T13 |
1 |
|
T39 |
10 |
| others[3] |
368 |
1 |
|
T11 |
1 |
|
T39 |
13 |
|
T146 |
23 |
| false |
115 |
1 |
|
T39 |
4 |
|
T146 |
9 |
|
T149 |
4 |
| true |
5471 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
991 |
1 |
|
T2 |
3 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
982 |
1 |
|
T2 |
2 |
|
T8 |
1 |
|
T39 |
23 |
| others[2] |
1040 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
1784 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T11 |
2 |
| false |
543 |
1 |
|
T2 |
1 |
|
T39 |
8 |
|
T40 |
2 |
| true |
1291 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T16 |
1 |
|
T39 |
9 |
|
T59 |
1 |
| others[1] |
232 |
1 |
|
T17 |
1 |
|
T39 |
6 |
|
T69 |
1 |
| others[2] |
247 |
1 |
|
T11 |
1 |
|
T39 |
12 |
|
T222 |
1 |
| others[3] |
348 |
1 |
|
T15 |
1 |
|
T39 |
22 |
|
T85 |
1 |
| false |
111 |
1 |
|
T39 |
5 |
|
T146 |
1 |
|
T161 |
1 |
| true |
5479 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T33 |
1 |
| others[1] |
211 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
8 |
| others[2] |
200 |
1 |
|
T39 |
9 |
|
T146 |
10 |
|
T149 |
12 |
| others[3] |
373 |
1 |
|
T7 |
1 |
|
T39 |
11 |
|
T45 |
1 |
| false |
117 |
1 |
|
T17 |
1 |
|
T16 |
1 |
|
T39 |
5 |
| true |
5508 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1196 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T39 |
22 |
| others[1] |
1207 |
1 |
|
T2 |
7 |
|
T33 |
1 |
|
T8 |
1 |
| others[2] |
1174 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T39 |
31 |
| others[3] |
2100 |
1 |
|
T2 |
2 |
|
T11 |
2 |
|
T15 |
1 |
| false |
626 |
1 |
|
T2 |
1 |
|
T39 |
7 |
|
T96 |
6 |
| true |
328 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T15 |
1 |
| others[1] |
1243 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T39 |
27 |
| others[2] |
1242 |
1 |
|
T2 |
1 |
|
T39 |
15 |
|
T40 |
2 |
| others[3] |
2007 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T33 |
1 |
| false |
594 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T39 |
5 |
| true |
294 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T16 |
1 |
|
T39 |
3 |
|
T355 |
1 |
| others[1] |
106 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T39 |
5 |
| others[2] |
91 |
1 |
|
T11 |
1 |
|
T39 |
4 |
|
T146 |
2 |
| others[3] |
185 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T39 |
6 |
| false |
70 |
1 |
|
T39 |
2 |
|
T222 |
1 |
|
T146 |
5 |
| true |
6074 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T6 |
1 |
|
T39 |
10 |
|
T85 |
1 |
| others[1] |
240 |
1 |
|
T15 |
1 |
|
T39 |
10 |
|
T12 |
1 |
| others[2] |
226 |
1 |
|
T39 |
8 |
|
T146 |
11 |
|
T159 |
1 |
| others[3] |
407 |
1 |
|
T3 |
1 |
|
T39 |
20 |
|
T32 |
1 |
| false |
115 |
1 |
|
T39 |
5 |
|
T206 |
1 |
|
T146 |
5 |
| true |
5429 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1092 |
1 |
|
T2 |
2 |
|
T39 |
26 |
|
T40 |
2 |
| others[1] |
1071 |
1 |
|
T2 |
6 |
|
T33 |
1 |
|
T39 |
18 |
| others[2] |
946 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T11 |
1 |
| others[3] |
1638 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T15 |
1 |
| false |
544 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T13 |
1 |
| true |
1340 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T15 |
1 |
| others[1] |
230 |
1 |
|
T6 |
1 |
|
T39 |
8 |
|
T206 |
1 |
| others[2] |
205 |
1 |
|
T16 |
1 |
|
T39 |
12 |
|
T146 |
11 |
| others[3] |
405 |
1 |
|
T17 |
1 |
|
T39 |
14 |
|
T32 |
1 |
| false |
130 |
1 |
|
T39 |
7 |
|
T45 |
1 |
|
T146 |
8 |
| true |
5437 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T16 |
1 |
|
T39 |
16 |
|
T146 |
4 |
| others[1] |
199 |
1 |
|
T16 |
1 |
|
T39 |
4 |
|
T146 |
12 |
| others[2] |
231 |
1 |
|
T11 |
1 |
|
T39 |
4 |
|
T224 |
1 |
| others[3] |
365 |
1 |
|
T7 |
1 |
|
T39 |
11 |
|
T85 |
1 |
| false |
103 |
1 |
|
T11 |
1 |
|
T39 |
4 |
|
T146 |
3 |
| true |
5523 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1198 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T15 |
1 |
| others[1] |
1239 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T5 |
1 |
| others[2] |
1206 |
1 |
|
T2 |
4 |
|
T39 |
22 |
|
T69 |
1 |
| others[3] |
2005 |
1 |
|
T2 |
2 |
|
T33 |
1 |
|
T8 |
1 |
| false |
666 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T39 |
9 |
| true |
317 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T16 |
1 |
| others[1] |
1193 |
1 |
|
T2 |
2 |
|
T39 |
23 |
|
T9 |
1 |
| others[2] |
1176 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T33 |
1 |
| others[3] |
2080 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T16 |
1 |
| false |
644 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T39 |
12 |
| true |
299 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T39 |
3 |
|
T146 |
3 |
|
T149 |
4 |
| others[1] |
86 |
1 |
|
T39 |
1 |
|
T146 |
4 |
|
T354 |
1 |
| others[2] |
107 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
174 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T39 |
3 |
| false |
52 |
1 |
|
T16 |
1 |
|
T39 |
4 |
|
T146 |
2 |
| true |
6115 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T39 |
9 |
|
T84 |
1 |
|
T59 |
1 |
| others[1] |
216 |
1 |
|
T16 |
1 |
|
T39 |
13 |
|
T85 |
1 |
| others[2] |
214 |
1 |
|
T39 |
8 |
|
T12 |
1 |
|
T146 |
9 |
| others[3] |
408 |
1 |
|
T39 |
17 |
|
T355 |
1 |
|
T146 |
22 |
| false |
129 |
1 |
|
T7 |
1 |
|
T39 |
4 |
|
T146 |
4 |
| true |
5441 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T11 |
1 |
|
T39 |
18 |
|
T40 |
2 |
| others[1] |
1030 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T16 |
1 |
| others[2] |
1025 |
1 |
|
T2 |
2 |
|
T33 |
1 |
|
T16 |
1 |
| others[3] |
1702 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T17 |
1 |
| false |
520 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T39 |
8 |
| true |
1308 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T39 |
9 |
|
T84 |
1 |
|
T355 |
1 |
| others[1] |
233 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T268 |
1 |
| others[2] |
250 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T39 |
10 |
| others[3] |
371 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T13 |
1 |
| false |
124 |
1 |
|
T33 |
1 |
|
T39 |
6 |
|
T222 |
1 |
| true |
5444 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T39 |
11 |
|
T85 |
1 |
|
T46 |
1 |
| others[1] |
198 |
1 |
|
T39 |
8 |
|
T206 |
1 |
|
T146 |
10 |
| others[2] |
203 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
368 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| false |
136 |
1 |
|
T39 |
9 |
|
T355 |
1 |
|
T146 |
4 |
| true |
5507 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T39 |
22 |
|
T69 |
1 |
|
T40 |
1 |
| others[1] |
1211 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T39 |
19 |
| others[2] |
1207 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T5 |
1 |
| others[3] |
2058 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| false |
602 |
1 |
|
T2 |
3 |
|
T39 |
5 |
|
T96 |
11 |
| true |
330 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1210 |
1 |
|
T2 |
3 |
|
T39 |
19 |
|
T40 |
1 |
| others[1] |
1203 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| others[2] |
1286 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| others[3] |
1962 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T5 |
1 |
| false |
678 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T39 |
8 |
| true |
292 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T33 |
1 |
|
T39 |
4 |
|
T355 |
1 |
| others[1] |
98 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| others[2] |
107 |
1 |
|
T16 |
1 |
|
T39 |
5 |
|
T69 |
1 |
| others[3] |
193 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| false |
55 |
1 |
|
T39 |
3 |
|
T146 |
4 |
|
T149 |
4 |
| true |
6075 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T75 |
1 |
| others[1] |
231 |
1 |
|
T3 |
1 |
|
T39 |
12 |
|
T84 |
1 |
| others[2] |
227 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T13 |
1 |
| others[3] |
415 |
1 |
|
T39 |
11 |
|
T59 |
1 |
|
T355 |
1 |
| false |
103 |
1 |
|
T7 |
1 |
|
T39 |
4 |
|
T355 |
1 |
| true |
5436 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1011 |
1 |
|
T2 |
3 |
|
T33 |
1 |
|
T39 |
15 |
| others[1] |
985 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T13 |
1 |
| others[2] |
1013 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T39 |
27 |
| others[3] |
1792 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| false |
505 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T39 |
8 |
| true |
1325 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |