Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
269 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T39 |
11 |
| others[1] |
215 |
1 |
|
T33 |
1 |
|
T39 |
8 |
|
T59 |
1 |
| others[2] |
210 |
1 |
|
T39 |
10 |
|
T146 |
6 |
|
T149 |
8 |
| others[3] |
378 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T11 |
1 |
| false |
119 |
1 |
|
T39 |
5 |
|
T355 |
1 |
|
T146 |
3 |
| true |
5440 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T11 |
2 |
|
T16 |
1 |
|
T39 |
10 |
| others[1] |
213 |
1 |
|
T33 |
1 |
|
T39 |
11 |
|
T146 |
11 |
| others[2] |
233 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T39 |
3 |
| others[3] |
372 |
1 |
|
T6 |
1 |
|
T39 |
13 |
|
T69 |
1 |
| false |
106 |
1 |
|
T39 |
10 |
|
T146 |
6 |
|
T149 |
4 |
| true |
5494 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
21 |
| others[1] |
1204 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T8 |
1 |
| others[2] |
1227 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T5 |
1 |
| others[3] |
2032 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T33 |
1 |
| false |
626 |
1 |
|
T2 |
1 |
|
T39 |
16 |
|
T40 |
2 |
| true |
329 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1232 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T11 |
1 |
| others[1] |
1251 |
1 |
|
T2 |
5 |
|
T8 |
1 |
|
T39 |
23 |
| others[2] |
1201 |
1 |
|
T2 |
3 |
|
T39 |
15 |
|
T9 |
1 |
| others[3] |
2007 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T15 |
1 |
| false |
643 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T39 |
9 |
| true |
297 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T7 |
1 |
|
T39 |
3 |
|
T355 |
1 |
| others[1] |
111 |
1 |
|
T16 |
1 |
|
T39 |
3 |
|
T32 |
1 |
| others[2] |
85 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T39 |
4 |
| others[3] |
169 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T33 |
1 |
| false |
43 |
1 |
|
T16 |
1 |
|
T39 |
2 |
|
T146 |
2 |
| true |
6124 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T39 |
9 |
|
T12 |
1 |
|
T222 |
1 |
| others[1] |
197 |
1 |
|
T39 |
7 |
|
T146 |
6 |
|
T108 |
1 |
| others[2] |
220 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T39 |
9 |
| others[3] |
398 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T39 |
14 |
| false |
121 |
1 |
|
T6 |
1 |
|
T39 |
5 |
|
T146 |
3 |
| true |
5455 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1105 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| others[1] |
1009 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T39 |
23 |
| others[2] |
997 |
1 |
|
T2 |
4 |
|
T39 |
20 |
|
T69 |
1 |
| others[3] |
1702 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| false |
543 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T17 |
1 |
| true |
1275 |
1 |
|
T4 |
1 |
|
T13 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T39 |
12 |
|
T84 |
1 |
|
T45 |
1 |
| others[1] |
232 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T39 |
13 |
| others[2] |
212 |
1 |
|
T33 |
1 |
|
T39 |
5 |
|
T85 |
1 |
| others[3] |
358 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T15 |
1 |
| false |
122 |
1 |
|
T39 |
5 |
|
T59 |
1 |
|
T32 |
1 |
| true |
5507 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T33 |
1 |
| others[1] |
217 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T222 |
1 |
| others[2] |
200 |
1 |
|
T39 |
10 |
|
T206 |
1 |
|
T355 |
1 |
| others[3] |
383 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T39 |
14 |
| false |
113 |
1 |
|
T39 |
4 |
|
T46 |
1 |
|
T146 |
4 |
| true |
5497 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1140 |
1 |
|
T11 |
1 |
|
T39 |
16 |
|
T40 |
1 |
| others[1] |
1230 |
1 |
|
T2 |
4 |
|
T16 |
1 |
|
T39 |
25 |
| others[2] |
1241 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T15 |
1 |
| others[3] |
2079 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T8 |
1 |
| false |
610 |
1 |
|
T2 |
1 |
|
T39 |
6 |
|
T9 |
1 |
| true |
331 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T2 |
3 |
|
T39 |
18 |
|
T40 |
5 |
| others[1] |
1249 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T39 |
20 |
| others[2] |
1230 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T8 |
1 |
| others[3] |
2005 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T5 |
1 |
| false |
623 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T33 |
1 |
| true |
293 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T39 |
5 |
| others[1] |
100 |
1 |
|
T39 |
3 |
|
T146 |
3 |
|
T354 |
1 |
| others[2] |
119 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| others[3] |
176 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| false |
41 |
1 |
|
T39 |
2 |
|
T146 |
3 |
|
T108 |
1 |
| true |
6089 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T16 |
1 |
|
T39 |
6 |
|
T75 |
1 |
| others[1] |
240 |
1 |
|
T6 |
1 |
|
T39 |
13 |
|
T222 |
1 |
| others[2] |
247 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T39 |
15 |
| others[3] |
349 |
1 |
|
T11 |
1 |
|
T39 |
18 |
|
T85 |
1 |
| false |
121 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T39 |
4 |
| true |
5464 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1000 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| others[1] |
1097 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T11 |
1 |
| others[2] |
952 |
1 |
|
T2 |
2 |
|
T39 |
22 |
|
T40 |
2 |
| others[3] |
1763 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T17 |
1 |
| false |
517 |
1 |
|
T39 |
11 |
|
T40 |
2 |
|
T96 |
3 |
| true |
1302 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T6 |
1 |
|
T39 |
10 |
|
T32 |
1 |
| others[1] |
209 |
1 |
|
T11 |
1 |
|
T39 |
13 |
|
T146 |
13 |
| others[2] |
230 |
1 |
|
T39 |
11 |
|
T146 |
11 |
|
T161 |
1 |
| others[3] |
385 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T13 |
1 |
| false |
108 |
1 |
|
T39 |
1 |
|
T85 |
1 |
|
T268 |
1 |
| true |
5466 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T39 |
9 |
|
T146 |
12 |
|
T163 |
1 |
| others[1] |
220 |
1 |
|
T16 |
2 |
|
T39 |
12 |
|
T268 |
1 |
| others[2] |
193 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T39 |
8 |
| others[3] |
372 |
1 |
|
T7 |
1 |
|
T39 |
15 |
|
T206 |
1 |
| false |
121 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T39 |
5 |
| true |
5526 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1136 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T5 |
1 |
| others[1] |
1255 |
1 |
|
T2 |
1 |
|
T11 |
2 |
|
T39 |
30 |
| others[2] |
1171 |
1 |
|
T2 |
2 |
|
T39 |
12 |
|
T75 |
1 |
| others[3] |
2062 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T16 |
2 |
| false |
689 |
1 |
|
T33 |
1 |
|
T39 |
5 |
|
T96 |
11 |
| true |
318 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T33 |
1 |
| others[1] |
1290 |
1 |
|
T2 |
1 |
|
T39 |
19 |
|
T9 |
1 |
| others[2] |
1200 |
1 |
|
T2 |
1 |
|
T11 |
2 |
|
T15 |
1 |
| others[3] |
2052 |
1 |
|
T2 |
7 |
|
T16 |
2 |
|
T39 |
32 |
| false |
596 |
1 |
|
T2 |
2 |
|
T39 |
6 |
|
T40 |
3 |
| true |
289 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T39 |
6 |
|
T355 |
1 |
|
T146 |
3 |
| others[1] |
114 |
1 |
|
T11 |
1 |
|
T39 |
5 |
|
T222 |
1 |
| others[2] |
116 |
1 |
|
T11 |
1 |
|
T39 |
1 |
|
T355 |
1 |
| others[3] |
162 |
1 |
|
T15 |
1 |
|
T33 |
1 |
|
T16 |
2 |
| false |
56 |
1 |
|
T39 |
2 |
|
T146 |
2 |
|
T108 |
2 |
| true |
6095 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T33 |
1 |
|
T39 |
7 |
|
T69 |
1 |
| others[1] |
266 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T224 |
1 |
| others[2] |
212 |
1 |
|
T39 |
11 |
|
T32 |
1 |
|
T46 |
1 |
| others[3] |
401 |
1 |
|
T11 |
1 |
|
T13 |
1 |
|
T39 |
21 |
| false |
130 |
1 |
|
T39 |
8 |
|
T206 |
1 |
|
T146 |
3 |
| true |
5394 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1102 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
1 |
| others[1] |
1015 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| others[2] |
968 |
1 |
|
T2 |
5 |
|
T8 |
1 |
|
T39 |
16 |
| others[3] |
1717 |
1 |
|
T2 |
4 |
|
T11 |
2 |
|
T33 |
1 |
| false |
534 |
1 |
|
T15 |
1 |
|
T39 |
11 |
|
T40 |
1 |
| true |
1295 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T39 |
12 |
|
T222 |
1 |
|
T146 |
15 |
| others[1] |
225 |
1 |
|
T3 |
1 |
|
T39 |
6 |
|
T84 |
1 |
| others[2] |
237 |
1 |
|
T39 |
9 |
|
T85 |
1 |
|
T355 |
1 |
| others[3] |
346 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| false |
111 |
1 |
|
T15 |
1 |
|
T39 |
5 |
|
T146 |
5 |
| true |
5486 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T11 |
1 |
|
T39 |
11 |
|
T146 |
14 |
| others[1] |
204 |
1 |
|
T6 |
1 |
|
T39 |
6 |
|
T69 |
1 |
| others[2] |
230 |
1 |
|
T39 |
19 |
|
T355 |
1 |
|
T146 |
11 |
| others[3] |
368 |
1 |
|
T7 |
1 |
|
T16 |
2 |
|
T39 |
21 |
| false |
108 |
1 |
|
T39 |
2 |
|
T146 |
1 |
|
T149 |
4 |
| true |
5514 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| others[1] |
1227 |
1 |
|
T2 |
3 |
|
T4 |
1 |
|
T33 |
1 |
| others[2] |
1206 |
1 |
|
T2 |
5 |
|
T8 |
1 |
|
T39 |
17 |
| others[3] |
2028 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T6 |
1 |
| false |
624 |
1 |
|
T11 |
1 |
|
T39 |
14 |
|
T40 |
1 |
| true |
313 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T8 |
1 |
| others[1] |
1222 |
1 |
|
T2 |
3 |
|
T39 |
16 |
|
T40 |
2 |
| others[2] |
1210 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
2073 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T11 |
1 |
| false |
603 |
1 |
|
T2 |
1 |
|
T39 |
13 |
|
T9 |
1 |
| true |
289 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T33 |
1 |
|
T16 |
1 |
|
T39 |
4 |
| others[1] |
103 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
4 |
| others[2] |
101 |
1 |
|
T11 |
1 |
|
T39 |
1 |
|
T222 |
2 |
| others[3] |
200 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T15 |
1 |
| false |
64 |
1 |
|
T3 |
1 |
|
T39 |
1 |
|
T146 |
4 |
| true |
6070 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T33 |
1 |
|
T39 |
10 |
|
T75 |
1 |
| others[1] |
213 |
1 |
|
T39 |
8 |
|
T224 |
1 |
|
T46 |
1 |
| others[2] |
268 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T84 |
1 |
| others[3] |
357 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T13 |
1 |
| false |
114 |
1 |
|
T16 |
1 |
|
T39 |
11 |
|
T146 |
9 |
| true |
5467 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1024 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T8 |
1 |
| others[1] |
1074 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T16 |
1 |
| others[2] |
1006 |
1 |
|
T2 |
4 |
|
T7 |
1 |
|
T15 |
1 |
| others[3] |
1673 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T11 |
2 |
| false |
544 |
1 |
|
T2 |
2 |
|
T39 |
8 |
|
T40 |
2 |
| true |
1310 |
1 |
|
T4 |
1 |
|
T13 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T11 |
1 |
|
T39 |
7 |
|
T59 |
1 |
| others[1] |
218 |
1 |
|
T39 |
9 |
|
T146 |
12 |
|
T108 |
2 |
| others[2] |
215 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T39 |
13 |
| others[3] |
424 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T39 |
14 |
| false |
106 |
1 |
|
T15 |
1 |
|
T39 |
5 |
|
T32 |
1 |
| true |
5459 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T39 |
16 |
| others[1] |
212 |
1 |
|
T39 |
6 |
|
T146 |
10 |
|
T159 |
1 |
| others[2] |
220 |
1 |
|
T39 |
11 |
|
T32 |
1 |
|
T46 |
1 |
| others[3] |
359 |
1 |
|
T39 |
19 |
|
T224 |
1 |
|
T146 |
13 |
| false |
116 |
1 |
|
T11 |
1 |
|
T39 |
6 |
|
T146 |
4 |
| true |
5507 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T8 |
1 |
| others[1] |
1204 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T39 |
16 |
| others[2] |
1194 |
1 |
|
T2 |
3 |
|
T33 |
1 |
|
T39 |
22 |
| others[3] |
1985 |
1 |
|
T2 |
6 |
|
T11 |
2 |
|
T15 |
1 |
| false |
643 |
1 |
|
T6 |
1 |
|
T39 |
8 |
|
T40 |
1 |
| true |
320 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |