Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T15 |
1 |
| others[1] |
1302 |
1 |
|
T2 |
3 |
|
T33 |
1 |
|
T5 |
1 |
| others[2] |
1167 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T16 |
1 |
| others[3] |
1984 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T11 |
1 |
| false |
622 |
1 |
|
T2 |
1 |
|
T39 |
10 |
|
T40 |
1 |
| true |
291 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| others[1] |
114 |
1 |
|
T15 |
1 |
|
T39 |
3 |
|
T355 |
1 |
| others[2] |
94 |
1 |
|
T39 |
3 |
|
T146 |
3 |
|
T108 |
1 |
| others[3] |
161 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
4 |
| false |
52 |
1 |
|
T39 |
3 |
|
T146 |
1 |
|
T108 |
1 |
| true |
6116 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T16 |
1 |
|
T39 |
7 |
|
T355 |
1 |
| others[1] |
203 |
1 |
|
T11 |
1 |
|
T39 |
9 |
|
T59 |
1 |
| others[2] |
237 |
1 |
|
T39 |
12 |
|
T146 |
9 |
|
T109 |
1 |
| others[3] |
381 |
1 |
|
T6 |
1 |
|
T39 |
16 |
|
T12 |
1 |
| false |
104 |
1 |
|
T39 |
6 |
|
T85 |
1 |
|
T222 |
1 |
| true |
5482 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1004 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T17 |
1 |
| others[1] |
1054 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T11 |
2 |
| others[2] |
984 |
1 |
|
T2 |
3 |
|
T39 |
21 |
|
T14 |
1 |
| others[3] |
1731 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| false |
528 |
1 |
|
T2 |
5 |
|
T16 |
1 |
|
T39 |
5 |
| true |
1330 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T39 |
8 |
|
T146 |
8 |
|
T159 |
1 |
| others[1] |
231 |
1 |
|
T3 |
1 |
|
T13 |
1 |
|
T39 |
9 |
| others[2] |
209 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T39 |
6 |
| others[3] |
379 |
1 |
|
T16 |
1 |
|
T39 |
15 |
|
T85 |
1 |
| false |
126 |
1 |
|
T39 |
5 |
|
T69 |
1 |
|
T146 |
5 |
| true |
5459 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T268 |
1 |
| others[1] |
236 |
1 |
|
T3 |
1 |
|
T39 |
12 |
|
T84 |
1 |
| others[2] |
205 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T146 |
5 |
| others[3] |
379 |
1 |
|
T15 |
1 |
|
T33 |
1 |
|
T39 |
15 |
| false |
116 |
1 |
|
T6 |
1 |
|
T39 |
2 |
|
T146 |
3 |
| true |
5484 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T33 |
1 |
|
T39 |
16 |
|
T40 |
1 |
| others[1] |
1174 |
1 |
|
T11 |
1 |
|
T39 |
21 |
|
T86 |
1 |
| others[2] |
1240 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T39 |
23 |
| others[3] |
2033 |
1 |
|
T2 |
7 |
|
T4 |
1 |
|
T6 |
1 |
| false |
624 |
1 |
|
T2 |
4 |
|
T8 |
1 |
|
T39 |
6 |
| true |
321 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T2 |
2 |
|
T7 |
1 |
|
T16 |
1 |
| others[1] |
1225 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T39 |
22 |
| others[2] |
1150 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T33 |
1 |
| others[3] |
2069 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T15 |
1 |
| false |
660 |
1 |
|
T2 |
1 |
|
T39 |
9 |
|
T96 |
8 |
| true |
296 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T33 |
1 |
|
T39 |
5 |
|
T45 |
1 |
| others[1] |
95 |
1 |
|
T39 |
7 |
|
T222 |
1 |
|
T146 |
2 |
| others[2] |
113 |
1 |
|
T3 |
1 |
|
T39 |
5 |
|
T206 |
1 |
| others[3] |
167 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| false |
47 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T355 |
1 |
| true |
6105 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T13 |
1 |
| others[1] |
205 |
1 |
|
T6 |
1 |
|
T39 |
20 |
|
T146 |
3 |
| others[2] |
224 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T39 |
9 |
| others[3] |
356 |
1 |
|
T11 |
1 |
|
T39 |
14 |
|
T84 |
1 |
| false |
128 |
1 |
|
T39 |
2 |
|
T32 |
1 |
|
T146 |
5 |
| true |
5475 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1021 |
1 |
|
T2 |
2 |
|
T33 |
1 |
|
T23 |
1 |
| others[1] |
1031 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T16 |
1 |
| others[2] |
1038 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T5 |
1 |
| others[3] |
1717 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T15 |
1 |
| false |
518 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T39 |
14 |
| true |
1306 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T39 |
13 |
|
T69 |
1 |
|
T45 |
1 |
| others[1] |
239 |
1 |
|
T7 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| others[2] |
241 |
1 |
|
T39 |
12 |
|
T268 |
1 |
|
T46 |
1 |
| others[3] |
398 |
1 |
|
T39 |
22 |
|
T85 |
1 |
|
T224 |
1 |
| false |
107 |
1 |
|
T146 |
6 |
|
T169 |
1 |
|
T108 |
1 |
| true |
5416 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T16 |
1 |
|
T39 |
10 |
|
T85 |
1 |
| others[1] |
245 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T69 |
1 |
| others[2] |
197 |
1 |
|
T39 |
9 |
|
T45 |
1 |
|
T222 |
1 |
| others[3] |
356 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T39 |
13 |
| false |
100 |
1 |
|
T17 |
1 |
|
T39 |
4 |
|
T146 |
3 |
| true |
5512 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T33 |
1 |
| others[1] |
1230 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T39 |
22 |
| others[2] |
1246 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
2017 |
1 |
|
T2 |
6 |
|
T15 |
1 |
|
T5 |
1 |
| false |
626 |
1 |
|
T39 |
16 |
|
T40 |
1 |
|
T14 |
1 |
| true |
305 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| others[1] |
1209 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T39 |
19 |
| others[2] |
1218 |
1 |
|
T2 |
5 |
|
T6 |
1 |
|
T11 |
1 |
| others[3] |
2012 |
1 |
|
T2 |
4 |
|
T11 |
1 |
|
T5 |
1 |
| false |
650 |
1 |
|
T39 |
9 |
|
T96 |
9 |
|
T147 |
10 |
| true |
296 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T11 |
2 |
|
T33 |
1 |
|
T39 |
4 |
| others[1] |
111 |
1 |
|
T16 |
2 |
|
T39 |
3 |
|
T222 |
1 |
| others[2] |
108 |
1 |
|
T39 |
3 |
|
T355 |
1 |
|
T146 |
3 |
| others[3] |
163 |
1 |
|
T15 |
1 |
|
T39 |
9 |
|
T32 |
1 |
| false |
53 |
1 |
|
T39 |
4 |
|
T146 |
1 |
|
T149 |
5 |
| true |
6089 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T39 |
6 |
|
T69 |
1 |
|
T146 |
4 |
| others[1] |
230 |
1 |
|
T7 |
1 |
|
T39 |
9 |
|
T84 |
1 |
| others[2] |
240 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T15 |
1 |
| others[3] |
365 |
1 |
|
T16 |
1 |
|
T39 |
18 |
|
T222 |
1 |
| false |
120 |
1 |
|
T39 |
3 |
|
T222 |
1 |
|
T146 |
3 |
| true |
5453 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1043 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
1036 |
1 |
|
T2 |
2 |
|
T7 |
1 |
|
T11 |
1 |
| others[2] |
1002 |
1 |
|
T6 |
1 |
|
T23 |
1 |
|
T39 |
17 |
| others[3] |
1689 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T15 |
1 |
| false |
492 |
1 |
|
T2 |
3 |
|
T39 |
8 |
|
T40 |
1 |
| true |
1369 |
1 |
|
T17 |
1 |
|
T13 |
1 |
|
T84 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T39 |
13 |
| others[1] |
218 |
1 |
|
T6 |
1 |
|
T39 |
11 |
|
T146 |
12 |
| others[2] |
226 |
1 |
|
T13 |
1 |
|
T39 |
9 |
|
T146 |
13 |
| others[3] |
384 |
1 |
|
T11 |
1 |
|
T33 |
1 |
|
T39 |
16 |
| false |
122 |
1 |
|
T39 |
2 |
|
T69 |
1 |
|
T268 |
1 |
| true |
5453 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T39 |
13 |
| others[1] |
213 |
1 |
|
T11 |
1 |
|
T39 |
9 |
|
T146 |
8 |
| others[2] |
218 |
1 |
|
T39 |
11 |
|
T69 |
1 |
|
T146 |
6 |
| others[3] |
344 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| false |
130 |
1 |
|
T15 |
1 |
|
T39 |
4 |
|
T32 |
1 |
| true |
5491 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T15 |
1 |
| others[1] |
1201 |
1 |
|
T2 |
4 |
|
T16 |
1 |
|
T39 |
24 |
| others[2] |
1211 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T39 |
17 |
| others[3] |
1983 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T33 |
1 |
| false |
645 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T39 |
11 |
| true |
312 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T2 |
2 |
|
T39 |
15 |
|
T40 |
5 |
| others[1] |
1228 |
1 |
|
T2 |
2 |
|
T39 |
14 |
|
T9 |
1 |
| others[2] |
1241 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T39 |
27 |
| others[3] |
2035 |
1 |
|
T2 |
6 |
|
T4 |
1 |
|
T11 |
2 |
| false |
600 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T39 |
9 |
| true |
287 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T39 |
3 |
| others[1] |
94 |
1 |
|
T11 |
2 |
|
T39 |
2 |
|
T46 |
1 |
| others[2] |
104 |
1 |
|
T16 |
1 |
|
T39 |
2 |
|
T355 |
1 |
| others[3] |
172 |
1 |
|
T33 |
1 |
|
T39 |
6 |
|
T69 |
1 |
| false |
50 |
1 |
|
T39 |
2 |
|
T146 |
2 |
|
T280 |
1 |
| true |
6103 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T13 |
1 |
| others[1] |
220 |
1 |
|
T39 |
9 |
|
T46 |
1 |
|
T146 |
14 |
| others[2] |
225 |
1 |
|
T39 |
10 |
|
T69 |
1 |
|
T45 |
1 |
| others[3] |
400 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T39 |
20 |
| false |
121 |
1 |
|
T39 |
2 |
|
T222 |
1 |
|
T146 |
4 |
| true |
5419 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
998 |
1 |
|
T2 |
2 |
|
T39 |
16 |
|
T9 |
1 |
| others[1] |
971 |
1 |
|
T2 |
3 |
|
T33 |
1 |
|
T5 |
1 |
| others[2] |
1042 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T7 |
1 |
| others[3] |
1722 |
1 |
|
T2 |
4 |
|
T11 |
2 |
|
T15 |
1 |
| false |
558 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T39 |
12 |
| true |
1340 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T39 |
5 |
|
T59 |
1 |
|
T146 |
10 |
| others[1] |
242 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| others[2] |
217 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T39 |
14 |
| others[3] |
349 |
1 |
|
T33 |
1 |
|
T16 |
1 |
|
T39 |
14 |
| false |
111 |
1 |
|
T39 |
7 |
|
T84 |
1 |
|
T85 |
1 |
| true |
5486 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T16 |
1 |
|
T39 |
9 |
|
T69 |
1 |
| others[1] |
248 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T33 |
1 |
| others[2] |
231 |
1 |
|
T39 |
12 |
|
T84 |
1 |
|
T46 |
1 |
| others[3] |
382 |
1 |
|
T11 |
1 |
|
T39 |
17 |
|
T32 |
1 |
| false |
124 |
1 |
|
T39 |
7 |
|
T146 |
3 |
|
T149 |
7 |
| true |
5448 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1165 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T39 |
14 |
| others[1] |
1246 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| others[2] |
1195 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T16 |
1 |
| others[3] |
2031 |
1 |
|
T2 |
7 |
|
T11 |
1 |
|
T15 |
1 |
| false |
670 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T33 |
1 |
| true |
324 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8 |
1 |
|
T73 |
1 |
|
T133 |
1 |
|
T127 |
1 |
| others[1] |
7 |
1 |
|
T132 |
1 |
|
T126 |
1 |
|
T145 |
1 |
| others[2] |
3 |
1 |
|
T356 |
1 |
|
T37 |
1 |
|
T357 |
1 |
| others[3] |
4 |
1 |
|
T358 |
1 |
|
T38 |
1 |
|
T137 |
1 |
| false |
2 |
1 |
|
T359 |
1 |
|
T360 |
1 |
|
- |
- |
| true |
36 |
1 |
|
T30 |
1 |
|
T131 |
1 |
|
T111 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T88 |
1 |
|
T361 |
1 |
|
T362 |
1 |
| others[1] |
1 |
1 |
|
T363 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
4 |
1 |
|
T364 |
1 |
|
T365 |
1 |
|
T366 |
1 |
| others[3] |
3 |
1 |
|
T92 |
1 |
|
T367 |
1 |
|
T368 |
1 |
| false |
10 |
1 |
|
T94 |
1 |
|
T369 |
1 |
|
T370 |
1 |
| true |
28 |
1 |
|
T87 |
1 |
|
T351 |
1 |
|
T93 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T351 |
1 |
|
T367 |
1 |
|
T362 |
1 |
| others[1] |
1 |
1 |
|
T371 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
5 |
1 |
|
T93 |
1 |
|
T370 |
1 |
|
T372 |
1 |
| others[3] |
4 |
1 |
|
T373 |
1 |
|
T374 |
1 |
|
T375 |
1 |
| false |
9 |
1 |
|
T87 |
1 |
|
T88 |
1 |
|
T376 |
1 |
| true |
28 |
1 |
|
T94 |
1 |
|
T92 |
1 |
|
T369 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |