Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11285 |
1 |
|
T2 |
6 |
|
T11 |
1 |
|
T22 |
2 |
| others[1] |
778 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| others[2] |
786 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T39 |
25 |
| others[3] |
1279 |
1 |
|
T2 |
5 |
|
T6 |
1 |
|
T33 |
1 |
| false |
380 |
1 |
|
T2 |
1 |
|
T39 |
10 |
|
T146 |
9 |
| true |
392 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2573 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T39 |
8 |
| others[1] |
2571 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T33 |
1 |
| others[2] |
2646 |
1 |
|
T2 |
4 |
|
T22 |
1 |
|
T39 |
9 |
| others[3] |
4295 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T11 |
2 |
| false |
1335 |
1 |
|
T2 |
2 |
|
T39 |
8 |
|
T24 |
1 |
| true |
1480 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10763 |
1 |
|
T16 |
1 |
|
T22 |
2 |
|
T39 |
9 |
| others[1] |
250 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| others[2] |
234 |
1 |
|
T16 |
1 |
|
T13 |
1 |
|
T39 |
6 |
| others[3] |
430 |
1 |
|
T39 |
12 |
|
T14 |
1 |
|
T12 |
1 |
| false |
114 |
1 |
|
T3 |
1 |
|
T39 |
4 |
|
T69 |
1 |
| true |
3109 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10983 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T22 |
2 |
| others[1] |
463 |
1 |
|
T16 |
2 |
|
T39 |
14 |
|
T40 |
1 |
| others[2] |
429 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
700 |
1 |
|
T2 |
5 |
|
T8 |
1 |
|
T39 |
12 |
| false |
232 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T39 |
4 |
| true |
2093 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10726 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T22 |
2 |
| others[1] |
242 |
1 |
|
T6 |
1 |
|
T39 |
8 |
|
T168 |
1 |
| others[2] |
250 |
1 |
|
T39 |
8 |
|
T268 |
1 |
|
T146 |
14 |
| others[3] |
405 |
1 |
|
T11 |
2 |
|
T15 |
1 |
|
T17 |
1 |
| false |
130 |
1 |
|
T7 |
1 |
|
T39 |
8 |
|
T146 |
1 |
| true |
3147 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10732 |
1 |
|
T7 |
1 |
|
T33 |
1 |
|
T22 |
2 |
| others[1] |
252 |
1 |
|
T8 |
1 |
|
T39 |
10 |
|
T84 |
1 |
| others[2] |
235 |
1 |
|
T39 |
9 |
|
T9 |
1 |
|
T168 |
1 |
| others[3] |
436 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| false |
136 |
1 |
|
T17 |
1 |
|
T16 |
1 |
|
T39 |
5 |
| true |
3109 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11297 |
1 |
|
T2 |
1 |
|
T22 |
2 |
|
T39 |
22 |
| others[1] |
772 |
1 |
|
T2 |
5 |
|
T6 |
1 |
|
T39 |
17 |
| others[2] |
753 |
1 |
|
T2 |
2 |
|
T8 |
1 |
|
T39 |
24 |
| others[3] |
1282 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T16 |
1 |
| false |
405 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T39 |
12 |
| true |
391 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11294 |
1 |
|
T2 |
2 |
|
T4 |
1 |
|
T7 |
1 |
| others[1] |
780 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T39 |
20 |
| others[2] |
772 |
1 |
|
T2 |
3 |
|
T39 |
21 |
|
T40 |
4 |
| others[3] |
1296 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T8 |
1 |
| false |
346 |
1 |
|
T2 |
2 |
|
T39 |
12 |
|
T40 |
1 |
| true |
386 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2572 |
1 |
|
T2 |
3 |
|
T7 |
1 |
|
T16 |
1 |
| others[1] |
2619 |
1 |
|
T2 |
1 |
|
T39 |
9 |
|
T45 |
1 |
| others[2] |
2427 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| others[3] |
4505 |
1 |
|
T2 |
7 |
|
T11 |
2 |
|
T15 |
1 |
| false |
1302 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T22 |
1 |
| true |
1449 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10755 |
1 |
|
T22 |
2 |
|
T13 |
1 |
|
T39 |
12 |
| others[1] |
237 |
1 |
|
T3 |
1 |
|
T39 |
8 |
|
T222 |
1 |
| others[2] |
274 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T39 |
13 |
| others[3] |
453 |
1 |
|
T11 |
1 |
|
T39 |
14 |
|
T268 |
1 |
| false |
137 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T39 |
5 |
| true |
3018 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10900 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| others[1] |
458 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T39 |
7 |
| others[2] |
433 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T8 |
1 |
| others[3] |
686 |
1 |
|
T2 |
5 |
|
T6 |
1 |
|
T33 |
1 |
| false |
228 |
1 |
|
T2 |
1 |
|
T39 |
4 |
|
T31 |
1 |
| true |
2169 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10745 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T22 |
2 |
| others[1] |
261 |
1 |
|
T39 |
5 |
|
T222 |
1 |
|
T146 |
6 |
| others[2] |
256 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T39 |
12 |
| others[3] |
379 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T39 |
13 |
| false |
127 |
1 |
|
T33 |
1 |
|
T39 |
4 |
|
T32 |
1 |
| true |
3106 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10716 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T5 |
1 |
| others[1] |
255 |
1 |
|
T6 |
1 |
|
T39 |
8 |
|
T32 |
1 |
| others[2] |
243 |
1 |
|
T39 |
10 |
|
T69 |
1 |
|
T84 |
1 |
| others[3] |
404 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| false |
140 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T39 |
3 |
| true |
3116 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11258 |
1 |
|
T2 |
4 |
|
T33 |
1 |
|
T22 |
2 |
| others[1] |
768 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T11 |
1 |
| others[2] |
770 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T5 |
1 |
| others[3] |
1288 |
1 |
|
T2 |
3 |
|
T39 |
32 |
|
T40 |
9 |
| false |
402 |
1 |
|
T2 |
1 |
|
T39 |
11 |
|
T86 |
1 |
| true |
388 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11290 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T22 |
2 |
| others[1] |
781 |
1 |
|
T2 |
5 |
|
T7 |
1 |
|
T5 |
1 |
| others[2] |
731 |
1 |
|
T2 |
2 |
|
T33 |
1 |
|
T8 |
1 |
| others[3] |
1276 |
1 |
|
T2 |
2 |
|
T39 |
41 |
|
T40 |
6 |
| false |
402 |
1 |
|
T3 |
1 |
|
T39 |
5 |
|
T40 |
1 |
| true |
394 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2620 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T33 |
1 |
| others[1] |
2618 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T16 |
1 |
| others[2] |
2580 |
1 |
|
T2 |
2 |
|
T39 |
7 |
|
T9 |
1 |
| others[3] |
4277 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T6 |
1 |
| false |
1345 |
1 |
|
T2 |
2 |
|
T39 |
6 |
|
T96 |
7 |
| true |
1434 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10757 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T22 |
2 |
| others[1] |
258 |
1 |
|
T39 |
8 |
|
T146 |
16 |
|
T377 |
1 |
| others[2] |
230 |
1 |
|
T39 |
8 |
|
T206 |
1 |
|
T146 |
10 |
| others[3] |
466 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T39 |
12 |
| false |
138 |
1 |
|
T39 |
6 |
|
T12 |
1 |
|
T46 |
1 |
| true |
3025 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10917 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T16 |
1 |
| others[1] |
432 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T33 |
1 |
| others[2] |
438 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| others[3] |
752 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T15 |
1 |
| false |
265 |
1 |
|
T2 |
1 |
|
T39 |
5 |
|
T40 |
1 |
| true |
2070 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10759 |
1 |
|
T6 |
1 |
|
T22 |
2 |
|
T39 |
12 |
| others[1] |
257 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T16 |
1 |
| others[2] |
232 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T39 |
12 |
| others[3] |
428 |
1 |
|
T39 |
16 |
|
T146 |
11 |
|
T148 |
2 |
| false |
108 |
1 |
|
T11 |
1 |
|
T39 |
1 |
|
T268 |
1 |
| true |
3090 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10735 |
1 |
|
T33 |
1 |
|
T22 |
2 |
|
T39 |
10 |
| others[1] |
220 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T39 |
14 |
| others[2] |
224 |
1 |
|
T39 |
9 |
|
T146 |
7 |
|
T159 |
1 |
| others[3] |
424 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| false |
116 |
1 |
|
T15 |
1 |
|
T39 |
6 |
|
T146 |
5 |
| true |
3155 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11235 |
1 |
|
T2 |
4 |
|
T7 |
1 |
|
T22 |
2 |
| others[1] |
794 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T16 |
1 |
| others[2] |
763 |
1 |
|
T2 |
2 |
|
T39 |
21 |
|
T40 |
3 |
| others[3] |
1283 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T15 |
1 |
| false |
413 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T39 |
11 |
| true |
386 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11271 |
1 |
|
T2 |
3 |
|
T22 |
2 |
|
T39 |
19 |
| others[1] |
783 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T39 |
23 |
| others[2] |
743 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T8 |
1 |
| others[3] |
1278 |
1 |
|
T2 |
4 |
|
T7 |
1 |
|
T39 |
28 |
| false |
401 |
1 |
|
T39 |
9 |
|
T40 |
2 |
|
T355 |
1 |
| true |
398 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2551 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T16 |
1 |
| others[1] |
2659 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T11 |
1 |
| others[2] |
2514 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T96 |
20 |
| others[3] |
4338 |
1 |
|
T2 |
5 |
|
T17 |
1 |
|
T33 |
1 |
| false |
1362 |
1 |
|
T2 |
2 |
|
T39 |
7 |
|
T14 |
1 |
| true |
1450 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10736 |
1 |
|
T33 |
1 |
|
T22 |
2 |
|
T39 |
10 |
| others[1] |
246 |
1 |
|
T13 |
1 |
|
T39 |
8 |
|
T206 |
1 |
| others[2] |
249 |
1 |
|
T17 |
1 |
|
T39 |
9 |
|
T84 |
1 |
| others[3] |
406 |
1 |
|
T7 |
1 |
|
T5 |
1 |
|
T39 |
14 |
| false |
126 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T39 |
7 |
| true |
3111 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10941 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T16 |
2 |
| others[1] |
415 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T33 |
1 |
| others[2] |
445 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
738 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T7 |
1 |
| false |
232 |
1 |
|
T4 |
1 |
|
T39 |
5 |
|
T40 |
2 |
| true |
2103 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10736 |
1 |
|
T22 |
2 |
|
T39 |
10 |
|
T24 |
2 |
| others[1] |
242 |
1 |
|
T39 |
6 |
|
T9 |
1 |
|
T168 |
1 |
| others[2] |
263 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T39 |
12 |
| others[3] |
445 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| false |
119 |
1 |
|
T39 |
2 |
|
T378 |
1 |
|
T146 |
7 |
| true |
3069 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10728 |
1 |
|
T11 |
1 |
|
T22 |
2 |
|
T39 |
9 |
| others[1] |
253 |
1 |
|
T39 |
8 |
|
T268 |
1 |
|
T355 |
1 |
| others[2] |
261 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T39 |
9 |
| others[3] |
383 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T39 |
20 |
| false |
140 |
1 |
|
T39 |
9 |
|
T146 |
11 |
|
T158 |
1 |
| true |
3109 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11266 |
1 |
|
T11 |
1 |
|
T22 |
2 |
|
T39 |
19 |
| others[1] |
790 |
1 |
|
T2 |
3 |
|
T16 |
1 |
|
T39 |
21 |
| others[2] |
761 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T39 |
15 |
| others[3] |
1284 |
1 |
|
T2 |
5 |
|
T15 |
1 |
|
T16 |
1 |
| false |
409 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T8 |
1 |
| true |
364 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11285 |
1 |
|
T33 |
1 |
|
T22 |
2 |
|
T39 |
25 |
| others[1] |
792 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T16 |
1 |
| others[2] |
738 |
1 |
|
T5 |
1 |
|
T39 |
17 |
|
T9 |
1 |
| others[3] |
1272 |
1 |
|
T2 |
6 |
|
T11 |
1 |
|
T16 |
1 |
| false |
393 |
1 |
|
T2 |
4 |
|
T6 |
1 |
|
T39 |
10 |
| true |
394 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2634 |
1 |
|
T2 |
3 |
|
T22 |
1 |
|
T8 |
1 |
| others[1] |
2546 |
1 |
|
T2 |
4 |
|
T16 |
1 |
|
T39 |
12 |
| others[2] |
2569 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T39 |
11 |
| others[3] |
4316 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T15 |
1 |
| false |
1373 |
1 |
|
T39 |
4 |
|
T24 |
1 |
|
T86 |
1 |
| true |
1436 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10713 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T22 |
2 |
| others[1] |
244 |
1 |
|
T33 |
1 |
|
T39 |
11 |
|
T9 |
1 |
| others[2] |
274 |
1 |
|
T17 |
1 |
|
T16 |
1 |
|
T13 |
1 |
| others[3] |
451 |
1 |
|
T39 |
10 |
|
T14 |
1 |
|
T224 |
1 |
| false |
128 |
1 |
|
T11 |
1 |
|
T39 |
2 |
|
T146 |
8 |
| true |
3064 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |