Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10964 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[1] |
418 |
1 |
|
T2 |
2 |
|
T33 |
1 |
|
T39 |
10 |
| others[2] |
440 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T15 |
1 |
| others[3] |
728 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T16 |
1 |
| false |
223 |
1 |
|
T6 |
1 |
|
T39 |
6 |
|
T40 |
1 |
| true |
2101 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10721 |
1 |
|
T11 |
1 |
|
T22 |
2 |
|
T39 |
13 |
| others[1] |
253 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T39 |
13 |
| others[2] |
235 |
1 |
|
T16 |
1 |
|
T39 |
8 |
|
T69 |
1 |
| others[3] |
430 |
1 |
|
T39 |
19 |
|
T84 |
1 |
|
T32 |
1 |
| false |
140 |
1 |
|
T39 |
5 |
|
T146 |
8 |
|
T148 |
1 |
| true |
3095 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10734 |
1 |
|
T6 |
1 |
|
T22 |
2 |
|
T39 |
6 |
| others[1] |
215 |
1 |
|
T39 |
8 |
|
T268 |
1 |
|
T146 |
10 |
| others[2] |
247 |
1 |
|
T16 |
1 |
|
T39 |
5 |
|
T206 |
1 |
| others[3] |
404 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T39 |
16 |
| false |
132 |
1 |
|
T39 |
8 |
|
T146 |
4 |
|
T148 |
1 |
| true |
3142 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11241 |
1 |
|
T22 |
2 |
|
T39 |
14 |
|
T24 |
2 |
| others[1] |
764 |
1 |
|
T2 |
5 |
|
T16 |
1 |
|
T39 |
15 |
| others[2] |
779 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T15 |
1 |
| others[3] |
1304 |
1 |
|
T2 |
3 |
|
T39 |
35 |
|
T40 |
4 |
| false |
405 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T5 |
1 |
| true |
381 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11241 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T16 |
1 |
| others[1] |
762 |
1 |
|
T39 |
13 |
|
T40 |
1 |
|
T44 |
1 |
| others[2] |
781 |
1 |
|
T39 |
23 |
|
T69 |
1 |
|
T40 |
2 |
| others[3] |
1283 |
1 |
|
T2 |
10 |
|
T5 |
1 |
|
T8 |
1 |
| false |
390 |
1 |
|
T2 |
1 |
|
T39 |
11 |
|
T40 |
1 |
| true |
417 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2542 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T5 |
1 |
| others[1] |
2552 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T33 |
1 |
| others[2] |
2592 |
1 |
|
T2 |
4 |
|
T22 |
1 |
|
T39 |
8 |
| others[3] |
4351 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T7 |
1 |
| false |
1366 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T39 |
2 |
| true |
1471 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10758 |
1 |
|
T22 |
2 |
|
T39 |
4 |
|
T24 |
2 |
| others[1] |
251 |
1 |
|
T39 |
9 |
|
T32 |
1 |
|
T146 |
7 |
| others[2] |
289 |
1 |
|
T13 |
1 |
|
T39 |
6 |
|
T222 |
1 |
| others[3] |
418 |
1 |
|
T5 |
1 |
|
T16 |
2 |
|
T39 |
12 |
| false |
163 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T39 |
5 |
| true |
2995 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10930 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T22 |
2 |
| others[1] |
459 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T33 |
1 |
| others[2] |
444 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| others[3] |
731 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T13 |
1 |
| false |
243 |
1 |
|
T39 |
3 |
|
T91 |
1 |
|
T110 |
1 |
| true |
2067 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10740 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T22 |
2 |
| others[1] |
236 |
1 |
|
T3 |
1 |
|
T39 |
7 |
|
T268 |
1 |
| others[2] |
227 |
1 |
|
T11 |
2 |
|
T39 |
13 |
|
T9 |
1 |
| others[3] |
429 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T39 |
18 |
| false |
97 |
1 |
|
T39 |
2 |
|
T146 |
4 |
|
T158 |
1 |
| true |
3145 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10758 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T5 |
1 |
| others[1] |
248 |
1 |
|
T16 |
1 |
|
T39 |
10 |
|
T269 |
1 |
| others[2] |
243 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T33 |
1 |
| others[3] |
405 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| false |
132 |
1 |
|
T39 |
9 |
|
T14 |
1 |
|
T146 |
2 |
| true |
3088 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11269 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T5 |
1 |
| others[1] |
798 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T33 |
1 |
| others[2] |
793 |
1 |
|
T2 |
5 |
|
T16 |
1 |
|
T39 |
14 |
| others[3] |
1228 |
1 |
|
T2 |
5 |
|
T7 |
1 |
|
T16 |
1 |
| false |
397 |
1 |
|
T2 |
2 |
|
T11 |
1 |
|
T39 |
11 |
| true |
389 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11258 |
1 |
|
T2 |
2 |
|
T22 |
2 |
|
T39 |
17 |
| others[1] |
759 |
1 |
|
T2 |
5 |
|
T11 |
1 |
|
T15 |
1 |
| others[2] |
750 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T39 |
15 |
| others[3] |
1308 |
1 |
|
T2 |
3 |
|
T33 |
1 |
|
T5 |
1 |
| false |
398 |
1 |
|
T8 |
1 |
|
T39 |
16 |
|
T40 |
2 |
| true |
401 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2577 |
1 |
|
T2 |
2 |
|
T39 |
6 |
|
T9 |
1 |
| others[1] |
2560 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| others[2] |
2600 |
1 |
|
T2 |
7 |
|
T33 |
1 |
|
T39 |
14 |
| others[3] |
4354 |
1 |
|
T2 |
2 |
|
T7 |
1 |
|
T11 |
1 |
| false |
1333 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| true |
1450 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10747 |
1 |
|
T3 |
1 |
|
T11 |
1 |
|
T22 |
2 |
| others[1] |
276 |
1 |
|
T13 |
1 |
|
T39 |
9 |
|
T69 |
1 |
| others[2] |
276 |
1 |
|
T16 |
2 |
|
T39 |
4 |
|
T206 |
1 |
| others[3] |
424 |
1 |
|
T6 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| false |
123 |
1 |
|
T39 |
6 |
|
T355 |
1 |
|
T146 |
6 |
| true |
3028 |
1 |
|
T2 |
13 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10931 |
1 |
|
T5 |
1 |
|
T22 |
2 |
|
T39 |
9 |
| others[1] |
467 |
1 |
|
T2 |
3 |
|
T17 |
1 |
|
T33 |
1 |
| others[2] |
425 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T13 |
1 |
| others[3] |
731 |
1 |
|
T2 |
1 |
|
T11 |
2 |
|
T15 |
1 |
| false |
222 |
1 |
|
T7 |
1 |
|
T39 |
6 |
|
T40 |
1 |
| true |
2098 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10736 |
1 |
|
T22 |
2 |
|
T39 |
3 |
|
T24 |
2 |
| others[1] |
261 |
1 |
|
T39 |
9 |
|
T268 |
1 |
|
T46 |
1 |
| others[2] |
244 |
1 |
|
T39 |
9 |
|
T146 |
8 |
|
T159 |
1 |
| others[3] |
432 |
1 |
|
T11 |
1 |
|
T39 |
13 |
|
T14 |
1 |
| false |
149 |
1 |
|
T7 |
1 |
|
T39 |
5 |
|
T355 |
1 |
| true |
3052 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10748 |
1 |
|
T22 |
2 |
|
T39 |
12 |
|
T24 |
2 |
| others[1] |
247 |
1 |
|
T16 |
1 |
|
T39 |
7 |
|
T268 |
1 |
| others[2] |
236 |
1 |
|
T6 |
1 |
|
T39 |
15 |
|
T84 |
1 |
| others[3] |
403 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T39 |
16 |
| false |
137 |
1 |
|
T5 |
1 |
|
T39 |
5 |
|
T146 |
7 |
| true |
3103 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11247 |
1 |
|
T2 |
2 |
|
T22 |
2 |
|
T39 |
18 |
| others[1] |
761 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T39 |
22 |
| others[2] |
844 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T39 |
18 |
| others[3] |
1236 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T39 |
32 |
| false |
399 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| true |
387 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11291 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T16 |
2 |
| others[1] |
735 |
1 |
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
792 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T39 |
25 |
| others[3] |
1264 |
1 |
|
T2 |
6 |
|
T11 |
1 |
|
T33 |
1 |
| false |
398 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T39 |
7 |
| true |
394 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2631 |
1 |
|
T2 |
4 |
|
T33 |
1 |
|
T22 |
1 |
| others[1] |
2590 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| others[2] |
2552 |
1 |
|
T2 |
3 |
|
T11 |
1 |
|
T22 |
1 |
| others[3] |
4320 |
1 |
|
T2 |
5 |
|
T7 |
1 |
|
T11 |
1 |
| false |
1376 |
1 |
|
T17 |
1 |
|
T16 |
1 |
|
T39 |
5 |
| true |
1405 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10766 |
1 |
|
T33 |
1 |
|
T16 |
1 |
|
T22 |
2 |
| others[1] |
253 |
1 |
|
T7 |
1 |
|
T13 |
1 |
|
T39 |
8 |
| others[2] |
256 |
1 |
|
T39 |
5 |
|
T268 |
1 |
|
T10 |
1 |
| others[3] |
408 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T8 |
1 |
| false |
149 |
1 |
|
T17 |
1 |
|
T39 |
5 |
|
T84 |
1 |
| true |
3042 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10928 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T33 |
1 |
| others[1] |
416 |
1 |
|
T16 |
2 |
|
T39 |
9 |
|
T84 |
1 |
| others[2] |
450 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T17 |
1 |
| others[3] |
745 |
1 |
|
T2 |
2 |
|
T4 |
1 |
|
T15 |
1 |
| false |
219 |
1 |
|
T11 |
1 |
|
T39 |
3 |
|
T110 |
1 |
| true |
2116 |
1 |
|
T2 |
8 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10730 |
1 |
|
T16 |
1 |
|
T22 |
2 |
|
T39 |
15 |
| others[1] |
263 |
1 |
|
T11 |
1 |
|
T15 |
1 |
|
T33 |
1 |
| others[2] |
253 |
1 |
|
T7 |
1 |
|
T39 |
13 |
|
T59 |
1 |
| others[3] |
407 |
1 |
|
T6 |
1 |
|
T39 |
15 |
|
T45 |
1 |
| false |
122 |
1 |
|
T39 |
7 |
|
T146 |
5 |
|
T149 |
4 |
| true |
3099 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10712 |
1 |
|
T22 |
2 |
|
T39 |
7 |
|
T24 |
2 |
| others[1] |
255 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T39 |
14 |
| others[2] |
259 |
1 |
|
T11 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| others[3] |
410 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T39 |
23 |
| false |
134 |
1 |
|
T6 |
1 |
|
T39 |
5 |
|
T146 |
6 |
| true |
3104 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11254 |
1 |
|
T2 |
2 |
|
T22 |
2 |
|
T39 |
15 |
| others[1] |
771 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T15 |
1 |
| others[2] |
758 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T39 |
18 |
| others[3] |
1328 |
1 |
|
T2 |
7 |
|
T33 |
1 |
|
T39 |
36 |
| false |
380 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T16 |
1 |
| true |
383 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |