Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	198825	1		T2	138		T3	841		T4	8
auto[FlashEraseBank]	220423	1		T2	116		T3	1020		T4	9

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	231197	1		T4	12		T6	79		T7	1306
auto[FlashOpProgram]	166822	1		T2	254		T3	1861		T4	5
auto[FlashOpErase]	17229	1		T6	42		T33	1		T16	1
auto[FlashOpInvalid]	4000	1		T96	200		T147	200		T203	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	231197	1		T4	12		T6	79		T7	1306
op[FlashOpProgram]	166822	1		T2	254		T3	1861		T4	5
op[FlashOpErase]	17229	1		T6	42		T33	1		T16	1
read_erase_read	719	1		T6	6		T39	10		T87	2
read_prog_read	498	1		T6	10		T7	6		T39	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	289699	1		T2	254		T3	1649		T4	5
auto[FlashPartInfo]	126256	1		T3	203		T4	12		T6	7
auto[FlashPartInfo1]	838	1		T7	3		T17	1		T84	2
auto[FlashPartInfo2]	2455	1		T3	9		T7	19		T17	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	164796	1		T4	4		T6	76		T7	979
auto[FlashPartData]	auto[FlashOpProgram]	117205	1		T2	254		T3	1649		T4	1
auto[FlashPartData]	auto[FlashOpErase]	3784	1		T6	42		T33	1		T16	1
auto[FlashPartData]	auto[FlashOpInvalid]	3914	1		T96	192		T147	194		T203	198
auto[FlashPartInfo]	auto[FlashOpRead]	64008	1		T4	8		T6	3		T7	314
auto[FlashPartInfo]	auto[FlashOpProgram]	48772	1		T3	203		T4	4		T6	4
auto[FlashPartInfo]	auto[FlashOpErase]	13402	1		T39	19		T87	11		T96	4
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T96	8		T147	6		T203	2
auto[FlashPartInfo1]	auto[FlashOpRead]	669	1		T7	3		T17	1		T84	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T170	32		T172	32		T173	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T146	1		T152	2		T381	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T381	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1724	1		T7	10		T17	10		T13	35
auto[FlashPartInfo2]	auto[FlashOpProgram]	682	1		T3	9		T7	9		T32	11
auto[FlashPartInfo2]	auto[FlashOpErase]	39	1		T146	1		T165	1		T171	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T165	2		T382	2		T383	2