Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	6	26	81.25

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	6	26	81.25	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33184	1		T6	40		T39	4		T86	1
auto[1]	12	1		T325	8		T326	4		-	-
auto[2]	18	1		T7	1		T40	4		T179	4
auto[3]	32	1		T75	1		T12	1		T79	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8315	1		T6	10		T7	1		T39	1
evic_idx[1]	8315	1		T6	10		T39	1		T40	1
evic_idx[2]	8309	1		T6	10		T39	1		T40	1
evic_idx[3]	8307	1		T6	10		T39	1		T40	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32372	1		T96	400		T147	400		T191	4
evic_op[2]	282	1		T7	1		T39	4		T75	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	6	26	81.25	6

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1] , evic_idx[2]]	*	[auto[2]]	--	--	4

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[3]]	[evic_op[1]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8088	1		T96	100		T147	100		T191	1
evic_idx[0]	evic_op[1]	auto[1]	1	1		T326	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	2	1		T327	1		T328	1		-	-
evic_idx[0]	evic_op[2]	auto[0]	67	1		T39	1		T86	1		T44	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T325	2		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T7	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	6	1		T77	1		T188	1		T176	1
evic_idx[1]	evic_op[1]	auto[0]	8090	1		T96	100		T147	100		T191	1
evic_idx[1]	evic_op[1]	auto[1]	1	1		T326	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	4	1		T327	1		T329	1		T328	2
evic_idx[1]	evic_op[2]	auto[0]	65	1		T39	1		T44	4		T149	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T325	2		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	5	1		T75	1		T330	1		T331	1
evic_idx[2]	evic_op[1]	auto[0]	8088	1		T96	100		T147	100		T191	1
evic_idx[2]	evic_op[1]	auto[1]	1	1		T326	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	5	1		T79	1		T327	1		T329	1
evic_idx[2]	evic_op[2]	auto[0]	61	1		T39	1		T44	4		T28	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T325	2		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	4	1		T78	1		T332	1		T333	1
evic_idx[3]	evic_op[1]	auto[0]	8088	1		T96	100		T147	100		T191	1
evic_idx[3]	evic_op[1]	auto[1]	1	1		T326	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	3	1		T79	1		T328	2		-	-
evic_idx[3]	evic_op[2]	auto[0]	61	1		T39	1		T44	4		T149	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T325	2		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T334	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	3	1		T12	1		T188	1		T335	1