Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	11396	1		T312	8753		T313	2643		-	-
rd_lvl[2]	31068	1		T314	5366		T315	6036		T312	4815
rd_lvl[3]	11536	1		T5	2468		T316	2615		T314	441
rd_lvl[4]	31501	1		T5	1442		T13	2924		T158	3316
rd_lvl[5]	21377	1		T13	1300		T317	921		T318	1695
rd_lvl[6]	16398	1		T161	1284		T27	1000		T318	1137
rd_lvl[7]	11813	1		T13	10		T59	1198		T161	521
rd_lvl[8]	16269	1		T59	892		T319	618		T292	762
rd_lvl[9]	8063	1		T14	208		T59	65		T161	115
rd_lvl[10]	5304	1		T14	530		T59	65		T161	115
rd_lvl[11]	4913	1		T81	529		T320	345		T202	46
rd_lvl[12]	6234	1		T13	10		T80	77		T81	289
rd_lvl[13]	4964	1		T321	561		T322	485		T323	388
rd_lvl[14]	2814	1		T81	66		T324	535		T322	267
rd_lvl[15]	3210	1		T82	566		T321	78		T324	208