Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	260437	1		T1	1		T2	1		T3	2
all_pins[1]	260437	1		T1	1		T2	1		T3	2
all_pins[2]	260437	1		T1	1		T2	1		T3	2
all_pins[3]	260437	1		T1	1		T2	1		T3	2
all_pins[4]	260437	1		T1	1		T2	1		T3	2
all_pins[5]	260437	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1289044	1		T1	6		T2	6		T3	12
values[0x1]	273578	1		T5	4987		T13	5328		T14	1476
transitions[0x0=>0x1]	244716	1		T5	4692		T13	4295		T14	1476
transitions[0x1=>0x0]	244705	1		T5	4692		T13	4295		T14	1476

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	260276	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	161	1		T247	7		T248	7		T249	2
all_pins[0]	transitions[0x0=>0x1]	83	1		T247	3		T248	6		T249	1
all_pins[0]	transitions[0x1=>0x0]	80	1		T248	1		T249	5		T305	1
all_pins[1]	values[0x0]	260279	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	158	1		T247	4		T248	2		T249	6
all_pins[1]	transitions[0x0=>0x1]	132	1		T247	4		T248	1		T249	6
all_pins[1]	transitions[0x1=>0x0]	2071	1		T82	283		T338	464		T339	112
all_pins[2]	values[0x0]	258340	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	2097	1		T82	283		T338	464		T339	112
all_pins[2]	transitions[0x0=>0x1]	50	1		T247	2		T248	2		T249	1
all_pins[2]	transitions[0x1=>0x0]	188224	1		T5	3910		T13	4244		T14	738
all_pins[3]	values[0x0]	70166	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	190271	1		T5	3910		T13	4244		T14	738
all_pins[3]	transitions[0x0=>0x1]	163616	1		T5	3615		T13	3211		T14	738
all_pins[3]	transitions[0x1=>0x0]	54169	1		T5	782		T13	51		T14	738
all_pins[4]	values[0x0]	179613	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	80824	1		T5	1077		T13	1084		T14	738
all_pins[4]	transitions[0x0=>0x1]	80807	1		T5	1077		T13	1084		T14	738
all_pins[4]	transitions[0x1=>0x0]	50	1		T247	2		T248	1		T307	2
all_pins[5]	values[0x0]	260370	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	67	1		T247	4		T248	1		T307	2
all_pins[5]	transitions[0x0=>0x1]	28	1		T307	1		T308	1		T311	1
all_pins[5]	transitions[0x1=>0x0]	111	1		T247	2		T248	5		T249	2