Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T247	7		T248	7		T249	7
all_values[1]	284	1		T247	7		T248	7		T249	7
all_values[2]	284	1		T247	7		T248	7		T249	7
all_values[3]	284	1		T247	7		T248	7		T249	7
all_values[4]	284	1		T247	7		T248	7		T249	7
all_values[5]	284	1		T247	7		T248	7		T249	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	885	1		T247	16		T248	16		T249	29
auto[1]	819	1		T247	26		T248	26		T249	13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	579	1		T247	13		T248	18		T249	20
auto[1]	1125	1		T247	29		T248	24		T249	22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1007	1		T247	24		T248	28		T249	31
auto[1]	697	1		T247	18		T248	14		T249	11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T248	1		T249	5		T305	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1		T247	4		T248	2		T305	2
all_values[0]	auto[1]	auto[0]	auto[1]	57	1		T247	2		T249	1		T305	2
all_values[0]	auto[1]	auto[1]	auto[1]	56	1		T247	1		T248	4		T249	1
all_values[1]	auto[0]	auto[0]	auto[1]	75	1		T247	2		T248	3		T249	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1		T247	1		T248	2		T249	4
all_values[1]	auto[1]	auto[0]	auto[1]	73	1		T247	3		T248	2		T305	3
all_values[1]	auto[1]	auto[1]	auto[1]	60	1		T247	1		T249	2		T305	1
all_values[2]	auto[0]	auto[0]	auto[0]	80	1		T247	1		T248	1		T249	2
all_values[2]	auto[0]	auto[1]	auto[0]	87	1		T247	3		T248	2		T249	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T247	1		T248	2		T249	3
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T247	2		T248	2		T306	1
all_values[3]	auto[0]	auto[0]	auto[0]	90	1		T247	3		T248	3		T249	4
all_values[3]	auto[0]	auto[1]	auto[0]	85	1		T247	1		T248	3		T249	2
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T247	2		T306	1		T307	2
all_values[3]	auto[1]	auto[1]	auto[1]	44	1		T247	1		T248	1		T249	1
all_values[4]	auto[0]	auto[0]	auto[0]	69	1		T249	6		T305	1		T306	3
all_values[4]	auto[0]	auto[0]	auto[1]	19	1		T308	1		T309	2		T310	1
all_values[4]	auto[0]	auto[1]	auto[0]	59	1		T247	3		T248	4		T305	2
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T247	1		T248	1		T305	1
all_values[4]	auto[1]	auto[0]	auto[1]	50	1		T249	1		T305	2		T306	2
all_values[4]	auto[1]	auto[1]	auto[1]	58	1		T247	3		T248	2		T305	1
all_values[5]	auto[0]	auto[0]	auto[0]	65	1		T247	1		T248	3		T249	3
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T248	1		T249	1		T311	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1		T247	1		T248	2		T249	1
all_values[5]	auto[0]	auto[1]	auto[1]	31	1		T247	3		T307	1		T308	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T247	1		T249	2		T306	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T247	1		T248	1		T307	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal