Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.99 95.74 93.52 94.81 90.48 97.86 94.71 97.78


Total test records in report: 1088
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html

T833 /workspace/coverage/default/20.flash_ctrl_prog_reset.41058611 May 09 01:36:58 PM PDT 24 May 09 01:37:12 PM PDT 24 60370200 ps
T360 /workspace/coverage/default/18.flash_ctrl_disable.2753988133 May 09 01:37:00 PM PDT 24 May 09 01:37:24 PM PDT 24 73016500 ps
T834 /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1291704606 May 09 01:36:47 PM PDT 24 May 09 01:40:19 PM PDT 24 11935755400 ps
T835 /workspace/coverage/default/8.flash_ctrl_ro_derr.1184678355 May 09 01:35:26 PM PDT 24 May 09 01:37:30 PM PDT 24 680252100 ps
T26 /workspace/coverage/default/2.flash_ctrl_wr_intg.1184461690 May 09 01:34:23 PM PDT 24 May 09 01:34:38 PM PDT 24 45736700 ps
T836 /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3960667780 May 09 01:35:16 PM PDT 24 May 09 01:37:28 PM PDT 24 6503896200 ps
T837 /workspace/coverage/default/3.flash_ctrl_full_mem_access.3315479119 May 09 01:34:25 PM PDT 24 May 09 02:25:00 PM PDT 24 962050730100 ps
T838 /workspace/coverage/default/28.flash_ctrl_alert_test.2531638736 May 09 01:37:33 PM PDT 24 May 09 01:37:49 PM PDT 24 62128700 ps
T839 /workspace/coverage/default/32.flash_ctrl_connect.3103246020 May 09 01:37:43 PM PDT 24 May 09 01:38:00 PM PDT 24 13134800 ps
T840 /workspace/coverage/default/13.flash_ctrl_connect.1944835630 May 09 01:36:17 PM PDT 24 May 09 01:36:31 PM PDT 24 46094100 ps
T841 /workspace/coverage/default/6.flash_ctrl_intr_rd.1986013013 May 09 01:35:21 PM PDT 24 May 09 01:37:59 PM PDT 24 2034938600 ps
T842 /workspace/coverage/default/29.flash_ctrl_disable.1667682618 May 09 01:37:49 PM PDT 24 May 09 01:38:10 PM PDT 24 28651400 ps
T843 /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.1886753940 May 09 01:37:31 PM PDT 24 May 09 01:38:04 PM PDT 24 44174300 ps
T844 /workspace/coverage/default/19.flash_ctrl_re_evict.2354353918 May 09 01:37:13 PM PDT 24 May 09 01:37:50 PM PDT 24 133615000 ps
T845 /workspace/coverage/default/1.flash_ctrl_error_prog_win.3484587058 May 09 01:33:44 PM PDT 24 May 09 01:49:38 PM PDT 24 688498500 ps
T846 /workspace/coverage/default/23.flash_ctrl_alert_test.2113731020 May 09 01:37:30 PM PDT 24 May 09 01:37:45 PM PDT 24 125555300 ps
T847 /workspace/coverage/default/68.flash_ctrl_connect.1162702738 May 09 01:38:46 PM PDT 24 May 09 01:39:01 PM PDT 24 18552400 ps
T848 /workspace/coverage/default/6.flash_ctrl_error_prog_win.3152287340 May 09 01:35:05 PM PDT 24 May 09 01:49:34 PM PDT 24 1353228300 ps
T849 /workspace/coverage/default/4.flash_ctrl_intr_rd.4255345349 May 09 01:34:50 PM PDT 24 May 09 01:37:52 PM PDT 24 1836236100 ps
T850 /workspace/coverage/default/37.flash_ctrl_otp_reset.2489293584 May 09 01:38:25 PM PDT 24 May 09 01:40:37 PM PDT 24 76322300 ps
T851 /workspace/coverage/default/44.flash_ctrl_connect.3733604371 May 09 01:38:32 PM PDT 24 May 09 01:38:49 PM PDT 24 48087200 ps
T852 /workspace/coverage/default/1.flash_ctrl_re_evict.3968947485 May 09 01:34:00 PM PDT 24 May 09 01:34:37 PM PDT 24 94485400 ps
T853 /workspace/coverage/default/10.flash_ctrl_re_evict.4093352742 May 09 01:35:41 PM PDT 24 May 09 01:36:21 PM PDT 24 120020800 ps
T854 /workspace/coverage/default/31.flash_ctrl_connect.306454553 May 09 01:37:42 PM PDT 24 May 09 01:37:56 PM PDT 24 41302200 ps
T855 /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1969203301 May 09 01:37:21 PM PDT 24 May 09 01:41:14 PM PDT 24 35659838900 ps
T856 /workspace/coverage/default/47.flash_ctrl_alert_test.164989183 May 09 01:38:34 PM PDT 24 May 09 01:38:49 PM PDT 24 296911800 ps
T857 /workspace/coverage/default/3.flash_ctrl_smoke.889881200 May 09 01:34:24 PM PDT 24 May 09 01:36:27 PM PDT 24 63216800 ps
T858 /workspace/coverage/default/9.flash_ctrl_mp_regions.3192439842 May 09 01:35:28 PM PDT 24 May 09 01:49:43 PM PDT 24 17104881100 ps
T859 /workspace/coverage/default/13.flash_ctrl_mp_regions.1007788065 May 09 01:36:07 PM PDT 24 May 09 01:51:17 PM PDT 24 18049687600 ps
T860 /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.208633041 May 09 01:37:45 PM PDT 24 May 09 01:39:35 PM PDT 24 3505552500 ps
T861 /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.4168963311 May 09 01:34:36 PM PDT 24 May 09 01:34:51 PM PDT 24 42993100 ps
T862 /workspace/coverage/default/5.flash_ctrl_ro.2678763677 May 09 01:34:57 PM PDT 24 May 09 01:36:53 PM PDT 24 1670693300 ps
T863 /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.4092962316 May 09 01:33:50 PM PDT 24 May 09 01:34:13 PM PDT 24 19067000 ps
T864 /workspace/coverage/default/6.flash_ctrl_ro_derr.1468444977 May 09 01:35:05 PM PDT 24 May 09 01:37:17 PM PDT 24 3054597500 ps
T104 /workspace/coverage/default/9.flash_ctrl_fetch_code.4192275244 May 09 01:35:38 PM PDT 24 May 09 01:36:01 PM PDT 24 402280800 ps
T865 /workspace/coverage/default/75.flash_ctrl_connect.4120838118 May 09 01:38:59 PM PDT 24 May 09 01:39:17 PM PDT 24 15252400 ps
T866 /workspace/coverage/default/1.flash_ctrl_ro_serr.4056989936 May 09 01:33:54 PM PDT 24 May 09 01:36:01 PM PDT 24 993846100 ps
T867 /workspace/coverage/default/10.flash_ctrl_intr_rd.387348201 May 09 01:35:40 PM PDT 24 May 09 01:38:22 PM PDT 24 15018351900 ps
T868 /workspace/coverage/default/2.flash_ctrl_hw_rma.2782763535 May 09 01:34:17 PM PDT 24 May 09 02:09:59 PM PDT 24 334253787700 ps
T869 /workspace/coverage/default/35.flash_ctrl_alert_test.4193874833 May 09 01:38:00 PM PDT 24 May 09 01:38:14 PM PDT 24 60493500 ps
T870 /workspace/coverage/default/19.flash_ctrl_intr_rd.710311872 May 09 01:37:11 PM PDT 24 May 09 01:39:54 PM PDT 24 1410267600 ps
T871 /workspace/coverage/default/0.flash_ctrl_invalid_op.702786297 May 09 01:33:30 PM PDT 24 May 09 01:34:59 PM PDT 24 2033873300 ps
T313 /workspace/coverage/default/15.flash_ctrl_intr_rd.782263817 May 09 01:36:25 PM PDT 24 May 09 01:40:14 PM PDT 24 1323724200 ps
T872 /workspace/coverage/default/13.flash_ctrl_wo.4001896387 May 09 01:36:05 PM PDT 24 May 09 01:39:40 PM PDT 24 3035562200 ps
T296 /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.640203770 May 09 01:35:32 PM PDT 24 May 09 01:36:23 PM PDT 24 10034220300 ps
T328 /workspace/coverage/default/5.flash_ctrl_re_evict.3070442679 May 09 01:35:00 PM PDT 24 May 09 01:35:36 PM PDT 24 74746600 ps
T873 /workspace/coverage/default/12.flash_ctrl_rw.1473151551 May 09 01:36:02 PM PDT 24 May 09 01:45:58 PM PDT 24 17252638400 ps
T874 /workspace/coverage/default/18.flash_ctrl_smoke.2553511123 May 09 01:36:47 PM PDT 24 May 09 01:38:05 PM PDT 24 71108400 ps
T875 /workspace/coverage/default/36.flash_ctrl_connect.2617795043 May 09 01:38:09 PM PDT 24 May 09 01:38:26 PM PDT 24 37757800 ps
T876 /workspace/coverage/default/4.flash_ctrl_smoke.1570994169 May 09 01:34:36 PM PDT 24 May 09 01:36:40 PM PDT 24 38441500 ps
T193 /workspace/coverage/default/9.flash_ctrl_ro_serr.4287209609 May 09 01:35:37 PM PDT 24 May 09 01:38:02 PM PDT 24 1622049400 ps
T877 /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2795351343 May 09 01:34:48 PM PDT 24 May 09 01:39:00 PM PDT 24 141594739400 ps
T878 /workspace/coverage/default/3.flash_ctrl_ro_serr.1831960873 May 09 01:34:27 PM PDT 24 May 09 01:37:03 PM PDT 24 2209572000 ps
T879 /workspace/coverage/default/2.flash_ctrl_rand_ops.2216973816 May 09 01:34:03 PM PDT 24 May 09 01:50:11 PM PDT 24 851905500 ps
T880 /workspace/coverage/default/16.flash_ctrl_sec_info_access.4137929636 May 09 01:36:38 PM PDT 24 May 09 01:37:37 PM PDT 24 6209035600 ps
T881 /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.4280455609 May 09 01:34:36 PM PDT 24 May 09 01:34:50 PM PDT 24 20439800 ps
T353 /workspace/coverage/default/16.flash_ctrl_disable.1691549757 May 09 01:36:34 PM PDT 24 May 09 01:36:56 PM PDT 24 10436900 ps
T882 /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1798844397 May 09 01:37:11 PM PDT 24 May 09 01:40:36 PM PDT 24 8756112300 ps
T883 /workspace/coverage/default/18.flash_ctrl_connect.3568264482 May 09 01:37:05 PM PDT 24 May 09 01:37:21 PM PDT 24 104127600 ps
T884 /workspace/coverage/default/0.flash_ctrl_otp_reset.554168110 May 09 01:33:19 PM PDT 24 May 09 01:35:11 PM PDT 24 83189500 ps
T885 /workspace/coverage/default/3.flash_ctrl_error_prog_win.3283960759 May 09 01:34:27 PM PDT 24 May 09 01:48:34 PM PDT 24 9965464500 ps
T886 /workspace/coverage/default/26.flash_ctrl_disable.3193208702 May 09 01:37:30 PM PDT 24 May 09 01:37:52 PM PDT 24 32216600 ps
T887 /workspace/coverage/default/7.flash_ctrl_sec_info_access.434294534 May 09 01:35:26 PM PDT 24 May 09 01:36:33 PM PDT 24 1829144300 ps
T888 /workspace/coverage/default/11.flash_ctrl_phy_arb.3000144748 May 09 01:35:51 PM PDT 24 May 09 01:41:38 PM PDT 24 3374028200 ps
T889 /workspace/coverage/default/1.flash_ctrl_ro_derr.2097656280 May 09 01:33:50 PM PDT 24 May 09 01:35:53 PM PDT 24 3044221100 ps
T890 /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.275695365 May 09 01:37:23 PM PDT 24 May 09 01:41:09 PM PDT 24 18240668300 ps
T891 /workspace/coverage/default/5.flash_ctrl_connect.2919823628 May 09 01:35:19 PM PDT 24 May 09 01:35:33 PM PDT 24 45207700 ps
T892 /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.951184502 May 09 01:37:03 PM PDT 24 May 09 01:38:07 PM PDT 24 10057856200 ps
T893 /workspace/coverage/default/33.flash_ctrl_connect.4136558566 May 09 01:37:59 PM PDT 24 May 09 01:38:16 PM PDT 24 51888800 ps
T183 /workspace/coverage/default/2.flash_ctrl_mid_op_rst.345660592 May 09 01:34:13 PM PDT 24 May 09 01:35:25 PM PDT 24 957694600 ps
T894 /workspace/coverage/default/45.flash_ctrl_sec_info_access.185329202 May 09 01:38:30 PM PDT 24 May 09 01:39:37 PM PDT 24 1260600700 ps
T895 /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2871662606 May 09 01:33:30 PM PDT 24 May 09 02:15:05 PM PDT 24 250733869500 ps
T896 /workspace/coverage/default/6.flash_ctrl_sec_info_access.188066564 May 09 01:35:12 PM PDT 24 May 09 01:36:23 PM PDT 24 3049493200 ps
T897 /workspace/coverage/default/2.flash_ctrl_config_regwen.942947922 May 09 01:34:28 PM PDT 24 May 09 01:34:43 PM PDT 24 19736900 ps
T898 /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3979916838 May 09 01:33:38 PM PDT 24 May 09 01:35:50 PM PDT 24 9015510800 ps
T899 /workspace/coverage/default/6.flash_ctrl_invalid_op.4033003299 May 09 01:35:06 PM PDT 24 May 09 01:36:12 PM PDT 24 2179537300 ps
T900 /workspace/coverage/default/74.flash_ctrl_otp_reset.2347762808 May 09 01:38:57 PM PDT 24 May 09 01:41:09 PM PDT 24 171556300 ps
T901 /workspace/coverage/default/5.flash_ctrl_rand_ops.3978428358 May 09 01:35:00 PM PDT 24 May 09 01:37:30 PM PDT 24 68977700 ps
T902 /workspace/coverage/default/14.flash_ctrl_otp_reset.1893247771 May 09 01:36:12 PM PDT 24 May 09 01:38:22 PM PDT 24 38681800 ps
T903 /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1483775651 May 09 01:35:03 PM PDT 24 May 09 01:35:17 PM PDT 24 32718200 ps
T904 /workspace/coverage/default/21.flash_ctrl_sec_info_access.1404013130 May 09 01:37:24 PM PDT 24 May 09 01:38:23 PM PDT 24 2584599500 ps
T905 /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1078157918 May 09 01:35:31 PM PDT 24 May 09 01:35:45 PM PDT 24 15948600 ps
T906 /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1918997825 May 09 01:36:35 PM PDT 24 May 09 01:40:12 PM PDT 24 9281451300 ps
T907 /workspace/coverage/default/48.flash_ctrl_sec_info_access.379259771 May 09 01:38:43 PM PDT 24 May 09 01:39:55 PM PDT 24 2630866800 ps
T908 /workspace/coverage/default/12.flash_ctrl_re_evict.705556268 May 09 01:36:02 PM PDT 24 May 09 01:36:38 PM PDT 24 77237600 ps
T909 /workspace/coverage/default/24.flash_ctrl_alert_test.4153255073 May 09 01:37:22 PM PDT 24 May 09 01:37:37 PM PDT 24 84369500 ps
T910 /workspace/coverage/default/7.flash_ctrl_error_mp.3311413 May 09 01:35:15 PM PDT 24 May 09 02:12:43 PM PDT 24 5258395900 ps
T911 /workspace/coverage/default/0.flash_ctrl_config_regwen.2156830316 May 09 01:33:34 PM PDT 24 May 09 01:33:49 PM PDT 24 20631500 ps
T912 /workspace/coverage/default/4.flash_ctrl_stress_all.448858312 May 09 01:34:54 PM PDT 24 May 09 02:03:09 PM PDT 24 2072020400 ps
T913 /workspace/coverage/default/6.flash_ctrl_smoke.1697982700 May 09 01:35:19 PM PDT 24 May 09 01:36:59 PM PDT 24 112092500 ps
T184 /workspace/coverage/default/0.flash_ctrl_mid_op_rst.1101031700 May 09 01:33:27 PM PDT 24 May 09 01:34:43 PM PDT 24 3949688300 ps
T914 /workspace/coverage/default/5.flash_ctrl_sec_info_access.2143620148 May 09 01:34:59 PM PDT 24 May 09 01:35:57 PM PDT 24 391555500 ps
T915 /workspace/coverage/default/54.flash_ctrl_otp_reset.327657866 May 09 01:38:46 PM PDT 24 May 09 01:40:58 PM PDT 24 44788100 ps
T916 /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.491062475 May 09 01:36:35 PM PDT 24 May 09 01:36:49 PM PDT 24 48032200 ps
T917 /workspace/coverage/default/24.flash_ctrl_sec_info_access.2837766931 May 09 01:37:23 PM PDT 24 May 09 01:38:39 PM PDT 24 4247529700 ps
T918 /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1255025740 May 09 01:33:50 PM PDT 24 May 09 01:34:14 PM PDT 24 45805300 ps
T919 /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.726378268 May 09 01:33:49 PM PDT 24 May 09 01:37:30 PM PDT 24 8313887600 ps
T920 /workspace/coverage/default/6.flash_ctrl_rand_ops.3605042129 May 09 01:35:21 PM PDT 24 May 09 01:52:55 PM PDT 24 1067799700 ps
T921 /workspace/coverage/default/41.flash_ctrl_otp_reset.12873114 May 09 01:38:22 PM PDT 24 May 09 01:40:35 PM PDT 24 68270200 ps
T922 /workspace/coverage/default/1.flash_ctrl_phy_arb.1811539654 May 09 01:33:41 PM PDT 24 May 09 01:34:50 PM PDT 24 466446400 ps
T923 /workspace/coverage/default/55.flash_ctrl_connect.1635243793 May 09 01:38:44 PM PDT 24 May 09 01:38:59 PM PDT 24 46948900 ps
T924 /workspace/coverage/default/12.flash_ctrl_mp_regions.3923633724 May 09 01:36:16 PM PDT 24 May 09 01:43:39 PM PDT 24 5640913800 ps
T925 /workspace/coverage/default/4.flash_ctrl_sw_op.3281896747 May 09 01:34:38 PM PDT 24 May 09 01:35:03 PM PDT 24 88881400 ps
T926 /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1668315171 May 09 01:37:09 PM PDT 24 May 09 01:41:06 PM PDT 24 42649997100 ps
T927 /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2915729612 May 09 01:35:41 PM PDT 24 May 09 01:35:56 PM PDT 24 25394000 ps
T928 /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3329140629 May 09 01:37:00 PM PDT 24 May 09 01:37:14 PM PDT 24 15904000 ps
T929 /workspace/coverage/default/47.flash_ctrl_connect.1181042632 May 09 01:38:30 PM PDT 24 May 09 01:38:44 PM PDT 24 20516900 ps
T930 /workspace/coverage/default/3.flash_ctrl_otp_reset.3408232102 May 09 01:34:25 PM PDT 24 May 09 01:36:37 PM PDT 24 75539100 ps
T931 /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2780151458 May 09 01:35:40 PM PDT 24 May 09 01:40:26 PM PDT 24 85467980300 ps
T932 /workspace/coverage/default/2.flash_ctrl_error_prog_type.1693811011 May 09 01:34:16 PM PDT 24 May 09 02:21:44 PM PDT 24 921148800 ps
T933 /workspace/coverage/default/10.flash_ctrl_smoke.2349926162 May 09 01:35:51 PM PDT 24 May 09 01:37:55 PM PDT 24 27160700 ps
T934 /workspace/coverage/default/58.flash_ctrl_otp_reset.3201574074 May 09 01:38:50 PM PDT 24 May 09 01:41:01 PM PDT 24 71298600 ps
T935 /workspace/coverage/default/46.flash_ctrl_alert_test.2061239267 May 09 01:38:32 PM PDT 24 May 09 01:38:48 PM PDT 24 84834000 ps
T936 /workspace/coverage/default/3.flash_ctrl_ro_derr.2134436303 May 09 01:34:35 PM PDT 24 May 09 01:36:58 PM PDT 24 2808370500 ps
T937 /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1875383601 May 09 01:35:38 PM PDT 24 May 09 01:39:35 PM PDT 24 37009942600 ps
T938 /workspace/coverage/default/0.flash_ctrl_error_mp.1944860339 May 09 01:33:31 PM PDT 24 May 09 02:08:32 PM PDT 24 1773182600 ps
T939 /workspace/coverage/default/53.flash_ctrl_connect.1227346265 May 09 01:38:43 PM PDT 24 May 09 01:38:59 PM PDT 24 60992000 ps
T940 /workspace/coverage/default/28.flash_ctrl_prog_reset.2418040484 May 09 01:37:44 PM PDT 24 May 09 01:37:59 PM PDT 24 64049500 ps
T941 /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.847146353 May 09 01:35:51 PM PDT 24 May 09 01:36:51 PM PDT 24 10037341700 ps
T942 /workspace/coverage/default/10.flash_ctrl_connect.4112752329 May 09 01:35:41 PM PDT 24 May 09 01:35:55 PM PDT 24 47804800 ps
T223 /workspace/coverage/default/0.flash_ctrl_wr_intg.1303408172 May 09 01:33:40 PM PDT 24 May 09 01:33:56 PM PDT 24 405262700 ps
T943 /workspace/coverage/default/11.flash_ctrl_connect.2889981643 May 09 01:35:51 PM PDT 24 May 09 01:36:06 PM PDT 24 76834000 ps
T944 /workspace/coverage/default/31.flash_ctrl_otp_reset.2864921459 May 09 01:37:58 PM PDT 24 May 09 01:40:15 PM PDT 24 43178100 ps
T247 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2082663294 May 09 01:12:57 PM PDT 24 May 09 01:13:12 PM PDT 24 59373800 ps
T141 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1217111503 May 09 01:12:32 PM PDT 24 May 09 01:12:50 PM PDT 24 551843100 ps
T248 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3361807600 May 09 01:12:56 PM PDT 24 May 09 01:13:11 PM PDT 24 24984000 ps
T61 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4136715779 May 09 01:12:47 PM PDT 24 May 09 01:13:05 PM PDT 24 69067800 ps
T249 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1139690737 May 09 01:12:45 PM PDT 24 May 09 01:13:01 PM PDT 24 25557800 ps
T945 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3542533003 May 09 01:12:48 PM PDT 24 May 09 01:13:05 PM PDT 24 45338200 ps
T946 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2923384628 May 09 01:12:43 PM PDT 24 May 09 01:13:00 PM PDT 24 13244700 ps
T62 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.608287284 May 09 01:12:47 PM PDT 24 May 09 01:13:05 PM PDT 24 804710500 ps
T305 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.568745665 May 09 01:13:03 PM PDT 24 May 09 01:13:20 PM PDT 24 57285800 ps
T947 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1966300492 May 09 01:12:43 PM PDT 24 May 09 01:12:57 PM PDT 24 16441100 ps
T948 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2524964006 May 09 01:12:45 PM PDT 24 May 09 01:13:03 PM PDT 24 18174800 ps
T949 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.889208439 May 09 01:12:44 PM PDT 24 May 09 01:13:00 PM PDT 24 13814200 ps
T142 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2952414968 May 09 01:12:43 PM PDT 24 May 09 01:13:04 PM PDT 24 120963000 ps
T950 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.654435910 May 09 01:12:22 PM PDT 24 May 09 01:12:41 PM PDT 24 118352800 ps
T306 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3184571521 May 09 01:12:57 PM PDT 24 May 09 01:13:12 PM PDT 24 17464200 ps
T63 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.294001016 May 09 01:12:57 PM PDT 24 May 09 01:13:18 PM PDT 24 98428300 ps
T951 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.796827973 May 09 01:12:49 PM PDT 24 May 09 01:13:06 PM PDT 24 126227000 ps
T67 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4027528631 May 09 01:12:51 PM PDT 24 May 09 01:13:10 PM PDT 24 55869200 ps
T64 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.312232906 May 09 01:12:43 PM PDT 24 May 09 01:20:23 PM PDT 24 360976000 ps
T238 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3286903295 May 09 01:12:45 PM PDT 24 May 09 01:13:05 PM PDT 24 991932900 ps
T307 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1767379367 May 09 01:12:56 PM PDT 24 May 09 01:13:11 PM PDT 24 57270400 ps
T219 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2578732513 May 09 01:12:22 PM PDT 24 May 09 01:13:12 PM PDT 24 200688000 ps
T952 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3313935926 May 09 01:12:21 PM PDT 24 May 09 01:12:36 PM PDT 24 16190800 ps
T65 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.442718066 May 09 01:12:45 PM PDT 24 May 09 01:13:06 PM PDT 24 142458900 ps
T308 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.337064366 May 09 01:12:56 PM PDT 24 May 09 01:13:11 PM PDT 24 35608400 ps
T264 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1827007754 May 09 01:12:25 PM PDT 24 May 09 01:13:42 PM PDT 24 2200605400 ps
T953 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.276749933 May 09 01:12:58 PM PDT 24 May 09 01:13:14 PM PDT 24 18012100 ps
T226 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.349408102 May 09 01:12:32 PM PDT 24 May 09 01:12:53 PM PDT 24 186202300 ps
T311 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3584430263 May 09 01:12:56 PM PDT 24 May 09 01:13:11 PM PDT 24 18039500 ps
T239 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2174110314 May 09 01:12:34 PM PDT 24 May 09 01:12:56 PM PDT 24 539346200 ps
T66 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1622336612 May 09 01:12:51 PM PDT 24 May 09 01:28:11 PM PDT 24 1419524900 ps
T954 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1945851147 May 09 01:12:57 PM PDT 24 May 09 01:13:13 PM PDT 24 19616800 ps
T252 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.653970362 May 09 01:12:23 PM PDT 24 May 09 01:12:53 PM PDT 24 31760500 ps
T227 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2332264682 May 09 01:12:51 PM PDT 24 May 09 01:13:07 PM PDT 24 113196900 ps
T228 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.64036864 May 09 01:12:49 PM PDT 24 May 09 01:27:48 PM PDT 24 1674064800 ps
T240 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3925805386 May 09 01:12:33 PM PDT 24 May 09 01:12:52 PM PDT 24 65587500 ps
T309 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.213587749 May 09 01:12:59 PM PDT 24 May 09 01:13:16 PM PDT 24 15685000 ps
T259 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3223672024 May 09 01:12:33 PM PDT 24 May 09 01:20:31 PM PDT 24 1728087800 ps
T310 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1045287736 May 09 01:12:57 PM PDT 24 May 09 01:13:13 PM PDT 24 218965300 ps
T241 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.157418169 May 09 01:12:25 PM PDT 24 May 09 01:12:41 PM PDT 24 32256000 ps
T242 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.899636444 May 09 01:12:20 PM PDT 24 May 09 01:12:36 PM PDT 24 205724600 ps
T229 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3260036367 May 09 01:12:44 PM PDT 24 May 09 01:13:01 PM PDT 24 99635800 ps
T230 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3730408714 May 09 01:12:32 PM PDT 24 May 09 01:12:50 PM PDT 24 55308900 ps
T302 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4292959996 May 09 01:12:23 PM PDT 24 May 09 01:13:32 PM PDT 24 1609953800 ps
T231 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2216724000 May 09 01:12:43 PM PDT 24 May 09 01:25:21 PM PDT 24 1490616200 ps
T243 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3135514653 May 09 01:12:46 PM PDT 24 May 09 01:13:09 PM PDT 24 166405400 ps
T955 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1752257668 May 09 01:12:50 PM PDT 24 May 09 01:13:05 PM PDT 24 45655800 ps
T956 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.997877496 May 09 01:12:34 PM PDT 24 May 09 01:12:52 PM PDT 24 22985300 ps
T957 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3463730352 May 09 01:12:22 PM PDT 24 May 09 01:12:38 PM PDT 24 17616100 ps
T232 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3406377291 May 09 01:12:33 PM PDT 24 May 09 01:12:50 PM PDT 24 56347400 ps
T958 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3576078152 May 09 01:12:33 PM PDT 24 May 09 01:13:37 PM PDT 24 1271053300 ps
T959 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.303327971 May 09 01:12:32 PM PDT 24 May 09 01:12:50 PM PDT 24 181348700 ps
T960 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1269657574 May 09 01:13:04 PM PDT 24 May 09 01:13:20 PM PDT 24 176033600 ps
T961 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1053516374 May 09 01:12:45 PM PDT 24 May 09 01:13:03 PM PDT 24 43831700 ps
T261 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3915166050 May 09 01:12:23 PM PDT 24 May 09 01:27:27 PM PDT 24 681913500 ps
T962 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1425603278 May 09 01:12:48 PM PDT 24 May 09 01:13:06 PM PDT 24 12835200 ps
T963 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3813334138 May 09 01:12:43 PM PDT 24 May 09 01:13:00 PM PDT 24 182257000 ps
T283 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.657613525 May 09 01:12:45 PM PDT 24 May 09 01:13:07 PM PDT 24 388535200 ps
T964 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2808911529 May 09 01:12:31 PM PDT 24 May 09 01:12:47 PM PDT 24 16707400 ps
T965 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1937171809 May 09 01:13:02 PM PDT 24 May 09 01:13:18 PM PDT 24 27695400 ps
T966 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2118248101 May 09 01:13:05 PM PDT 24 May 09 01:13:23 PM PDT 24 29723600 ps
T967 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2491859643 May 09 01:12:36 PM PDT 24 May 09 01:13:13 PM PDT 24 229359700 ps
T244 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1211017284 May 09 01:12:50 PM PDT 24 May 09 01:13:08 PM PDT 24 36534500 ps
T968 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1526033208 May 09 01:12:44 PM PDT 24 May 09 01:13:00 PM PDT 24 54081300 ps
T969 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2976193359 May 09 01:12:59 PM PDT 24 May 09 01:13:15 PM PDT 24 16043600 ps
T970 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1106151493 May 09 01:12:31 PM PDT 24 May 09 01:12:48 PM PDT 24 59291300 ps
T233 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1194797141 May 09 01:12:31 PM PDT 24 May 09 01:12:46 PM PDT 24 17007600 ps
T971 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2359511172 May 09 01:12:21 PM PDT 24 May 09 01:12:36 PM PDT 24 83271100 ps
T972 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2340782118 May 09 01:12:45 PM PDT 24 May 09 01:13:01 PM PDT 24 64722500 ps
T282 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.568156906 May 09 01:12:20 PM PDT 24 May 09 01:27:36 PM PDT 24 731731600 ps
T262 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3799313255 May 09 01:12:48 PM PDT 24 May 09 01:25:46 PM PDT 24 8616319500 ps
T258 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.75800939 May 09 01:12:44 PM PDT 24 May 09 01:27:51 PM PDT 24 1905241300 ps
T973 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.725832856 May 09 01:12:26 PM PDT 24 May 09 01:13:48 PM PDT 24 4807082100 ps
T974 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2253576722 May 09 01:12:46 PM PDT 24 May 09 01:13:04 PM PDT 24 48893300 ps
T975 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3161590945 May 09 01:12:54 PM PDT 24 May 09 01:13:09 PM PDT 24 29771100 ps
T303 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4113442844 May 09 01:12:45 PM PDT 24 May 09 01:13:08 PM PDT 24 202121300 ps
T976 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3870834928 May 09 01:12:24 PM PDT 24 May 09 01:12:40 PM PDT 24 16423200 ps
T304 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.186593814 May 09 01:12:46 PM PDT 24 May 09 01:13:07 PM PDT 24 102421400 ps
T977 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2755601300 May 09 01:12:46 PM PDT 24 May 09 01:13:01 PM PDT 24 67110300 ps
T260 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3573812698 May 09 01:12:57 PM PDT 24 May 09 01:13:18 PM PDT 24 171347500 ps
T978 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3234591340 May 09 01:12:58 PM PDT 24 May 09 01:13:14 PM PDT 24 53793000 ps
T343 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3954003243 May 09 01:12:44 PM PDT 24 May 09 01:27:47 PM PDT 24 811433800 ps
T979 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1435046347 May 09 01:12:44 PM PDT 24 May 09 01:13:01 PM PDT 24 46895500 ps
T980 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2927527677 May 09 01:12:57 PM PDT 24 May 09 01:13:13 PM PDT 24 30508000 ps
T253 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2218925326 May 09 01:12:25 PM PDT 24 May 09 01:12:43 PM PDT 24 130267300 ps
T981 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2909476395 May 09 01:12:56 PM PDT 24 May 09 01:13:11 PM PDT 24 29388000 ps
T982 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2451044097 May 09 01:13:00 PM PDT 24 May 09 01:13:18 PM PDT 24 57401200 ps
T348 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2796838219 May 09 01:12:36 PM PDT 24 May 09 01:19:03 PM PDT 24 2406480700 ps
T983 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.275353426 May 09 01:12:48 PM PDT 24 May 09 01:13:11 PM PDT 24 212069200 ps
T254 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1494539816 May 09 01:12:25 PM PDT 24 May 09 01:12:45 PM PDT 24 38891900 ps
T984 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2214254449 May 09 01:12:34 PM PDT 24 May 09 01:12:49 PM PDT 24 15188900 ps
T985 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4166450043 May 09 01:12:45 PM PDT 24 May 09 01:13:03 PM PDT 24 24595700 ps
T986 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2861314262 May 09 01:12:33 PM PDT 24 May 09 01:12:48 PM PDT 24 57323200 ps
T987 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3082409971 May 09 01:12:48 PM PDT 24 May 09 01:13:03 PM PDT 24 29151600 ps
T988 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.382483365 May 09 01:12:36 PM PDT 24 May 09 01:12:54 PM PDT 24 25190700 ps
T989 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.450719478 May 09 01:12:44 PM PDT 24 May 09 01:13:00 PM PDT 24 14849500 ps
T990 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.523502255 May 09 01:12:50 PM PDT 24 May 09 01:13:11 PM PDT 24 803128400 ps
T991 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3889700465 May 09 01:12:35 PM PDT 24 May 09 01:13:12 PM PDT 24 319891900 ps
T992 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3391977280 May 09 01:12:33 PM PDT 24 May 09 01:12:51 PM PDT 24 34931500 ps
T993 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2569823852 May 09 01:12:33 PM PDT 24 May 09 01:12:52 PM PDT 24 148920900 ps
T994 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3752792694 May 09 01:12:22 PM PDT 24 May 09 01:12:41 PM PDT 24 24295900 ps
T995 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1573444533 May 09 01:12:34 PM PDT 24 May 09 01:13:23 PM PDT 24 196644800 ps
T245 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1494964976 May 09 01:12:43 PM PDT 24 May 09 01:13:05 PM PDT 24 244392500 ps
T996 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3306013399 May 09 01:12:23 PM PDT 24 May 09 01:12:43 PM PDT 24 139993200 ps
T997 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.857735939 May 09 01:12:44 PM PDT 24 May 09 01:13:02 PM PDT 24 134059900 ps
T998 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4020639272 May 09 01:12:34 PM PDT 24 May 09 01:13:31 PM PDT 24 1691038400 ps
T999 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.399864250 May 09 01:12:24 PM PDT 24 May 09 01:13:00 PM PDT 24 2157100700 ps
T1000 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.573490762 May 09 01:12:36 PM PDT 24 May 09 01:12:51 PM PDT 24 44606300 ps
T1001 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4133375552 May 09 01:12:25 PM PDT 24 May 09 01:12:42 PM PDT 24 12596600 ps
T1002 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.105839218 May 09 01:12:48 PM PDT 24 May 09 01:13:07 PM PDT 24 149338600 ps
T349 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3735220681 May 09 01:12:26 PM PDT 24 May 09 01:20:08 PM PDT 24 3371282100 ps
T1003 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1337501559 May 09 01:12:31 PM PDT 24 May 09 01:13:12 PM PDT 24 889448800 ps
T1004 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1479887450 May 09 01:12:49 PM PDT 24 May 09 01:13:07 PM PDT 24 51092200 ps
T1005 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.488289120 May 09 01:12:44 PM PDT 24 May 09 01:13:03 PM PDT 24 54762600 ps
T1006 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.621530843 May 09 01:12:44 PM PDT 24 May 09 01:13:22 PM PDT 24 201207000 ps
T1007 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1095400276 May 09 01:12:32 PM PDT 24 May 09 01:12:52 PM PDT 24 140809600 ps
T1008 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.4271223272 May 09 01:12:59 PM PDT 24 May 09 01:13:15 PM PDT 24 23372100 ps
T1009 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4106753626 May 09 01:12:33 PM PDT 24 May 09 01:13:15 PM PDT 24 339582100 ps
T246 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2134233441 May 09 01:12:24 PM PDT 24 May 09 01:12:46 PM PDT 24 120513200 ps
T234 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2259333196 May 09 01:12:22 PM PDT 24 May 09 01:12:39 PM PDT 24 59978700 ps
T255 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.453888741 May 09 01:12:22 PM PDT 24 May 09 01:12:45 PM PDT 24 145505200 ps
T1010 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2901437797 May 09 01:12:44 PM PDT 24 May 09 01:13:03 PM PDT 24 42081500 ps
T257 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.632909209 May 09 01:12:41 PM PDT 24 May 09 01:12:58 PM PDT 24 66442500 ps
T1011 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3177268524 May 09 01:12:50 PM PDT 24 May 09 01:13:07 PM PDT 24 16795100 ps
T1012 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.31318299 May 09 01:12:24 PM PDT 24 May 09 01:12:45 PM PDT 24 212020200 ps
T1013 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3670707583 May 09 01:12:49 PM PDT 24 May 09 01:13:04 PM PDT 24 24301600 ps
T1014 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1189361089 May 09 01:13:00 PM PDT 24 May 09 01:13:17 PM PDT 24 44137700 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%