GPIO Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.550s	178.493us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.550s	365.546us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.630s	34.055us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.700s	35.392us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.050s	257.529us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.840s	557.420us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.330s	100.716us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.700s	35.392us	20	20	100.00
		gpio_csr_aliasing	0.840s	557.420us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.270s	264.657us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.400s	114.987us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.120s	58.190us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.580s	114.357us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.330s	108.222us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.700s	95.593us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.590s	4.374ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.140s	490.338us	50	50	100.00
V2	full_random	gpio_full_random	1.050s	83.825us	50	50	100.00
V2	stress_all	gpio_stress_all	3.567m	16.993ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	35.168us	50	50	100.00
V2	intr_test	gpio_intr_test	0.730s	35.261us	25	50	50.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.880s	183.573us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.880s	183.573us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.700s	35.392us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	42.520us	20	20	100.00
		gpio_csr_aliasing	0.840s	557.420us	5	5	100.00
		gpio_csr_hw_reset	0.630s	34.055us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.700s	35.392us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	42.520us	20	20	100.00
		gpio_csr_aliasing	0.840s	557.420us	5	5	100.00
		gpio_csr_hw_reset	0.630s	34.055us	5	5	100.00
V2		TOTAL			615	640	96.09
V2S	tl_intg_err	gpio_tl_intg_err	1.580s	1.023ms	20	20	100.00
		gpio_sec_cm	0.970s	440.289us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.580s	1.023ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	43.967m	477.810ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			845	870	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 25 failures:

Test gpio_intr_test has 25 failures.

1.gpio_intr_test.3322959456
Line 217, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_test/latest/run.log

  UVM_ERROR @   4439730 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2426012654 [0x909a03ee]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   4439730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.gpio_intr_test.2460376491
Line 217, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_test/latest/run.log

  UVM_ERROR @   1518025 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3618080112 [0xd7a78570]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   1518025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.