GPIO Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.200s	82.173us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.050s	183.948us	50	50	100.00
		gpio_smoke_en_cdc_prim	2.150s	204.963us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.930s	305.298us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	1.000s	24.772us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.930s	48.051us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	5.200s	337.874us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.250s	117.288us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.350s	35.647us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.930s	48.051us	20	20	100.00
		gpio_csr_aliasing	1.250s	117.288us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.830s	501.965us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.960s	111.126us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.430s	153.390us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.150s	429.620us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.770s	283.884us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.110s	331.462us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	36.350s	777.861us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	8.420s	486.465us	50	50	100.00
V2	full_random	gpio_full_random	1.660s	1.270ms	50	50	100.00
V2	stress_all	gpio_stress_all	4.411m	76.487ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.880s	49.225us	50	50	100.00
V2	intr_test	gpio_intr_test	0.920s	30.540us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.920s	1.433ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.920s	1.433ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.930s	48.051us	20	20	100.00
		gpio_same_csr_outstanding	1.250s	125.699us	20	20	100.00
		gpio_csr_aliasing	1.250s	117.288us	5	5	100.00
		gpio_csr_hw_reset	1.000s	24.772us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.930s	48.051us	20	20	100.00
		gpio_same_csr_outstanding	1.250s	125.699us	20	20	100.00
		gpio_csr_aliasing	1.250s	117.288us	5	5	100.00
		gpio_csr_hw_reset	1.000s	24.772us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	2.180s	140.915us	20	20	100.00
		gpio_sec_cm	1.000s	80.242us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	2.180s	140.915us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.619m	410.867ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
  • Test gpio_stress_all_with_rand_reset has 31 failures.

    • 0.gpio_stress_all_with_rand_reset.96088766477286537293383162061851366361571717102131733366152699522188041069134
      Line 2777, in log /workspaces/repo/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21052582070 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21052582070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.103324977108667040369873386740772664149650994634311521224802759772893556641916
      Line 2925, in log /workspaces/repo/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9453972738 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9453972738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

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