GPIO Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.060s	77.529us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.170s	130.786us	50	50	100.00
		gpio_smoke_en_cdc_prim	2.350s	375.048us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	2.500s	95.106us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.980s	44.579us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.960s	15.604us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	4.190s	330.193us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.390s	38.448us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.880s	29.316us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.960s	15.604us	20	20	100.00
		gpio_csr_aliasing	1.390s	38.448us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	2.050s	286.779us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	2.120s	134.398us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.430s	164.884us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.210s	338.456us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.840s	176.280us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.330s	96.784us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	39.430s	725.018us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	8.900s	465.456us	50	50	100.00
V2	full_random	gpio_full_random	1.600s	128.208us	50	50	100.00
V2	stress_all	gpio_stress_all	3.833m	7.836ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.910s	15.686us	50	50	100.00
V2	intr_test	gpio_intr_test	0.950s	15.216us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.820s	184.754us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.820s	184.754us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.960s	15.604us	20	20	100.00
		gpio_same_csr_outstanding	1.200s	126.935us	20	20	100.00
		gpio_csr_aliasing	1.390s	38.448us	5	5	100.00
		gpio_csr_hw_reset	0.980s	44.579us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.960s	15.604us	20	20	100.00
		gpio_same_csr_outstanding	1.200s	126.935us	20	20	100.00
		gpio_csr_aliasing	1.390s	38.448us	5	5	100.00
		gpio_csr_hw_reset	0.980s	44.579us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	2.230s	198.851us	20	20	100.00
		gpio_sec_cm	1.090s	158.780us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	2.230s	198.851us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	4.700m	31.979ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.04	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
  • Test gpio_stress_all_with_rand_reset has 31 failures.

    • 0.gpio_stress_all_with_rand_reset.22219046271076822760384380883175989722070607461257459525760914182904219575228
      Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 406247055 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10013 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 406247055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.109554529840386321604158824568549724392195854314605415380906328820136833752146
      Line 356, in log /workspaces/repo/scratch/os_regression_2024_10_14/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5648130015 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5648130015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

Past Results

• Latest
• lint
• 2024.10.13_03.37.48
• 2024.10.10_10.14.00
• 2024.10.04_00.40.53
• 2024.09.25_10.59.53
• 2024.09.19_09.03.41
• 2024.09.12_10.15.19