GPIO Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.530s	140.801us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.500s	365.850us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.520s	132.999us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.540s	200.546us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	21.252us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.690s	42.433us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.590s	2.489ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	144.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.650s	132.995us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.690s	42.433us	20	20	100.00
		gpio_csr_aliasing	0.890s	144.477us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	286.899us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.320s	293.571us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	56.018us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.470s	106.119us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.790s	468.310us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.550s	319.492us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.200s	874.592us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.740s	1.174ms	50	50	100.00
V2	full_random	gpio_full_random	1.120s	76.668us	50	50	100.00
V2	stress_all	gpio_stress_all	3.574m	7.761ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	119.683us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	105.524us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.290s	823.086us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.290s	823.086us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.690s	42.433us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	136.707us	20	20	100.00
		gpio_csr_aliasing	0.890s	144.477us	5	5	100.00
		gpio_csr_hw_reset	0.690s	21.252us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.690s	42.433us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	136.707us	20	20	100.00
		gpio_csr_aliasing	0.890s	144.477us	5	5	100.00
		gpio_csr_hw_reset	0.690s	21.252us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.400s	122.481us	20	20	100.00
		gpio_sec_cm	1.000s	80.651us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.400s	122.481us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	56.747m	304.428ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			937	970	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test gpio_stress_all_with_rand_reset has 33 failures.
  - 1.gpio_stress_all_with_rand_reset.50027934661435953208889090196261616720925011774691512962089627705966115493324
    Line 420, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 312382088 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 312382088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.51377283229460992740299414547640775514543363557365290318817922012013571068463
    Line 5096, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24345574832 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24345574832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.

GPIO Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `41bc3e0c7f`