Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7174790	1			T1	10		T2	28		T3	1
all_pins[1]	7174790	1			T1	10		T2	28		T3	1
all_pins[2]	7174790	1			T1	10		T2	28		T3	1
all_pins[3]	7174790	1			T1	10		T2	28		T3	1
all_pins[4]	7174790	1			T1	10		T2	28		T3	1
all_pins[5]	7174790	1			T1	10		T2	28		T3	1
all_pins[6]	7174790	1			T1	10		T2	28		T3	1
all_pins[7]	7174790	1			T1	10		T2	28		T3	1
all_pins[8]	7174790	1			T1	10		T2	28		T3	1
all_pins[9]	7174790	1			T1	10		T2	28		T3	1
all_pins[10]	7174790	1			T1	10		T2	28		T3	1
all_pins[11]	7174790	1			T1	10		T2	28		T3	1
all_pins[12]	7174790	1			T1	10		T2	28		T3	1
all_pins[13]	7174790	1			T1	10		T2	28		T3	1
all_pins[14]	7174790	1			T1	10		T2	28		T3	1
all_pins[15]	7174790	1			T1	10		T2	28		T3	1
all_pins[16]	7174790	1			T1	10		T2	28		T3	1
all_pins[17]	7174790	1			T1	10		T2	28		T3	1
all_pins[18]	7174790	1			T1	10		T2	28		T3	1
all_pins[19]	7174790	1			T1	10		T2	28		T3	1
all_pins[20]	7174790	1			T1	10		T2	28		T3	1
all_pins[21]	7174790	1			T1	10		T2	28		T3	1
all_pins[22]	7174790	1			T1	10		T2	28		T3	1
all_pins[23]	7174790	1			T1	10		T2	28		T3	1
all_pins[24]	7174790	1			T1	10		T2	28		T3	1
all_pins[25]	7174790	1			T1	10		T2	28		T3	1
all_pins[26]	7174790	1			T1	10		T2	28		T3	1
all_pins[27]	7174790	1			T1	10		T2	28		T3	1
all_pins[28]	7174790	1			T1	10		T2	28		T3	1
all_pins[29]	7174790	1			T1	10		T2	28		T3	1
all_pins[30]	7174790	1			T1	10		T2	28		T3	1
all_pins[31]	7174790	1			T1	10		T2	28		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	141870230	1			T1	211		T2	677		T3	32
values[0x1]	87723050	1			T1	109		T2	219		T7	83
transitions[0x0=>0x1]	52504625	1			T1	64		T2	168		T7	52
transitions[0x1=>0x0]	52504555	1			T1	64		T2	168		T7	52

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4394140	1			T1	1		T2	15		T3	1
all_pins[0]	values[0x1]	2780650	1			T1	9		T2	13		T8	13
all_pins[0]	transitions[0x0=>0x1]	1694985	1			T1	2		T2	7		T8	7
all_pins[0]	transitions[0x1=>0x0]	1674525	1			T2	5		T8	5		T10	2
all_pins[1]	values[0x0]	4404590	1			T1	3		T2	18		T3	1
all_pins[1]	values[0x1]	2770200	1			T1	7		T2	10		T7	4
all_pins[1]	transitions[0x0=>0x1]	1624690	1			T2	7		T7	4		T8	7
all_pins[1]	transitions[0x1=>0x0]	1635140	1			T1	2		T2	10		T8	10
all_pins[2]	values[0x0]	4434770	1			T1	8		T2	16		T3	1
all_pins[2]	values[0x1]	2740020	1			T1	2		T2	12		T7	2
all_pins[2]	transitions[0x0=>0x1]	1656440	1			T1	2		T2	9		T7	2
all_pins[2]	transitions[0x1=>0x0]	1686620	1			T1	7		T2	7		T7	4
all_pins[3]	values[0x0]	4488085	1			T1	8		T2	24		T3	1
all_pins[3]	values[0x1]	2686705	1			T1	2		T2	4		T7	2
all_pins[3]	transitions[0x0=>0x1]	1613380	1			T2	1		T8	1		T4	6
all_pins[3]	transitions[0x1=>0x0]	1666695	1			T2	9		T8	9		T10	3
all_pins[4]	values[0x0]	4448760	1			T1	4		T2	23		T3	1
all_pins[4]	values[0x1]	2726030	1			T1	6		T2	5		T7	5
all_pins[4]	transitions[0x0=>0x1]	1665260	1			T1	4		T2	4		T7	5
all_pins[4]	transitions[0x1=>0x0]	1625935	1			T2	3		T7	2		T8	3
all_pins[5]	values[0x0]	4417315	1			T1	8		T2	21		T3	1
all_pins[5]	values[0x1]	2757475	1			T1	2		T2	7		T7	6
all_pins[5]	transitions[0x0=>0x1]	1668620	1			T2	6		T7	2		T8	6
all_pins[5]	transitions[0x1=>0x0]	1637175	1			T1	4		T2	4		T7	1
all_pins[6]	values[0x0]	4512970	1			T1	9		T2	25		T3	1
all_pins[6]	values[0x1]	2661820	1			T1	1		T2	3		T8	3
all_pins[6]	transitions[0x0=>0x1]	1588500	1			T1	1		T2	2		T8	2
all_pins[6]	transitions[0x1=>0x0]	1684155	1			T1	2		T2	6		T7	6
all_pins[7]	values[0x0]	4433985	1			T1	10		T2	26		T3	1
all_pins[7]	values[0x1]	2740805	1			T2	2		T7	3		T8	2
all_pins[7]	transitions[0x0=>0x1]	1651475	1			T2	2		T7	3		T8	2
all_pins[7]	transitions[0x1=>0x0]	1572490	1			T1	1		T2	3		T8	3
all_pins[8]	values[0x0]	4417830	1			T1	1		T2	23		T3	1
all_pins[8]	values[0x1]	2756960	1			T1	9		T2	5		T8	5
all_pins[8]	transitions[0x0=>0x1]	1665900	1			T1	9		T2	5		T8	5
all_pins[8]	transitions[0x1=>0x0]	1649745	1			T2	2		T7	3		T8	2
all_pins[9]	values[0x0]	4408445	1			T1	6		T2	26		T3	1
all_pins[9]	values[0x1]	2766345	1			T1	4		T2	2		T7	1
all_pins[9]	transitions[0x0=>0x1]	1647115	1			T2	1		T7	1		T8	1
all_pins[9]	transitions[0x1=>0x0]	1637730	1			T1	5		T2	4		T8	4
all_pins[10]	values[0x0]	4433415	1			T1	10		T2	23		T3	1
all_pins[10]	values[0x1]	2741375	1			T2	5		T7	5		T8	5
all_pins[10]	transitions[0x0=>0x1]	1633390	1			T2	5		T7	4		T8	5
all_pins[10]	transitions[0x1=>0x0]	1658360	1			T1	4		T2	2		T8	2
all_pins[11]	values[0x0]	4384840	1			T1	3		T2	13		T3	1
all_pins[11]	values[0x1]	2789950	1			T1	7		T2	15		T7	6
all_pins[11]	transitions[0x0=>0x1]	1635050	1			T1	7		T2	13		T7	2
all_pins[11]	transitions[0x1=>0x0]	1586475	1			T2	3		T7	1		T8	3
all_pins[12]	values[0x0]	4411365	1			T1	4		T2	23		T3	1
all_pins[12]	values[0x1]	2763425	1			T1	6		T2	5		T7	3
all_pins[12]	transitions[0x0=>0x1]	1642220	1			T1	2		T2	2		T8	2
all_pins[12]	transitions[0x1=>0x0]	1668745	1			T1	3		T2	12		T7	3
all_pins[13]	values[0x0]	4383495	1			T1	4		T2	21		T3	1
all_pins[13]	values[0x1]	2791295	1			T1	6		T2	7		T7	3
all_pins[13]	transitions[0x0=>0x1]	1644915	1			T2	5		T7	1		T8	5
all_pins[13]	transitions[0x1=>0x0]	1617045	1			T2	3		T7	1		T8	3
all_pins[14]	values[0x0]	4466565	1			T1	10		T2	22		T3	1
all_pins[14]	values[0x1]	2708225	1			T2	6		T7	4		T8	6
all_pins[14]	transitions[0x0=>0x1]	1600110	1			T2	6		T7	3		T8	6
all_pins[14]	transitions[0x1=>0x0]	1683180	1			T1	6		T2	7		T7	2
all_pins[15]	values[0x0]	4419485	1			T1	10		T2	23		T3	1
all_pins[15]	values[0x1]	2755305	1			T2	5		T8	5		T10	2
all_pins[15]	transitions[0x0=>0x1]	1678580	1			T2	2		T8	2		T10	2
all_pins[15]	transitions[0x1=>0x0]	1631500	1			T2	3		T7	4		T8	3
all_pins[16]	values[0x0]	4436005	1			T1	6		T2	25		T3	1
all_pins[16]	values[0x1]	2738785	1			T1	4		T2	3		T7	2
all_pins[16]	transitions[0x0=>0x1]	1635415	1			T1	4		T2	3		T7	2
all_pins[16]	transitions[0x1=>0x0]	1651935	1			T2	5		T8	5		T4	17
all_pins[17]	values[0x0]	4409620	1			T1	10		T2	23		T3	1
all_pins[17]	values[0x1]	2765170	1			T2	5		T7	1		T8	5
all_pins[17]	transitions[0x0=>0x1]	1676815	1			T2	4		T8	4		T4	7
all_pins[17]	transitions[0x1=>0x0]	1650430	1			T1	4		T2	2		T7	1
all_pins[18]	values[0x0]	4466650	1			T1	10		T2	20		T3	1
all_pins[18]	values[0x1]	2708140	1			T2	8		T8	8		T4	11
all_pins[18]	transitions[0x0=>0x1]	1585300	1			T2	8		T8	8		T4	11
all_pins[18]	transitions[0x1=>0x0]	1642330	1			T2	5		T7	1		T8	5
all_pins[19]	values[0x0]	4444185	1			T1	2		T2	16		T3	1
all_pins[19]	values[0x1]	2730605	1			T1	8		T2	12		T7	5
all_pins[19]	transitions[0x0=>0x1]	1620785	1			T1	8		T2	12		T7	5
all_pins[19]	transitions[0x1=>0x0]	1598320	1			T2	8		T8	8		T4	9
all_pins[20]	values[0x0]	4402490	1			T1	7		T2	23		T3	1
all_pins[20]	values[0x1]	2772300	1			T1	3		T2	5		T7	5
all_pins[20]	transitions[0x0=>0x1]	1683795	1			T2	2		T8	2		T4	9
all_pins[20]	transitions[0x1=>0x0]	1642100	1			T1	5		T2	9		T8	9
all_pins[21]	values[0x0]	4483755	1			T1	10		T2	20		T3	1
all_pins[21]	values[0x1]	2691035	1			T2	8		T7	6		T8	8
all_pins[21]	transitions[0x0=>0x1]	1590880	1			T2	5		T7	2		T8	5
all_pins[21]	transitions[0x1=>0x0]	1672145	1			T1	3		T2	2		T7	1
all_pins[22]	values[0x0]	4371005	1			T1	3		T2	26		T3	1
all_pins[22]	values[0x1]	2803785	1			T1	7		T2	2		T7	3
all_pins[22]	transitions[0x0=>0x1]	1708605	1			T1	7		T2	2		T7	1
all_pins[22]	transitions[0x1=>0x0]	1595855	1			T2	8		T7	4		T8	8
all_pins[23]	values[0x0]	4466630	1			T1	7		T2	18		T3	1
all_pins[23]	values[0x1]	2708160	1			T1	3		T2	10		T8	10
all_pins[23]	transitions[0x0=>0x1]	1586050	1			T2	9		T8	9		T10	2
all_pins[23]	transitions[0x1=>0x0]	1681675	1			T1	4		T2	1		T7	3
all_pins[24]	values[0x0]	4470785	1			T1	9		T2	24		T3	1
all_pins[24]	values[0x1]	2704005	1			T1	1		T2	4		T7	3
all_pins[24]	transitions[0x0=>0x1]	1625765	1			T7	3		T9	3		T10	1
all_pins[24]	transitions[0x1=>0x0]	1629920	1			T1	2		T2	6		T8	6
all_pins[25]	values[0x0]	4395720	1			T1	7		T2	17		T3	1
all_pins[25]	values[0x1]	2779070	1			T1	3		T2	11		T8	11
all_pins[25]	transitions[0x0=>0x1]	1687010	1			T1	3		T2	10		T8	10
all_pins[25]	transitions[0x1=>0x0]	1611945	1			T1	1		T2	3		T7	3
all_pins[26]	values[0x0]	4434025	1			T1	8		T2	27		T3	1
all_pins[26]	values[0x1]	2740765	1			T1	2		T2	1		T7	3
all_pins[26]	transitions[0x0=>0x1]	1621565	1			T1	2		T2	1		T7	3
all_pins[26]	transitions[0x1=>0x0]	1659870	1			T1	3		T2	11		T8	11
all_pins[27]	values[0x0]	4395065	1			T1	4		T2	22		T3	1
all_pins[27]	values[0x1]	2779725	1			T1	6		T2	6		T7	1
all_pins[27]	transitions[0x0=>0x1]	1640560	1			T1	4		T2	6		T8	6
all_pins[27]	transitions[0x1=>0x0]	1601600	1			T2	1		T7	2		T8	1
all_pins[28]	values[0x0]	4470105	1			T1	8		T2	18		T3	1
all_pins[28]	values[0x1]	2704685	1			T1	2		T2	10		T7	5
all_pins[28]	transitions[0x0=>0x1]	1617990	1			T2	8		T7	4		T8	8
all_pins[28]	transitions[0x1=>0x0]	1693030	1			T1	4		T2	4		T8	4
all_pins[29]	values[0x0]	4488590	1			T1	10		T2	11		T3	1
all_pins[29]	values[0x1]	2686200	1			T2	17		T8	17		T10	4
all_pins[29]	transitions[0x0=>0x1]	1616120	1			T2	10		T8	10		T10	2
all_pins[29]	transitions[0x1=>0x0]	1634605	1			T1	2		T2	3		T7	5
all_pins[30]	values[0x0]	4461015	1			T1	8		T2	28		T3	1
all_pins[30]	values[0x1]	2713775	1			T1	2		T7	5		T9	5
all_pins[30]	transitions[0x0=>0x1]	1656700	1			T1	2		T7	5		T9	5
all_pins[30]	transitions[0x1=>0x0]	1629125	1			T2	17		T8	17		T10	4
all_pins[31]	values[0x0]	4414530	1			T1	3		T2	17		T3	1
all_pins[31]	values[0x1]	2760260	1			T1	7		T2	11		T8	11
all_pins[31]	transitions[0x0=>0x1]	1640640	1			T1	7		T2	11		T8	11
all_pins[31]	transitions[0x1=>0x0]	1594155	1			T1	2		T7	5		T9	5