Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	99.04	97.42	97.88		98.78	95.79

Total modules in report: 25

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gpio_csr_assert_fpv	0.00						0.00
prim_secded_inv_64_57_dec	90.52			90.52
tlul_rsp_intg_gen	91.67	83.33					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
prim_subreg_arb	94.44	83.33	100.00			100.00
prim_subreg_arb	100.00					100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 )	50.00	50.00
prim_subreg_arb ( parameter DW=32,SwAccess=3,Mubi=0 )	100.00	100.00	100.00
tlul_assert	94.54	100.00				85.71	97.90
tlul_adapter_reg	98.37	100.00	93.48			100.00	100.00
gpio_reg_top	99.39	100.00	97.56			100.00	100.00
prim_filter_ctr	100.00	100.00	100.00			100.00
gpio	100.00	100.00	100.00	100.00		100.00	100.00
tlul_data_integ_dec	100.00	100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
prim_alert_sender	100.00			100.00
prim_onehot_check	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
prim_intr_hw	100.00	100.00				100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
tb