Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	26109015	1			T1	6		T2	30		T3	1
all_values[1]	26109015	1			T1	6		T2	30		T3	1
all_values[2]	26109015	1			T1	6		T2	30		T3	1
all_values[3]	26109015	1			T1	6		T2	30		T3	1
all_values[4]	26109015	1			T1	6		T2	30		T3	1
all_values[5]	26109015	1			T1	6		T2	30		T3	1
all_values[6]	26109015	1			T1	6		T2	30		T3	1
all_values[7]	26109015	1			T1	6		T2	30		T3	1
all_values[8]	26109015	1			T1	6		T2	30		T3	1
all_values[9]	26109015	1			T1	6		T2	30		T3	1
all_values[10]	26109015	1			T1	6		T2	30		T3	1
all_values[11]	26109015	1			T1	6		T2	30		T3	1
all_values[12]	26109015	1			T1	6		T2	30		T3	1
all_values[13]	26109015	1			T1	6		T2	30		T3	1
all_values[14]	26109015	1			T1	6		T2	30		T3	1
all_values[15]	26109015	1			T1	6		T2	30		T3	1
all_values[16]	26109015	1			T1	6		T2	30		T3	1
all_values[17]	26109015	1			T1	6		T2	30		T3	1
all_values[18]	26109015	1			T1	6		T2	30		T3	1
all_values[19]	26109015	1			T1	6		T2	30		T3	1
all_values[20]	26109015	1			T1	6		T2	30		T3	1
all_values[21]	26109015	1			T1	6		T2	30		T3	1
all_values[22]	26109015	1			T1	6		T2	30		T3	1
all_values[23]	26109015	1			T1	6		T2	30		T3	1
all_values[24]	26109015	1			T1	6		T2	30		T3	1
all_values[25]	26109015	1			T1	6		T2	30		T3	1
all_values[26]	26109015	1			T1	6		T2	30		T3	1
all_values[27]	26109015	1			T1	6		T2	30		T3	1
all_values[28]	26109015	1			T1	6		T2	30		T3	1
all_values[29]	26109015	1			T1	6		T2	30		T3	1
all_values[30]	26109015	1			T1	6		T2	30		T3	1
all_values[31]	26109015	1			T1	6		T2	30		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

469578270

1

T1

99

T2

482

T3

32

auto[1]

365910210

1

T1

93

T2

478

T7

86

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164147170

1

T1

82

T2

553

T3

32

auto[1]

671341310

1

T1

110

T2

407

T7

118

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

827614580

1

T1

192

T2

827

T3

32

auto[1]

7873900

1

T2

133

T8

133

T12

133

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	4121360	1			T1	1		T2	5		T3	1
all_values[0]	auto[0]	auto[0]	auto[1]	10622800	1			T2	6		T8	6		T4	7
all_values[0]	auto[0]	auto[1]	auto[0]	969325	1			T2	2		T7	1		T8	2
all_values[0]	auto[0]	auto[1]	auto[1]	10151880	1			T1	5		T2	11		T8	11
all_values[0]	auto[1]	auto[0]	auto[1]	119650	1			T2	3		T8	3		T12	3
all_values[0]	auto[1]	auto[1]	auto[1]	124000	1			T2	3		T8	3		T12	3
all_values[1]	auto[0]	auto[0]	auto[0]	4040900	1			T1	1		T2	5		T3	1
all_values[1]	auto[0]	auto[0]	auto[1]	10399075	1			T1	1		T2	4		T7	1
all_values[1]	auto[0]	auto[1]	auto[0]	992180	1			T2	8		T8	8		T4	4
all_values[1]	auto[0]	auto[1]	auto[1]	10428510	1			T1	4		T2	9		T7	4
all_values[1]	auto[1]	auto[0]	auto[1]	121050	1			T2	2		T8	2		T12	2
all_values[1]	auto[1]	auto[1]	auto[1]	127300	1			T2	2		T8	2		T12	2
all_values[2]	auto[0]	auto[0]	auto[0]	4162650	1			T1	3		T2	11		T3	1
all_values[2]	auto[0]	auto[0]	auto[1]	10696670	1			T1	2		T2	1		T7	4
all_values[2]	auto[0]	auto[1]	auto[0]	937310	1			T2	5		T8	5		T4	7
all_values[2]	auto[0]	auto[1]	auto[1]	10069085	1			T1	1		T2	10		T7	1
all_values[2]	auto[1]	auto[0]	auto[1]	125100	1			T2	1		T8	1		T12	1
all_values[2]	auto[1]	auto[1]	auto[1]	118200	1			T2	2		T8	2		T12	2
all_values[3]	auto[0]	auto[0]	auto[0]	4134135	1			T1	4		T2	13		T3	1
all_values[3]	auto[0]	auto[0]	auto[1]	10528295	1			T1	1		T2	2		T7	1
all_values[3]	auto[0]	auto[1]	auto[0]	896010	1			T2	11		T8	11		T10	1
all_values[3]	auto[0]	auto[1]	auto[1]	10306175	1			T1	1		T2	2		T7	1
all_values[3]	auto[1]	auto[0]	auto[1]	128750	1			T80	48		T57	8		T58	8
all_values[3]	auto[1]	auto[1]	auto[1]	115650	1			T2	2		T8	2		T12	2
all_values[4]	auto[0]	auto[0]	auto[0]	4123660	1			T1	1		T2	11		T3	1
all_values[4]	auto[0]	auto[0]	auto[1]	10752075	1			T1	1		T2	5		T7	1
all_values[4]	auto[0]	auto[1]	auto[0]	1007730	1			T2	8		T7	2		T8	8
all_values[4]	auto[0]	auto[1]	auto[1]	9978050	1			T1	4		T2	2		T7	2
all_values[4]	auto[1]	auto[0]	auto[1]	123900	1			T2	1		T8	1		T12	1
all_values[4]	auto[1]	auto[1]	auto[1]	123600	1			T2	3		T8	3		T12	3
all_values[5]	auto[0]	auto[0]	auto[0]	4099030	1			T1	4		T2	12		T3	1
all_values[5]	auto[0]	auto[0]	auto[1]	10435355	1			T1	1		T2	2		T7	1
all_values[5]	auto[0]	auto[1]	auto[0]	1074920	1			T2	5		T8	5		T10	2
all_values[5]	auto[0]	auto[1]	auto[1]	10251910	1			T1	1		T2	6		T7	4
all_values[5]	auto[1]	auto[0]	auto[1]	122250	1			T2	4		T8	4		T12	4
all_values[5]	auto[1]	auto[1]	auto[1]	125550	1			T2	1		T8	1		T12	1
all_values[6]	auto[0]	auto[0]	auto[0]	4103730	1			T1	1		T2	11		T3	1
all_values[6]	auto[0]	auto[0]	auto[1]	10627755	1			T1	1		T2	4		T7	3
all_values[6]	auto[0]	auto[1]	auto[0]	992330	1			T1	2		T2	10		T8	10
all_values[6]	auto[0]	auto[1]	auto[1]	10135700	1			T1	2		T2	1		T8	1
all_values[6]	auto[1]	auto[0]	auto[1]	128500	1			T2	2		T8	2		T12	2
all_values[6]	auto[1]	auto[1]	auto[1]	121000	1			T2	2		T8	2		T12	2
all_values[7]	auto[0]	auto[0]	auto[0]	4087020	1			T1	1		T2	13		T3	1
all_values[7]	auto[0]	auto[0]	auto[1]	10483815	1			T1	5		T2	5		T7	3
all_values[7]	auto[0]	auto[1]	auto[0]	1028830	1			T2	4		T8	4		T10	1
all_values[7]	auto[0]	auto[1]	auto[1]	10262400	1			T2	3		T7	2		T8	3
all_values[7]	auto[1]	auto[0]	auto[1]	125950	1			T2	5		T8	5		T12	5
all_values[7]	auto[1]	auto[1]	auto[1]	121000	1			T80	36		T57	2		T58	2
all_values[8]	auto[0]	auto[0]	auto[0]	4085555	1			T1	1		T2	10		T3	1
all_values[8]	auto[0]	auto[0]	auto[1]	10524825	1			T2	6		T7	1		T8	6
all_values[8]	auto[0]	auto[1]	auto[0]	1033265	1			T2	5		T7	3		T8	5
all_values[8]	auto[0]	auto[1]	auto[1]	10219470	1			T1	5		T2	5		T8	5
all_values[8]	auto[1]	auto[0]	auto[1]	127050	1			T2	4		T8	4		T12	4
all_values[8]	auto[1]	auto[1]	auto[1]	118850	1			T80	39		T57	2		T58	2
all_values[9]	auto[0]	auto[0]	auto[0]	4064810	1			T1	1		T2	13		T3	1
all_values[9]	auto[0]	auto[0]	auto[1]	10501530	1			T1	2		T7	2		T9	2
all_values[9]	auto[0]	auto[1]	auto[0]	1015380	1			T2	15		T8	15		T4	9
all_values[9]	auto[0]	auto[1]	auto[1]	10281095	1			T1	3		T7	1		T9	1
all_values[9]	auto[1]	auto[0]	auto[1]	122800	1			T80	31		T57	8		T58	8
all_values[9]	auto[1]	auto[1]	auto[1]	123400	1			T2	2		T8	2		T12	2
all_values[10]	auto[0]	auto[0]	auto[0]	4165080	1			T1	1		T2	7		T3	1
all_values[10]	auto[0]	auto[0]	auto[1]	10302725	1			T1	2		T2	4		T7	1
all_values[10]	auto[0]	auto[1]	auto[0]	982720	1			T1	3		T2	13		T8	13
all_values[10]	auto[0]	auto[1]	auto[1]	10409140	1			T2	1		T7	4		T8	1
all_values[10]	auto[1]	auto[0]	auto[1]	125800	1			T2	1		T8	1		T12	1
all_values[10]	auto[1]	auto[1]	auto[1]	123550	1			T2	4		T8	4		T12	4
all_values[11]	auto[0]	auto[0]	auto[0]	4079270	1			T1	1		T2	9		T3	1
all_values[11]	auto[0]	auto[0]	auto[1]	10337915	1			T2	1		T7	1		T8	1
all_values[11]	auto[0]	auto[1]	auto[0]	1061940	1			T1	1		T2	3		T8	3
all_values[11]	auto[0]	auto[1]	auto[1]	10382040	1			T1	4		T2	12		T7	4
all_values[11]	auto[1]	auto[0]	auto[1]	127050	1			T2	2		T8	2		T12	2
all_values[11]	auto[1]	auto[1]	auto[1]	120800	1			T2	3		T8	3		T12	3
all_values[12]	auto[0]	auto[0]	auto[0]	4130530	1			T1	1		T2	13		T3	1
all_values[12]	auto[0]	auto[0]	auto[1]	9892215	1			T1	1		T2	3		T7	1
all_values[12]	auto[0]	auto[1]	auto[0]	1018835	1			T2	7		T7	1		T8	7
all_values[12]	auto[0]	auto[1]	auto[1]	10820085	1			T1	4		T2	1		T7	3
all_values[12]	auto[1]	auto[0]	auto[1]	120700	1			T2	2		T8	2		T12	2
all_values[12]	auto[1]	auto[1]	auto[1]	126650	1			T2	4		T8	4		T12	4
all_values[13]	auto[0]	auto[0]	auto[0]	4119220	1			T1	1		T2	13		T3	1
all_values[13]	auto[0]	auto[0]	auto[1]	10140485	1			T1	1		T2	2		T7	3
all_values[13]	auto[0]	auto[1]	auto[0]	956980	1			T2	7		T8	7		T10	2
all_values[13]	auto[0]	auto[1]	auto[1]	10648480	1			T1	4		T2	4		T7	2
all_values[13]	auto[1]	auto[0]	auto[1]	119200	1			T2	1		T8	1		T12	1
all_values[13]	auto[1]	auto[1]	auto[1]	124650	1			T2	3		T8	3		T12	3
all_values[14]	auto[0]	auto[0]	auto[0]	4113750	1			T1	2		T2	6		T3	1
all_values[14]	auto[0]	auto[0]	auto[1]	10344275	1			T2	10		T7	1		T8	10
all_values[14]	auto[0]	auto[1]	auto[0]	1063510	1			T1	3		T2	4		T8	4
all_values[14]	auto[0]	auto[1]	auto[1]	10344680	1			T1	1		T2	4		T7	4
all_values[14]	auto[1]	auto[0]	auto[1]	120900	1			T2	4		T8	4		T12	4
all_values[14]	auto[1]	auto[1]	auto[1]	121900	1			T2	2		T8	2		T12	2
all_values[15]	auto[0]	auto[0]	auto[0]	4088785	1			T1	3		T2	6		T3	1
all_values[15]	auto[0]	auto[0]	auto[1]	10448750	1			T2	2		T8	2		T4	7
all_values[15]	auto[0]	auto[1]	auto[0]	1024370	1			T1	3		T2	15		T7	4
all_values[15]	auto[0]	auto[1]	auto[1]	10301160	1			T2	3		T8	3		T4	5
all_values[15]	auto[1]	auto[0]	auto[1]	122600	1			T2	2		T8	2		T12	2
all_values[15]	auto[1]	auto[1]	auto[1]	123350	1			T2	2		T8	2		T12	2
all_values[16]	auto[0]	auto[0]	auto[0]	4075350	1			T1	4		T2	16		T3	1
all_values[16]	auto[0]	auto[0]	auto[1]	10277870	1			T2	4		T7	4		T8	4
all_values[16]	auto[0]	auto[1]	auto[0]	988100	1			T2	1		T8	1		T4	7
all_values[16]	auto[0]	auto[1]	auto[1]	10517095	1			T1	2		T2	3		T7	1
all_values[16]	auto[1]	auto[0]	auto[1]	126550	1			T2	6		T8	6		T12	6
all_values[16]	auto[1]	auto[1]	auto[1]	124050	1			T80	30		T57	1		T58	1
all_values[17]	auto[0]	auto[0]	auto[0]	4139500	1			T1	1		T2	7		T3	1
all_values[17]	auto[0]	auto[0]	auto[1]	10079420	1			T1	2		T2	5		T8	5
all_values[17]	auto[0]	auto[1]	auto[0]	952780	1			T1	3		T2	10		T7	4
all_values[17]	auto[0]	auto[1]	auto[1]	10693515	1			T2	4		T7	1		T8	4
all_values[17]	auto[1]	auto[0]	auto[1]	120550	1			T2	3		T8	3		T12	3
all_values[17]	auto[1]	auto[1]	auto[1]	123250	1			T2	1		T8	1		T12	1
all_values[18]	auto[0]	auto[0]	auto[0]	4215210	1			T1	4		T2	6		T3	1
all_values[18]	auto[0]	auto[0]	auto[1]	10566500	1			T2	4		T8	4		T10	1
all_values[18]	auto[0]	auto[1]	auto[0]	962515	1			T1	1		T2	7		T7	1
all_values[18]	auto[0]	auto[1]	auto[1]	10118590	1			T1	1		T2	8		T8	8
all_values[18]	auto[1]	auto[0]	auto[1]	122050	1			T2	4		T8	4		T12	4
all_values[18]	auto[1]	auto[1]	auto[1]	124150	1			T2	1		T8	1		T12	1
all_values[19]	auto[0]	auto[0]	auto[0]	4132000	1			T1	1		T2	4		T3	1
all_values[19]	auto[0]	auto[0]	auto[1]	10538835	1			T2	3		T7	1		T8	3
all_values[19]	auto[0]	auto[1]	auto[0]	982050	1			T2	10		T8	10		T4	3
all_values[19]	auto[0]	auto[1]	auto[1]	10207830	1			T1	5		T2	10		T7	4
all_values[19]	auto[1]	auto[0]	auto[1]	128150	1			T2	1		T8	1		T12	1
all_values[19]	auto[1]	auto[1]	auto[1]	120150	1			T2	2		T8	2		T12	2
all_values[20]	auto[0]	auto[0]	auto[0]	4099850	1			T1	1		T2	11		T3	1
all_values[20]	auto[0]	auto[0]	auto[1]	10056255	1			T1	4		T2	1		T7	1
all_values[20]	auto[0]	auto[1]	auto[0]	942220	1			T2	12		T8	12		T4	5
all_values[20]	auto[0]	auto[1]	auto[1]	10766490	1			T1	1		T2	3		T7	4
all_values[20]	auto[1]	auto[0]	auto[1]	120800	1			T80	39		T57	4		T58	4
all_values[20]	auto[1]	auto[1]	auto[1]	123400	1			T2	3		T8	3		T12	3
all_values[21]	auto[0]	auto[0]	auto[0]	4133420	1			T1	1		T2	2		T3	1
all_values[21]	auto[0]	auto[0]	auto[1]	10731555	1			T1	5		T7	1		T9	1
all_values[21]	auto[0]	auto[1]	auto[0]	1038560	1			T2	19		T8	19		T4	5
all_values[21]	auto[0]	auto[1]	auto[1]	9959930	1			T2	5		T7	4		T8	5
all_values[21]	auto[1]	auto[0]	auto[1]	127650	1			T80	36		T57	4		T58	4
all_values[21]	auto[1]	auto[1]	auto[1]	117900	1			T2	4		T8	4		T12	4
all_values[22]	auto[0]	auto[0]	auto[0]	4109050	1			T1	1		T2	10		T3	1
all_values[22]	auto[0]	auto[0]	auto[1]	10069225	1			T2	1		T7	1		T8	1
all_values[22]	auto[0]	auto[1]	auto[0]	978415	1			T1	1		T2	15		T7	1
all_values[22]	auto[0]	auto[1]	auto[1]	10705075	1			T1	4		T2	1		T7	3
all_values[22]	auto[1]	auto[0]	auto[1]	122600	1			T2	2		T8	2		T12	2
all_values[22]	auto[1]	auto[1]	auto[1]	124650	1			T2	1		T8	1		T12	1
all_values[23]	auto[0]	auto[0]	auto[0]	4170545	1			T1	2		T2	8		T3	1
all_values[23]	auto[0]	auto[0]	auto[1]	10601865	1			T2	5		T7	1		T8	5
all_values[23]	auto[0]	auto[1]	auto[0]	988925	1			T1	4		T2	5		T7	3
all_values[23]	auto[0]	auto[1]	auto[1]	10102230	1			T2	7		T8	7		T4	4
all_values[23]	auto[1]	auto[0]	auto[1]	123700	1			T2	2		T8	2		T12	2
all_values[23]	auto[1]	auto[1]	auto[1]	121750	1			T2	3		T8	3		T12	3
all_values[24]	auto[0]	auto[0]	auto[0]	4152090	1			T1	1		T2	5		T3	1
all_values[24]	auto[0]	auto[0]	auto[1]	10669465	1			T2	7		T7	3		T8	7
all_values[24]	auto[0]	auto[1]	auto[0]	983890	1			T1	4		T2	12		T8	12
all_values[24]	auto[0]	auto[1]	auto[1]	10057570	1			T1	1		T2	2		T7	2
all_values[24]	auto[1]	auto[0]	auto[1]	124750	1			T2	2		T8	2		T12	2
all_values[24]	auto[1]	auto[1]	auto[1]	121250	1			T2	2		T8	2		T12	2
all_values[25]	auto[0]	auto[0]	auto[0]	4183980	1			T1	1		T2	12		T3	1
all_values[25]	auto[0]	auto[0]	auto[1]	10238695	1			T1	4		T2	2		T7	5
all_values[25]	auto[0]	auto[1]	auto[0]	1036320	1			T2	2		T8	2		T4	6
all_values[25]	auto[0]	auto[1]	auto[1]	10404570	1			T1	1		T2	8		T8	8
all_values[25]	auto[1]	auto[0]	auto[1]	121250	1			T2	3		T8	3		T12	3
all_values[25]	auto[1]	auto[1]	auto[1]	124200	1			T2	3		T8	3		T12	3
all_values[26]	auto[0]	auto[0]	auto[0]	4170530	1			T1	1		T2	22		T3	1
all_values[26]	auto[0]	auto[0]	auto[1]	10507685	1			T1	1		T2	1		T7	3
all_values[26]	auto[0]	auto[1]	auto[0]	1135360	1			T1	3		T2	5		T8	5
all_values[26]	auto[0]	auto[1]	auto[1]	10051140	1			T1	1		T7	2		T9	2
all_values[26]	auto[1]	auto[0]	auto[1]	122150	1			T2	1		T8	1		T12	1
all_values[26]	auto[1]	auto[1]	auto[1]	122150	1			T2	1		T8	1		T12	1
all_values[27]	auto[0]	auto[0]	auto[0]	4073920	1			T1	1		T2	6		T3	1
all_values[27]	auto[0]	auto[0]	auto[1]	10449610	1			T1	1		T2	10		T7	4
all_values[27]	auto[0]	auto[1]	auto[0]	960170	1			T1	1		T2	3		T8	3
all_values[27]	auto[0]	auto[1]	auto[1]	10379115	1			T1	3		T2	6		T7	1
all_values[27]	auto[1]	auto[0]	auto[1]	119550	1			T2	4		T8	4		T12	4
all_values[27]	auto[1]	auto[1]	auto[1]	126650	1			T2	1		T8	1		T12	1
all_values[28]	auto[0]	auto[0]	auto[0]	4165390	1			T1	1		T2	4		T3	1
all_values[28]	auto[0]	auto[0]	auto[1]	10598735	1			T1	4		T2	7		T7	1
all_values[28]	auto[0]	auto[1]	auto[0]	1048960	1			T2	8		T8	8		T10	1
all_values[28]	auto[0]	auto[1]	auto[1]	10049930	1			T1	1		T2	6		T7	4
all_values[28]	auto[1]	auto[0]	auto[1]	126650	1			T2	1		T8	1		T12	1
all_values[28]	auto[1]	auto[1]	auto[1]	119350	1			T2	4		T8	4		T12	4
all_values[29]	auto[0]	auto[0]	auto[0]	4193760	1			T1	1		T2	3		T3	1
all_values[29]	auto[0]	auto[0]	auto[1]	10455615	1			T1	5		T2	5		T7	5
all_values[29]	auto[0]	auto[1]	auto[0]	1001130	1			T2	4		T8	4		T10	1
all_values[29]	auto[0]	auto[1]	auto[1]	10212310	1			T2	13		T8	13		T10	1
all_values[29]	auto[1]	auto[0]	auto[1]	122150	1			T2	1		T8	1		T12	1
all_values[29]	auto[1]	auto[1]	auto[1]	124050	1			T2	4		T8	4		T12	4
all_values[30]	auto[0]	auto[0]	auto[0]	4163140	1			T1	4		T2	23		T3	1
all_values[30]	auto[0]	auto[0]	auto[1]	10282905	1			T1	1		T7	1		T9	1
all_values[30]	auto[0]	auto[1]	auto[0]	1034330	1			T2	7		T8	7		T10	1
all_values[30]	auto[0]	auto[1]	auto[1]	10383340	1			T1	1		T7	4		T9	4
all_values[30]	auto[1]	auto[0]	auto[1]	119700	1			T80	34		T57	10		T58	10
all_values[30]	auto[1]	auto[1]	auto[1]	125600	1			T80	41		T57	1		T58	1
all_values[31]	auto[0]	auto[0]	auto[0]	4102220	1			T1	1		T2	5		T3	1
all_values[31]	auto[0]	auto[0]	auto[1]	10466535	1			T1	1		T2	2		T7	1
all_values[31]	auto[0]	auto[1]	auto[0]	1058370	1			T2	9		T7	4		T8	9
all_values[31]	auto[0]	auto[1]	auto[1]	10239490	1			T1	4		T2	10		T8	10
all_values[31]	auto[1]	auto[0]	auto[1]	120000	1			T2	2		T8	2		T12	2
all_values[31]	auto[1]	auto[1]	auto[1]	122400	1			T2	2		T8	2		T12	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal