Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[1]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[2]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[3]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[4]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[5]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[6]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[7]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[8]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[9]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[10]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[11]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[12]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[13]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[14]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[15]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[16]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[17]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[18]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[19]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[20]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[21]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[22]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[23]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[24]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[25]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[26]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[27]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[28]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[29]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[30]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[31]	25482115	1			T1	6		T2	1		T3	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

513033530

1

T1

192

T2

32

T3

32

auto[1]

302394150

1

T13

7100

T14

7100

T15

7100

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667535830

1

T1

192

T2

32

T3

32

auto[1]

147891850

1

T13

10576

T14

10576

T15

10576

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623352380

1

T1

192

T2

32

T3

32

auto[1]

192075300

1

T13

10980

T14

10980

T15

10980

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	10221215	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	6942900	1			T13	61		T14	61		T15	61
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2343100	1			T13	141		T14	141		T15	141
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	3458350	1			T13	204		T14	204		T15	204
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	249450	1			T56	19		T63	27		T64	19
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2267100	1			T13	140		T14	140		T15	140
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	10200665	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	6925700	1			T13	63		T14	63		T15	63
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2327750	1			T13	202		T14	202		T15	202
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	3453100	1			T13	124		T14	124		T15	124
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	249700	1			T56	28		T63	15		T64	28
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2325200	1			T13	199		T14	199		T15	199
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	10225165	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	6891550	1			T13	54		T14	54		T15	54
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2342850	1			T13	201		T14	201		T15	201
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	3460850	1			T13	128		T14	128		T15	128
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	258300	1			T56	26		T63	16		T64	26
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2303400	1			T13	208		T14	208		T15	208
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	10155615	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	6978500	1			T13	59		T14	59		T15	59
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2291300	1			T13	129		T14	129		T15	129
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	3464900	1			T13	196		T14	196		T15	196
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	258000	1			T56	19		T63	6		T64	19
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2333800	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	10194215	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	6887550	1			T13	58		T14	58		T15	58
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2336900	1			T13	144		T14	144		T15	144
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	3520700	1			T13	196		T14	196		T15	196
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	265650	1			T56	23		T63	23		T64	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2277100	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	10292715	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	6895200	1			T13	56		T14	56		T15	56
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2289300	1			T13	190		T14	190		T15	190
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	3434700	1			T13	186		T14	186		T15	186
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	242350	1			T56	25		T63	24		T64	25
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2327850	1			T13	162		T14	162		T15	162
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	10208815	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	6962800	1			T13	57		T14	57		T15	57
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2359500	1			T13	187		T14	187		T15	187
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	3453400	1			T13	182		T14	182		T15	182
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	252350	1			T56	20		T63	15		T64	20
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2245250	1			T13	154		T14	154		T15	154
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	10248915	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	6924350	1			T13	62		T14	62		T15	62
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2290550	1			T13	140		T14	140		T15	140
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	3445450	1			T13	194		T14	194		T15	194
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	254750	1			T56	47		T63	39		T64	47
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2318100	1			T13	125		T14	125		T15	125
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	10189315	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	7005350	1			T13	55		T14	55		T15	55
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2344100	1			T13	136		T14	136		T15	136
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	3393700	1			T13	199		T14	199		T15	199
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	255350	1			T56	31		T63	6		T64	31
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2294300	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	10222915	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	6848850	1			T13	59		T14	59		T15	59
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2353050	1			T13	176		T14	176		T15	176
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	3488550	1			T13	198		T14	198		T15	198
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	244250	1			T56	22		T63	14		T64	22
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2324500	1			T13	185		T14	185		T15	185
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	10310915	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	6863100	1			T13	52		T14	52		T15	52
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2335000	1			T13	169		T14	169		T15	169
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	3441100	1			T13	184		T14	184		T15	184
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	250850	1			T56	20		T63	38		T64	20
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2281150	1			T13	148		T14	148		T15	148
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	10248215	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	6822900	1			T13	55		T14	55		T15	55
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2332250	1			T13	158		T14	158		T15	158
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	3524800	1			T13	214		T14	214		T15	214
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	263800	1			T56	34		T63	7		T64	34
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2290150	1			T13	162		T14	162		T15	162
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	10314515	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	6866550	1			T13	53		T14	53		T15	53
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2327600	1			T13	150		T14	150		T15	150
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	3434300	1			T13	181		T14	181		T15	181
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	253250	1			T56	22		T63	7		T64	22
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2285900	1			T13	182		T14	182		T15	182
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	10167015	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	6919550	1			T13	52		T14	52		T15	52
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2344000	1			T13	166		T14	166		T15	166
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	3469550	1			T13	176		T14	176		T15	176
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	264650	1			T56	25		T63	27		T64	25
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2317350	1			T13	171		T14	171		T15	171
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	10306865	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	6844650	1			T13	50		T14	50		T15	50
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2338150	1			T13	128		T14	128		T15	128
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	3482600	1			T13	220		T14	220		T15	220
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	251600	1			T56	17		T63	22		T64	17
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2258250	1			T13	180		T14	180		T15	180
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	10353315	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	6800000	1			T13	64		T14	64		T15	64
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2308250	1			T13	164		T14	164		T15	164
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	3479000	1			T13	183		T14	183		T15	183
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	253850	1			T56	30		T63	28		T64	30
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2287700	1			T13	148		T14	148		T15	148
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	10293615	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	6881350	1			T13	56		T14	56		T15	56
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2300200	1			T13	214		T14	214		T15	214
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	3450400	1			T13	122		T14	122		T15	122
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	249850	1			T56	44		T63	16		T64	44
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2306700	1			T13	182		T14	182		T15	182
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	10249315	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	6865300	1			T13	57		T14	57		T15	57
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2348250	1			T13	148		T14	148		T15	148
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	3459500	1			T13	222		T14	222		T15	222
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	264900	1			T56	28		T63	28		T64	28
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2294850	1			T13	149		T14	149		T15	149
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	10375765	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	6794000	1			T13	55		T14	55		T15	55
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2332150	1			T13	183		T14	183		T15	183
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	3444150	1			T13	162		T14	162		T15	162
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	255250	1			T56	28		T63	20		T64	28
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2280800	1			T13	178		T14	178		T15	178
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	10174565	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	6934700	1			T13	59		T14	59		T15	59
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2311100	1			T13	184		T14	184		T15	184
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	3483300	1			T13	139		T14	139		T15	139
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	265050	1			T56	29		T63	26		T64	29
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2313400	1			T13	164		T14	164		T15	164
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	10233465	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	6944300	1			T13	58		T14	58		T15	58
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2276500	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	3476350	1			T13	162		T14	162		T15	162
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	252550	1			T56	17		T63	5		T64	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2298950	1			T13	129		T14	129		T15	129
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	10259465	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	6891950	1			T13	64		T14	64		T15	64
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2361700	1			T13	152		T14	152		T15	152
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	3436800	1			T13	184		T14	184		T15	184
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	259900	1			T56	20		T63	28		T64	20
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2272300	1			T13	176		T14	176		T15	176
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	10265715	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	6867150	1			T13	56		T14	56		T15	56
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2370600	1			T13	160		T14	160		T15	160
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	3433700	1			T13	168		T14	168		T15	168
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	257200	1			T56	31		T63	13		T64	31
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2287750	1			T13	180		T14	180		T15	180
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	10375115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	6908150	1			T13	54		T14	54		T15	54
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2331800	1			T13	166		T14	166		T15	166
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3383150	1			T13	174		T14	174		T15	174
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	239800	1			T56	30		T63	5		T64	30
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2244100	1			T13	138		T14	138		T15	138
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	10287565	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	6852850	1			T13	55		T14	55		T15	55
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2313950	1			T13	142		T14	142		T15	142
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	3465250	1			T13	181		T14	181		T15	181
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	271350	1			T56	28		T63	35		T64	28
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2291150	1			T13	142		T14	142		T15	142
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	10133065	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	7028350	1			T13	58		T14	58		T15	58
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2340350	1			T13	194		T14	194		T15	194
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	3456650	1			T13	144		T14	144		T15	144
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	251350	1			T56	25		T63	23		T64	25
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2272350	1			T13	159		T14	159		T15	159
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	10227865	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	6922900	1			T13	60		T14	60		T15	60
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2344200	1			T13	176		T14	176		T15	176
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	3411200	1			T13	151		T14	151		T15	151
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	251800	1			T56	33		T63	31		T64	33
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2324150	1			T13	196		T14	196		T15	196
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	10238565	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	6917200	1			T13	54		T14	54		T15	54
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2367400	1			T13	160		T14	160		T15	160
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	3419650	1			T13	198		T14	198		T15	198
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	255800	1			T56	30		T63	22		T64	30
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2283500	1			T13	181		T14	181		T15	181
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	10134715	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	6952950	1			T13	54		T14	54		T15	54
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2287250	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	3526350	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	259900	1			T56	13		T63	45		T64	13
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2320950	1			T13	132		T14	132		T15	132
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	10261815	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	6920800	1			T13	46		T14	46		T15	46
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2333900	1			T13	158		T14	158		T15	158
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	3418300	1			T13	165		T14	165		T15	165
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	244300	1			T56	20		T63	19		T64	20
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2303000	1			T13	174		T14	174		T15	174
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	10324565	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	6906250	1			T13	54		T14	54		T15	54
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2309650	1			T13	152		T14	152		T15	152
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	3443400	1			T13	206		T14	206		T15	206
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	258000	1			T56	21		T63	24		T64	21
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2240250	1			T13	157		T14	157		T15	157
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	10234865	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	6911000	1			T13	61		T14	61		T15	61
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2350600	1			T13	173		T14	173		T15	173
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	3446650	1			T13	176		T14	176		T15	176
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	261700	1			T56	43		T63	20		T64	43
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2277300	1			T13	172		T14	172		T15	172

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal