Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[1]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[2]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[3]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[4]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[5]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[6]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[7]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[8]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[9]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[10]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[11]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[12]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[13]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[14]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[15]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[16]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[17]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[18]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[19]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[20]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[21]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[22]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[23]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[24]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[25]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[26]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[27]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[28]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[29]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[30]	25482115	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[31]	25482115	1			T1	6		T2	1		T3	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

513033530

1

T1

192

T2

32

T3

32

auto[1]

302394150

1

T13

7100

T14

7100

T15

7100

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

513008185

1

T1

156

T2

32

T3

32

auto[1]

302419495

1

T1

36

T7

41

T9

41

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	15605765	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	416200	1			T13	41		T14	41		T15	41
bins_for_gpio_bits[0]	auto[1]	auto[0]	416900	1			T1	1		T4	8		T5	8
bins_for_gpio_bits[0]	auto[1]	auto[1]	9043250	1			T13	160		T14	160		T15	160
bins_for_gpio_bits[1]	auto[0]	auto[0]	15558140	1			T1	4		T2	1		T3	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	422250	1			T13	43		T14	43		T15	43
bins_for_gpio_bits[1]	auto[1]	auto[0]	423375	1			T1	2		T7	1		T9	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	9078350	1			T13	219		T14	219		T15	219
bins_for_gpio_bits[2]	auto[0]	auto[0]	15607010	1			T1	4		T2	1		T3	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	420850	1			T13	46		T14	46		T15	46
bins_for_gpio_bits[2]	auto[1]	auto[0]	421855	1			T1	2		T7	1		T9	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	9032400	1			T13	216		T14	216		T15	216
bins_for_gpio_bits[3]	auto[0]	auto[0]	15491575	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	419500	1			T13	40		T14	40		T15	40
bins_for_gpio_bits[3]	auto[1]	auto[0]	420240	1			T1	1		T4	7		T5	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	9150800	1			T13	191		T14	191		T15	191
bins_for_gpio_bits[4]	auto[0]	auto[0]	15633175	1			T1	4		T2	1		T3	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	418000	1			T13	44		T14	44		T15	44
bins_for_gpio_bits[4]	auto[1]	auto[0]	418640	1			T1	2		T7	3		T9	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	9012300	1			T13	186		T14	186		T15	186
bins_for_gpio_bits[5]	auto[0]	auto[0]	15600605	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	415350	1			T13	48		T14	48		T15	48
bins_for_gpio_bits[5]	auto[1]	auto[0]	416110	1			T1	1		T4	8		T5	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	9050050	1			T13	170		T14	170		T15	170
bins_for_gpio_bits[6]	auto[0]	auto[0]	15610090	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	410900	1			T13	44		T14	44		T15	44
bins_for_gpio_bits[6]	auto[1]	auto[0]	411625	1			T1	1		T7	1		T9	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	9049500	1			T13	167		T14	167		T15	167
bins_for_gpio_bits[7]	auto[0]	auto[0]	15568195	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	415850	1			T13	36		T14	36		T15	36
bins_for_gpio_bits[7]	auto[1]	auto[0]	416720	1			T7	1		T9	1		T10	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	9081350	1			T13	151		T14	151		T15	151
bins_for_gpio_bits[8]	auto[0]	auto[0]	15511860	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	414700	1			T13	41		T14	41		T15	41
bins_for_gpio_bits[8]	auto[1]	auto[0]	415255	1			T1	1		T7	1		T9	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	9140300	1			T13	186		T14	186		T15	186
bins_for_gpio_bits[9]	auto[0]	auto[0]	15639395	1			T1	2		T2	1		T3	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	424100	1			T13	47		T14	47		T15	47
bins_for_gpio_bits[9]	auto[1]	auto[0]	425120	1			T1	4		T7	4		T9	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	8993500	1			T13	197		T14	197		T15	197
bins_for_gpio_bits[10]	auto[0]	auto[0]	15668785	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	417700	1			T13	39		T14	39		T15	39
bins_for_gpio_bits[10]	auto[1]	auto[0]	418230	1			T4	3		T5	3		T6	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	8977400	1			T13	161		T14	161		T15	161
bins_for_gpio_bits[11]	auto[0]	auto[0]	15684025	1			T1	4		T2	1		T3	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	420350	1			T13	45		T14	45		T15	45
bins_for_gpio_bits[11]	auto[1]	auto[0]	421240	1			T1	2		T10	1		T4	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	8956500	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[12]	auto[0]	auto[0]	15659255	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	416650	1			T13	48		T14	48		T15	48
bins_for_gpio_bits[12]	auto[1]	auto[0]	417160	1			T7	2		T9	2		T4	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	8989050	1			T13	187		T14	187		T15	187
bins_for_gpio_bits[13]	auto[0]	auto[0]	15558740	1			T1	4		T2	1		T3	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	420700	1			T13	45		T14	45		T15	45
bins_for_gpio_bits[13]	auto[1]	auto[0]	421825	1			T1	2		T7	5		T9	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	9080850	1			T13	178		T14	178		T15	178
bins_for_gpio_bits[14]	auto[0]	auto[0]	15711825	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	415100	1			T13	48		T14	48		T15	48
bins_for_gpio_bits[14]	auto[1]	auto[0]	415790	1			T1	1		T7	4		T9	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	8939400	1			T13	182		T14	182		T15	182
bins_for_gpio_bits[15]	auto[0]	auto[0]	15723685	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	416150	1			T13	41		T14	41		T15	41
bins_for_gpio_bits[15]	auto[1]	auto[0]	416880	1			T1	1		T4	7		T5	7
bins_for_gpio_bits[15]	auto[1]	auto[1]	8925400	1			T13	171		T14	171		T15	171
bins_for_gpio_bits[16]	auto[0]	auto[0]	15630440	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	413250	1			T13	45		T14	45		T15	45
bins_for_gpio_bits[16]	auto[1]	auto[0]	413775	1			T10	2		T4	6		T11	2
bins_for_gpio_bits[16]	auto[1]	auto[1]	9024650	1			T13	193		T14	193		T15	193
bins_for_gpio_bits[17]	auto[0]	auto[0]	15638175	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	418000	1			T13	43		T14	43		T15	43
bins_for_gpio_bits[17]	auto[1]	auto[0]	418890	1			T7	2		T9	2		T4	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	9007050	1			T13	163		T14	163		T15	163
bins_for_gpio_bits[18]	auto[0]	auto[0]	15732315	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	418850	1			T13	43		T14	43		T15	43
bins_for_gpio_bits[18]	auto[1]	auto[0]	419750	1			T1	1		T4	6		T5	6
bins_for_gpio_bits[18]	auto[1]	auto[1]	8911200	1			T13	190		T14	190		T15	190
bins_for_gpio_bits[19]	auto[0]	auto[0]	15548640	1			T1	3		T2	1		T3	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	419450	1			T13	41		T14	41		T15	41
bins_for_gpio_bits[19]	auto[1]	auto[0]	420325	1			T1	3		T7	1		T9	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	9093700	1			T13	182		T14	182		T15	182
bins_for_gpio_bits[20]	auto[0]	auto[0]	15570160	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	415200	1			T13	35		T14	35		T15	35
bins_for_gpio_bits[20]	auto[1]	auto[0]	416155	1			T1	1		T7	1		T9	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	9080600	1			T13	152		T14	152		T15	152
bins_for_gpio_bits[21]	auto[0]	auto[0]	15647020	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	410350	1			T13	40		T14	40		T15	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	410945	1			T1	1		T7	1		T9	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	9013800	1			T13	200		T14	200		T15	200
bins_for_gpio_bits[22]	auto[0]	auto[0]	15652670	1			T1	2		T2	1		T3	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	416650	1			T13	41		T14	41		T15	41
bins_for_gpio_bits[22]	auto[1]	auto[0]	417345	1			T1	4		T7	2		T9	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	8995450	1			T13	195		T14	195		T15	195
bins_for_gpio_bits[23]	auto[0]	auto[0]	15676540	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	413050	1			T13	41		T14	41		T15	41
bins_for_gpio_bits[23]	auto[1]	auto[0]	413525	1			T1	1		T7	1		T9	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	8979000	1			T13	151		T14	151		T15	151
bins_for_gpio_bits[24]	auto[0]	auto[0]	15645405	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	420600	1			T13	36		T14	36		T15	36
bins_for_gpio_bits[24]	auto[1]	auto[0]	421360	1			T1	1		T7	1		T9	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	8994750	1			T13	161		T14	161		T15	161
bins_for_gpio_bits[25]	auto[0]	auto[0]	15517475	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	411650	1			T13	38		T14	38		T15	38
bins_for_gpio_bits[25]	auto[1]	auto[0]	412590	1			T7	2		T9	2		T4	11
bins_for_gpio_bits[25]	auto[1]	auto[1]	9140400	1			T13	179		T14	179		T15	179
bins_for_gpio_bits[26]	auto[0]	auto[0]	15559070	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	423150	1			T13	47		T14	47		T15	47
bins_for_gpio_bits[26]	auto[1]	auto[0]	424195	1			T7	1		T9	1		T4	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	9075700	1			T13	209		T14	209		T15	209
bins_for_gpio_bits[27]	auto[0]	auto[0]	15602780	1			T1	5		T2	1		T3	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	421800	1			T13	52		T14	52		T15	52
bins_for_gpio_bits[27]	auto[1]	auto[0]	422835	1			T1	1		T7	2		T9	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	9034700	1			T13	183		T14	183		T15	183
bins_for_gpio_bits[28]	auto[0]	auto[0]	15527490	1			T1	4		T2	1		T3	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	419900	1			T13	38		T14	38		T15	38
bins_for_gpio_bits[28]	auto[1]	auto[0]	420825	1			T1	2		T7	1		T9	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	9113900	1			T13	148		T14	148		T15	148
bins_for_gpio_bits[29]	auto[0]	auto[0]	15594940	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	418300	1			T13	43		T14	43		T15	43
bins_for_gpio_bits[29]	auto[1]	auto[0]	419075	1			T10	2		T4	4		T11	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	9049800	1			T13	177		T14	177		T15	177
bins_for_gpio_bits[30]	auto[0]	auto[0]	15660100	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	416800	1			T13	39		T14	39		T15	39
bins_for_gpio_bits[30]	auto[1]	auto[0]	417515	1			T7	2		T9	2		T4	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	8987700	1			T13	172		T14	172		T15	172
bins_for_gpio_bits[31]	auto[0]	auto[0]	15619490	1			T1	6		T2	1		T3	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	412000	1			T13	46		T14	46		T15	46
bins_for_gpio_bits[31]	auto[1]	auto[0]	412625	1			T7	1		T9	1		T10	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	9038000	1			T13	187		T14	187		T15	187