Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14863810 |
1 |
|
|
T1 |
1 |
|
T2 |
14 |
|
T3 |
1 |
| auto[1] |
11245205 |
1 |
|
|
T1 |
5 |
|
T2 |
16 |
|
T7 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24580465 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1528550 |
1 |
|
|
T80 |
30 |
|
T74 |
14 |
|
T75 |
6429 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15035990 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11073025 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4869905 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T10 |
2 |
| auto[1] |
auto[0] |
auto[1] |
786500 |
1 |
|
|
T80 |
9 |
|
T74 |
10 |
|
T75 |
3475 |
| auto[1] |
auto[1] |
auto[0] |
4674570 |
1 |
|
|
T1 |
1 |
|
T4 |
5 |
|
T5 |
5 |
| auto[1] |
auto[1] |
auto[1] |
742050 |
1 |
|
|
T80 |
21 |
|
T74 |
4 |
|
T75 |
2954 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14561025 |
1 |
|
|
T1 |
2 |
|
T2 |
11 |
|
T3 |
1 |
| auto[1] |
11547990 |
1 |
|
|
T1 |
4 |
|
T2 |
19 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24513180 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1595835 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14616685 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11492330 |
1 |
|
|
T7 |
2 |
|
T9 |
2 |
|
T10 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4956360 |
1 |
|
|
T10 |
2 |
|
T4 |
7 |
|
T11 |
2 |
| auto[1] |
auto[0] |
auto[1] |
802930 |
1 |
|
|
T27 |
4 |
|
T37 |
4 |
|
T42 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4940135 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
792905 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14593605 |
1 |
|
|
T1 |
3 |
|
T2 |
12 |
|
T3 |
1 |
| auto[1] |
11515410 |
1 |
|
|
T1 |
3 |
|
T2 |
18 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24555465 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1553550 |
1 |
|
|
T80 |
34 |
|
T57 |
1 |
|
T74 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14874750 |
1 |
|
|
T1 |
1 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11234265 |
1 |
|
|
T1 |
5 |
|
T7 |
5 |
|
T9 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4785565 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[0] |
auto[1] |
763450 |
1 |
|
|
T80 |
15 |
|
T57 |
1 |
|
T74 |
10 |
| auto[1] |
auto[1] |
auto[0] |
4895150 |
1 |
|
|
T1 |
3 |
|
T7 |
4 |
|
T9 |
4 |
| auto[1] |
auto[1] |
auto[1] |
790100 |
1 |
|
|
T80 |
19 |
|
T74 |
8 |
|
T75 |
3196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14544235 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T3 |
1 |
| auto[1] |
11564780 |
1 |
|
|
T1 |
5 |
|
T2 |
18 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24510195 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1598820 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T33 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14587875 |
1 |
|
|
T1 |
1 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11521140 |
1 |
|
|
T1 |
5 |
|
T7 |
4 |
|
T9 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4953095 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T4 |
7 |
| auto[1] |
auto[0] |
auto[1] |
803450 |
1 |
|
|
T80 |
12 |
|
T74 |
7 |
|
T75 |
3259 |
| auto[1] |
auto[1] |
auto[0] |
4969225 |
1 |
|
|
T1 |
4 |
|
T7 |
3 |
|
T9 |
3 |
| auto[1] |
auto[1] |
auto[1] |
795370 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T33 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14143445 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
1 |
| auto[1] |
11965570 |
1 |
|
|
T1 |
4 |
|
T2 |
12 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24482045 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1626970 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14382555 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11726460 |
1 |
|
|
T1 |
1 |
|
T4 |
11 |
|
T5 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4896350 |
1 |
|
|
T4 |
8 |
|
T5 |
8 |
|
T27 |
2 |
| auto[1] |
auto[0] |
auto[1] |
786470 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |
| auto[1] |
auto[1] |
auto[0] |
5203140 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T5 |
3 |
| auto[1] |
auto[1] |
auto[1] |
840500 |
1 |
|
|
T80 |
15 |
|
T74 |
4 |
|
T75 |
3329 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14378905 |
1 |
|
|
T1 |
2 |
|
T2 |
16 |
|
T3 |
1 |
| auto[1] |
11730110 |
1 |
|
|
T1 |
4 |
|
T2 |
14 |
|
T7 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24510125 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1598890 |
1 |
|
|
T1 |
1 |
|
T27 |
6 |
|
T37 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14507710 |
1 |
|
|
T1 |
3 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11601305 |
1 |
|
|
T1 |
3 |
|
T7 |
3 |
|
T9 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4901635 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T4 |
9 |
| auto[1] |
auto[0] |
auto[1] |
782720 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[0] |
5100780 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T9 |
2 |
| auto[1] |
auto[1] |
auto[1] |
816170 |
1 |
|
|
T27 |
6 |
|
T37 |
6 |
|
T42 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14578925 |
1 |
|
|
T1 |
2 |
|
T2 |
20 |
|
T3 |
1 |
| auto[1] |
11530090 |
1 |
|
|
T1 |
4 |
|
T2 |
10 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24543390 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1565625 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14813900 |
1 |
|
|
T1 |
2 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11295115 |
1 |
|
|
T1 |
4 |
|
T7 |
5 |
|
T9 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4986590 |
1 |
|
|
T1 |
1 |
|
T4 |
6 |
|
T5 |
6 |
| auto[1] |
auto[0] |
auto[1] |
810555 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
15 |
| auto[1] |
auto[1] |
auto[0] |
4742900 |
1 |
|
|
T1 |
3 |
|
T7 |
4 |
|
T9 |
4 |
| auto[1] |
auto[1] |
auto[1] |
755070 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14660135 |
1 |
|
|
T1 |
3 |
|
T2 |
10 |
|
T3 |
1 |
| auto[1] |
11448880 |
1 |
|
|
T1 |
3 |
|
T2 |
20 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24475315 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1633700 |
1 |
|
|
T80 |
38 |
|
T57 |
1 |
|
T74 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14430750 |
1 |
|
|
T1 |
4 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11678265 |
1 |
|
|
T1 |
2 |
|
T7 |
5 |
|
T9 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
5047975 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[0] |
auto[1] |
823450 |
1 |
|
|
T80 |
19 |
|
T57 |
1 |
|
T74 |
9 |
| auto[1] |
auto[1] |
auto[0] |
4996590 |
1 |
|
|
T7 |
4 |
|
T9 |
4 |
|
T4 |
6 |
| auto[1] |
auto[1] |
auto[1] |
810250 |
1 |
|
|
T80 |
19 |
|
T74 |
3 |
|
T75 |
3087 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14479770 |
1 |
|
|
T1 |
4 |
|
T2 |
26 |
|
T3 |
1 |
| auto[1] |
11629245 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T7 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24516265 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1592750 |
1 |
|
|
T80 |
40 |
|
T57 |
1 |
|
T74 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14637425 |
1 |
|
|
T1 |
1 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11471590 |
1 |
|
|
T1 |
5 |
|
T7 |
2 |
|
T9 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4757655 |
1 |
|
|
T1 |
3 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[0] |
auto[1] |
759950 |
1 |
|
|
T80 |
16 |
|
T57 |
1 |
|
T74 |
3 |
| auto[1] |
auto[1] |
auto[0] |
5121185 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
832800 |
1 |
|
|
T80 |
24 |
|
T74 |
2 |
|
T75 |
3351 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14339470 |
1 |
|
|
T1 |
3 |
|
T2 |
15 |
|
T3 |
1 |
| auto[1] |
11769545 |
1 |
|
|
T1 |
3 |
|
T2 |
15 |
|
T7 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24535010 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1574005 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
43 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14738315 |
1 |
|
|
T1 |
2 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11370700 |
1 |
|
|
T1 |
4 |
|
T7 |
2 |
|
T9 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4721970 |
1 |
|
|
T1 |
2 |
|
T10 |
1 |
|
T4 |
8 |
| auto[1] |
auto[0] |
auto[1] |
758750 |
1 |
|
|
T80 |
23 |
|
T74 |
8 |
|
T75 |
3139 |
| auto[1] |
auto[1] |
auto[0] |
5074725 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
815255 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14903760 |
1 |
|
|
T1 |
4 |
|
T2 |
14 |
|
T3 |
1 |
| auto[1] |
11205255 |
1 |
|
|
T1 |
2 |
|
T2 |
16 |
|
T7 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24524165 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1584850 |
1 |
|
|
T80 |
41 |
|
T74 |
10 |
|
T75 |
6838 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14691395 |
1 |
|
|
T1 |
2 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11417620 |
1 |
|
|
T1 |
4 |
|
T7 |
4 |
|
T9 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4965595 |
1 |
|
|
T1 |
2 |
|
T7 |
3 |
|
T9 |
3 |
| auto[1] |
auto[0] |
auto[1] |
804750 |
1 |
|
|
T80 |
19 |
|
T74 |
3 |
|
T75 |
3510 |
| auto[1] |
auto[1] |
auto[0] |
4867175 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
780100 |
1 |
|
|
T80 |
22 |
|
T74 |
7 |
|
T75 |
3328 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14798985 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
| auto[1] |
11310030 |
1 |
|
|
T1 |
5 |
|
T2 |
22 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24517415 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1591600 |
1 |
|
|
T27 |
5 |
|
T37 |
5 |
|
T42 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14623285 |
1 |
|
|
T1 |
3 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11485730 |
1 |
|
|
T1 |
3 |
|
T4 |
10 |
|
T5 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
5057280 |
1 |
|
|
T4 |
6 |
|
T5 |
6 |
|
T27 |
3 |
| auto[1] |
auto[0] |
auto[1] |
817150 |
1 |
|
|
T80 |
15 |
|
T74 |
2 |
|
T75 |
3295 |
| auto[1] |
auto[1] |
auto[0] |
4836850 |
1 |
|
|
T1 |
3 |
|
T4 |
4 |
|
T5 |
4 |
| auto[1] |
auto[1] |
auto[1] |
774450 |
1 |
|
|
T27 |
5 |
|
T37 |
5 |
|
T42 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14984420 |
1 |
|
|
T1 |
5 |
|
T2 |
13 |
|
T3 |
1 |
| auto[1] |
11124595 |
1 |
|
|
T1 |
1 |
|
T2 |
17 |
|
T7 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24521540 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1587475 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14668865 |
1 |
|
|
T1 |
4 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11440150 |
1 |
|
|
T1 |
2 |
|
T7 |
4 |
|
T9 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
5200840 |
1 |
|
|
T7 |
2 |
|
T9 |
2 |
|
T10 |
1 |
| auto[1] |
auto[0] |
auto[1] |
844125 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4651835 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
743350 |
1 |
|
|
T80 |
8 |
|
T74 |
7 |
|
T75 |
3070 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14276905 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T3 |
1 |
| auto[1] |
11832110 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24498045 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1610970 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T33 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14446800 |
1 |
|
|
T1 |
3 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11662215 |
1 |
|
|
T1 |
3 |
|
T7 |
1 |
|
T9 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4851790 |
1 |
|
|
T1 |
2 |
|
T4 |
5 |
|
T5 |
5 |
| auto[1] |
auto[0] |
auto[1] |
771470 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[0] |
5199455 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[1] |
839500 |
1 |
|
|
T80 |
16 |
|
T74 |
8 |
|
T75 |
3246 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14992625 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T3 |
1 |
| auto[1] |
11116390 |
1 |
|
|
T2 |
28 |
|
T7 |
4 |
|
T8 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24528090 |
1 |
|
|
T1 |
5 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1580925 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14648580 |
1 |
|
|
T1 |
4 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11460435 |
1 |
|
|
T1 |
2 |
|
T7 |
3 |
|
T9 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
5122775 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[0] |
auto[1] |
823020 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4756735 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[1] |
757905 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14300875 |
1 |
|
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
1 |
| auto[1] |
11808140 |
1 |
|
|
T1 |
5 |
|
T2 |
17 |
|
T7 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24463405 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1645610 |
1 |
|
|
T7 |
2 |
|
T9 |
2 |
|
T80 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14330660 |
1 |
|
|
T1 |
4 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11778355 |
1 |
|
|
T1 |
2 |
|
T7 |
3 |
|
T9 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4875450 |
1 |
|
|
T4 |
4 |
|
T5 |
4 |
|
T27 |
26 |
| auto[1] |
auto[0] |
auto[1] |
781605 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
14 |
| auto[1] |
auto[1] |
auto[0] |
5257295 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
864005 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T80 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14896110 |
1 |
|
|
T1 |
2 |
|
T2 |
15 |
|
T3 |
1 |
| auto[1] |
11212905 |
1 |
|
|
T1 |
4 |
|
T2 |
15 |
|
T7 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24551045 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1557970 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |