Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14999635 |
1 |
|
|
T1 |
2 |
|
T2 |
17 |
|
T3 |
1 |
auto[1] |
11109380 |
1 |
|
|
T1 |
4 |
|
T2 |
13 |
|
T7 |
4 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24467445 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
auto[1] |
1641570 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14363535 |
1 |
|
|
T1 |
4 |
|
T2 |
30 |
|
T3 |
1 |
auto[1] |
11745480 |
1 |
|
|
T1 |
2 |
|
T4 |
11 |
|
T5 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
5262460 |
1 |
|
|
T4 |
8 |
|
T5 |
8 |
|
T27 |
25 |
auto[1] |
auto[0] |
auto[1] |
855220 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |
auto[1] |
auto[1] |
auto[0] |
4841450 |
1 |
|
|
T1 |
2 |
|
T4 |
3 |
|
T5 |
3 |
auto[1] |
auto[1] |
auto[1] |
786350 |
1 |
|
|
T80 |
15 |
|
T74 |
6 |
|
T75 |
3517 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |