Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14696785 |
1 |
|
|
T1 |
6 |
|
T2 |
23 |
|
T3 |
1 |
auto[1] |
11412230 |
1 |
|
|
T2 |
7 |
|
T7 |
2 |
|
T8 |
7 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24532265 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
auto[1] |
1576750 |
1 |
|
|
T80 |
39 |
|
T74 |
13 |
|
T75 |
6535 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14784260 |
1 |
|
|
T1 |
1 |
|
T2 |
30 |
|
T3 |
1 |
auto[1] |
11324755 |
1 |
|
|
T1 |
5 |
|
T7 |
3 |
|
T9 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4993995 |
1 |
|
|
T1 |
5 |
|
T7 |
1 |
|
T9 |
1 |
auto[1] |
auto[0] |
auto[1] |
810050 |
1 |
|
|
T80 |
26 |
|
T74 |
11 |
|
T75 |
3309 |
auto[1] |
auto[1] |
auto[0] |
4754010 |
1 |
|
|
T7 |
2 |
|
T9 |
2 |
|
T4 |
2 |
auto[1] |
auto[1] |
auto[1] |
766700 |
1 |
|
|
T80 |
13 |
|
T74 |
2 |
|
T75 |
3226 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |