Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14869545 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11239470 |
1 |
|
|
T7 |
2 |
|
T9 |
2 |
|
T10 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4864400 |
1 |
|
|
T10 |
1 |
|
T4 |
4 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
786820 |
1 |
|
|
T27 |
1 |
|
T37 |
1 |
|
T42 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4817100 |
1 |
|
|
T7 |
2 |
|
T9 |
2 |
|
T10 |
1 |
| auto[1] |
auto[1] |
auto[1] |
771150 |
1 |
|
|
T80 |
7 |
|
T74 |
4 |
|
T75 |
3165 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |