Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14791180 |
1 |
|
|
T1 |
5 |
|
T2 |
15 |
|
T3 |
1 |
| auto[1] |
11317835 |
1 |
|
|
T1 |
1 |
|
T2 |
15 |
|
T7 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24481165 |
1 |
|
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
1627850 |
1 |
|
|
T80 |
36 |
|
T74 |
5 |
|
T75 |
6447 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14425960 |
1 |
|
|
T1 |
3 |
|
T2 |
30 |
|
T3 |
1 |
| auto[1] |
11683055 |
1 |
|
|
T1 |
3 |
|
T7 |
3 |
|
T9 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
5080690 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T9 |
2 |
| auto[1] |
auto[0] |
auto[1] |
813150 |
1 |
|
|
T80 |
24 |
|
T74 |
3 |
|
T75 |
3254 |
| auto[1] |
auto[1] |
auto[0] |
4974515 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
814700 |
1 |
|
|
T80 |
12 |
|
T74 |
2 |
|
T75 |
3193 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |