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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.50 99.06 98.64 97.88 99.60 95.82 99.97


Total test records in report: 970
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T754 /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.19537924139128466079600388210732354978830952787700467163202982940379957411379 Nov 22 12:26:49 PM PST 23 Nov 22 12:26:52 PM PST 23 81278879 ps
T755 /workspace/coverage/default/48.gpio_filter_stress.115457173807654672950288678720562805920551722175343524778984666461135296162486 Nov 22 12:26:12 PM PST 23 Nov 22 12:26:36 PM PST 23 1135699015 ps
T756 /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.60068962190140110947514647975230269600041570973753059090913747582355862087864 Nov 22 12:26:31 PM PST 23 Nov 22 12:26:34 PM PST 23 112796484 ps
T757 /workspace/coverage/default/15.gpio_random_dout_din.56557797187325891480045929162141298098986566834440510141811574737600746268472 Nov 22 12:26:25 PM PST 23 Nov 22 12:26:31 PM PST 23 81278879 ps
T758 /workspace/coverage/default/5.gpio_filter_stress.77198136429741858640755577340512758431456044107879396838850910300735383690733 Nov 22 12:20:50 PM PST 23 Nov 22 12:21:13 PM PST 23 1135699015 ps
T759 /workspace/coverage/default/10.gpio_alert_test.115549588616482552473433655010853763297371910754738609248127792914444414217585 Nov 22 12:26:54 PM PST 23 Nov 22 12:26:58 PM PST 23 22440064 ps
T760 /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.99316075234383730859333681173712749149269072993111172522475005956408282472242 Nov 22 12:23:11 PM PST 23 Nov 22 12:23:17 PM PST 23 572864232 ps
T761 /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.103583900944911667832585680644174941339312506814991201642093585297630015553458 Nov 22 12:24:46 PM PST 23 Nov 22 12:43:22 PM PST 23 133069054254 ps
T762 /workspace/coverage/default/3.gpio_stress_all.78567829141984837314334064013132928469099146806068225222946676894935988119846 Nov 22 12:27:42 PM PST 23 Nov 22 12:30:34 PM PST 23 21104521406 ps
T763 /workspace/coverage/default/29.gpio_stress_all.64228208048135156423612132795901286474739691822130149272307708122147806086424 Nov 22 12:22:23 PM PST 23 Nov 22 12:25:15 PM PST 23 21104521406 ps
T764 /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.102819166560075331090441739609221294611202967692246440851301862389534855831243 Nov 22 12:26:05 PM PST 23 Nov 22 12:26:08 PM PST 23 81278879 ps
T765 /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.61511435668884695824487958047597845431237620790412197029394566361305338022898 Nov 22 12:26:03 PM PST 23 Nov 22 12:26:08 PM PST 23 134635595 ps
T766 /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.80454761455644122777353464430748921406872687983840693468478137006682755269582 Nov 22 12:21:24 PM PST 23 Nov 22 12:21:27 PM PST 23 57921923 ps
T767 /workspace/coverage/default/30.gpio_rand_intr_trigger.61748939738225096948420580115719765431122734167373999763597147077874689917960 Nov 22 12:27:00 PM PST 23 Nov 22 12:27:10 PM PST 23 228920555 ps
T768 /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.75487636028226287661252453197491595138157464454704361748040432842030101583871 Nov 22 12:25:38 PM PST 23 Nov 22 12:44:00 PM PST 23 133069054254 ps
T769 /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.27530947673014277031789312559644980412257918132521141752399819245082782443924 Nov 22 12:22:09 PM PST 23 Nov 22 12:22:12 PM PST 23 134635595 ps
T770 /workspace/coverage/default/25.gpio_rand_intr_trigger.37541436262181807651252811121172640223840768006905274172078255544327930014077 Nov 22 12:25:52 PM PST 23 Nov 22 12:25:57 PM PST 23 228920555 ps
T771 /workspace/coverage/default/2.gpio_filter_stress.30305212903864136502190218181628673877293390236052323505630212633375914393332 Nov 22 12:27:00 PM PST 23 Nov 22 12:27:28 PM PST 23 1135699015 ps
T772 /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.12486232468674280721965991263989796221665780204200194126354224262654892903784 Nov 22 12:27:57 PM PST 23 Nov 22 12:28:03 PM PST 23 572864232 ps
T773 /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.58613790161685551571055593525678157595833296554759350235129909383060931353368 Nov 22 12:26:23 PM PST 23 Nov 22 12:26:34 PM PST 23 572864232 ps
T774 /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.99630020818298273899428346200373527555740774301897554733596248559325260979463 Nov 22 12:26:26 PM PST 23 Nov 22 12:26:32 PM PST 23 57921923 ps
T775 /workspace/coverage/default/17.gpio_full_random.33122484396737569417733743298064382646184663869129220891967565080950604978025 Nov 22 12:26:20 PM PST 23 Nov 22 12:26:26 PM PST 23 137439144 ps
T776 /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.102017592617308942252660627460917610427768146788815340446041162723747115062720 Nov 22 12:25:53 PM PST 23 Nov 22 12:25:55 PM PST 23 81278879 ps
T777 /workspace/coverage/default/31.gpio_full_random.53061895565438714660947861268565895524228369435954744378689185498362292160793 Nov 22 12:23:40 PM PST 23 Nov 22 12:23:42 PM PST 23 137439144 ps
T778 /workspace/coverage/default/13.gpio_filter_stress.94189401480650494227396305940170435064613042394249324910881519120470306735978 Nov 22 12:27:40 PM PST 23 Nov 22 12:28:11 PM PST 23 1135699015 ps
T779 /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.112024020897992098097561074566009932477041237163559338932291999985922758922406 Nov 22 12:27:17 PM PST 23 Nov 22 12:27:24 PM PST 23 57921923 ps
T780 /workspace/coverage/default/22.gpio_filter_stress.39741501607180261481127470750180639126749772432611080598541300493992470421988 Nov 22 12:26:27 PM PST 23 Nov 22 12:26:52 PM PST 23 1135699015 ps
T781 /workspace/coverage/default/32.gpio_intr_rand_pgm.71126148035677194807765474409252560634081321981210920734585150570466984343554 Nov 22 12:26:02 PM PST 23 Nov 22 12:26:04 PM PST 23 119314289 ps
T782 /workspace/coverage/default/24.gpio_smoke.97175492085347572452206551381045931207919585784327889656948234627445625184699 Nov 22 12:27:09 PM PST 23 Nov 22 12:27:19 PM PST 23 112796484 ps
T783 /workspace/coverage/default/36.gpio_smoke.87221871308057986893314677722382303302875370331199183947742979179469933833881 Nov 22 12:26:49 PM PST 23 Nov 22 12:26:52 PM PST 23 112796484 ps
T784 /workspace/coverage/default/8.gpio_alert_test.109504546735407959447752416484134280533489734241436323116888776380496266211940 Nov 22 12:20:58 PM PST 23 Nov 22 12:21:00 PM PST 23 22440064 ps
T785 /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.59988482687817151809622753897469753283361015893489259485061733100716161772980 Nov 22 12:25:57 PM PST 23 Nov 22 12:43:39 PM PST 23 133069054254 ps
T786 /workspace/coverage/default/41.gpio_intr_rand_pgm.111226868612169275063491160021715981285314939094173816863482514032100285396265 Nov 22 12:28:17 PM PST 23 Nov 22 12:28:20 PM PST 23 119314289 ps
T787 /workspace/coverage/default/7.gpio_smoke.74923377595833975774895213999752140112394708711397623587231682158647808311834 Nov 22 12:26:17 PM PST 23 Nov 22 12:26:22 PM PST 23 112796484 ps
T788 /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.28705288921210423666621756358856262263732014010401646276547922800709080461724 Nov 22 12:25:38 PM PST 23 Nov 22 12:25:45 PM PST 23 134635595 ps
T789 /workspace/coverage/default/4.gpio_intr_rand_pgm.52007767162919050895319029763424913209554791944936755146682638638121953413921 Nov 22 12:26:17 PM PST 23 Nov 22 12:26:22 PM PST 23 119314289 ps
T790 /workspace/coverage/default/19.gpio_smoke.76001474886445122095872283881221311905833544383070273915282908322723706265742 Nov 22 12:26:20 PM PST 23 Nov 22 12:26:26 PM PST 23 112796484 ps
T791 /workspace/coverage/default/29.gpio_smoke.63632306851553030138814822574170741832084478410040476939401671697794952011943 Nov 22 12:27:51 PM PST 23 Nov 22 12:27:55 PM PST 23 112796484 ps
T792 /workspace/coverage/default/45.gpio_alert_test.18746220945873018617044328414856286437047634095866599282610214488613904567037 Nov 22 12:27:19 PM PST 23 Nov 22 12:27:26 PM PST 23 22440064 ps
T793 /workspace/coverage/default/3.gpio_rand_intr_trigger.27630917687525253001274542245938872028080940331898138157785642994388390176456 Nov 22 12:22:09 PM PST 23 Nov 22 12:22:13 PM PST 23 228920555 ps
T794 /workspace/coverage/default/33.gpio_alert_test.10341606183645119741798904727997523553493471165228953061242845695653864056171 Nov 22 12:23:45 PM PST 23 Nov 22 12:23:47 PM PST 23 22440064 ps
T795 /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.92407197670282551812756043757774673556267178351043754305632519393931638152685 Nov 22 12:26:20 PM PST 23 Nov 22 12:44:11 PM PST 23 133069054254 ps
T796 /workspace/coverage/default/8.gpio_smoke.84993912837912324996417060646874141743863917515918425318829935733678002243669 Nov 22 12:26:31 PM PST 23 Nov 22 12:26:34 PM PST 23 112796484 ps
T797 /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.76946931391720620367994725881321359944010625987049573177981355256968628495333 Nov 22 12:23:19 PM PST 23 Nov 22 12:23:20 PM PST 23 112796484 ps
T798 /workspace/coverage/default/25.gpio_alert_test.4841362604015595142051975840622890818777163480070686668078973065643800741255 Nov 22 12:26:57 PM PST 23 Nov 22 12:27:03 PM PST 23 22440064 ps
T799 /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.16655708844685683287093165361711376741259701628757137510237841017031579110118 Nov 22 12:23:07 PM PST 23 Nov 22 12:41:19 PM PST 23 133069054254 ps
T800 /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.18428568881781584069956759825724146621652112172695117712295920112431091811007 Nov 22 12:26:58 PM PST 23 Nov 22 12:27:09 PM PST 23 572864232 ps
T801 /workspace/coverage/default/2.gpio_rand_intr_trigger.61577142719803993619380677340319361392173266198339422719935827777451527998453 Nov 22 12:26:55 PM PST 23 Nov 22 12:27:03 PM PST 23 228920555 ps
T802 /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.99877770588142914094894421434310822300773763164648829267708594320719047396976 Nov 22 12:26:17 PM PST 23 Nov 22 12:26:22 PM PST 23 57921923 ps
T803 /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.95689114867951602522767138837088201558169253601084267017394062926788381658638 Nov 22 12:27:17 PM PST 23 Nov 22 12:45:19 PM PST 23 133069054254 ps
T804 /workspace/coverage/default/49.gpio_filter_stress.32848622701875800877553649957573635461678404126519430355114777747924461364527 Nov 22 12:26:13 PM PST 23 Nov 22 12:26:38 PM PST 23 1135699015 ps
T805 /workspace/coverage/default/1.gpio_random_dout_din.58654876011387290360420964687680241705295002910352144785782864549099565368131 Nov 22 12:27:17 PM PST 23 Nov 22 12:27:24 PM PST 23 81278879 ps
T73 /workspace/coverage/default/4.gpio_sec_cm.54619791556748974523808851673669144620720896927010424992625936827076918588823 Nov 22 12:21:44 PM PST 23 Nov 22 12:21:46 PM PST 23 134885593 ps
T806 /workspace/coverage/default/43.gpio_smoke.48384306901983091062784230565492136680517332437414659918339947965348792661326 Nov 22 12:27:00 PM PST 23 Nov 22 12:27:09 PM PST 23 112796484 ps
T807 /workspace/coverage/default/47.gpio_rand_intr_trigger.63296142253996766567799977095492693705119571036024249048859658582487900875407 Nov 22 12:24:39 PM PST 23 Nov 22 12:24:43 PM PST 23 228920555 ps
T808 /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.21889844032806622414269047025751575031029458938608691266517190936229110192891 Nov 22 12:26:59 PM PST 23 Nov 22 12:27:09 PM PST 23 134635595 ps
T809 /workspace/coverage/default/23.gpio_stress_all.68740420574563047795700968016506808286568494651636960106474618046339468560471 Nov 22 12:26:16 PM PST 23 Nov 22 12:28:48 PM PST 23 21104521406 ps
T810 /workspace/coverage/default/11.gpio_filter_stress.14778788360450907125681179359911629394132765920166737382151720896776154143293 Nov 22 12:26:55 PM PST 23 Nov 22 12:27:21 PM PST 23 1135699015 ps
T811 /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.45090438079294175059169668306749294458716425886846260619571847216106089241038 Nov 22 12:26:16 PM PST 23 Nov 22 12:26:20 PM PST 23 57921923 ps
T812 /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.96673396558441476280367258841708496707965177079679106298201300706898492201275 Nov 22 12:26:55 PM PST 23 Nov 22 12:45:20 PM PST 23 133069054254 ps
T813 /workspace/coverage/default/19.gpio_rand_intr_trigger.10393850205412903923121798478328229939448324670181819040230762419909992478268 Nov 22 12:21:39 PM PST 23 Nov 22 12:21:42 PM PST 23 228920555 ps
T814 /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.100292811982112754906926870899800752318281253158621144132707138460611553199134 Nov 22 12:26:16 PM PST 23 Nov 22 12:26:22 PM PST 23 112796484 ps
T815 /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.32546657689790367523319488589490146402348954657164413220038136888966233371514 Nov 22 12:26:58 PM PST 23 Nov 22 12:27:08 PM PST 23 134635595 ps
T816 /workspace/coverage/default/25.gpio_intr_rand_pgm.75949436917025007037624223283475378153564049419880139270282691955315679119388 Nov 22 12:26:02 PM PST 23 Nov 22 12:26:05 PM PST 23 119314289 ps
T817 /workspace/coverage/default/22.gpio_full_random.90046748296000438224246446135105476312672802144682195250688124490245307294387 Nov 22 12:26:57 PM PST 23 Nov 22 12:27:05 PM PST 23 137439144 ps
T818 /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.27313843206813793231927670370332223649244643293421465943139468656535580885184 Nov 22 12:27:42 PM PST 23 Nov 22 12:27:52 PM PST 23 134635595 ps
T819 /workspace/coverage/default/37.gpio_stress_all.29933103223813148822665778745314895916283125411472577473131474522530986134141 Nov 22 12:27:31 PM PST 23 Nov 22 12:30:28 PM PST 23 21104521406 ps
T820 /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.75036540835602179028034628740118167646941457217666337139517885525324991106815 Nov 22 12:26:16 PM PST 23 Nov 22 12:26:23 PM PST 23 134635595 ps
T821 /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.66005736856850227563211034157212543841875806217059013910985002485740355605928 Nov 22 12:21:06 PM PST 23 Nov 22 12:21:12 PM PST 23 572864232 ps
T822 /workspace/coverage/default/4.gpio_full_random.82554245653820496809311206638433934346849966310027040709786136381840709966983 Nov 22 12:23:40 PM PST 23 Nov 22 12:23:42 PM PST 23 137439144 ps
T823 /workspace/coverage/default/5.gpio_full_random.113521465009251586861417785897146185853263016748695448630504343905160721227433 Nov 22 12:27:38 PM PST 23 Nov 22 12:27:49 PM PST 23 137439144 ps
T824 /workspace/coverage/default/49.gpio_intr_rand_pgm.6328408482119347684712237218146930494159472357001249688750053377546944020141 Nov 22 12:26:29 PM PST 23 Nov 22 12:26:32 PM PST 23 119314289 ps
T825 /workspace/coverage/default/49.gpio_rand_intr_trigger.75677461944222565864091096359006588974338161303497906545268467842414029928733 Nov 22 12:26:13 PM PST 23 Nov 22 12:26:19 PM PST 23 228920555 ps
T826 /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.75919208927281852253212712553644427048937986522034109973693377713508614847277 Nov 22 12:25:01 PM PST 23 Nov 22 12:42:57 PM PST 23 133069054254 ps
T827 /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.5791429681955219252362441669533313558990016631927586286921187837120068072111 Nov 22 12:26:04 PM PST 23 Nov 22 12:26:09 PM PST 23 134635595 ps
T828 /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.5712667026245975515078064118918355745623078307840346576514001898105255245754 Nov 22 12:26:16 PM PST 23 Nov 22 12:26:21 PM PST 23 57921923 ps
T829 /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.81983850056095179140338059386060090906815362540282521121939057258954856783994 Nov 22 12:23:47 PM PST 23 Nov 22 12:23:50 PM PST 23 81278879 ps
T830 /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1122769481111691211322574759106784084441298970221319894942670479438217200130 Nov 22 12:26:59 PM PST 23 Nov 22 12:45:21 PM PST 23 133069054254 ps
T831 /workspace/coverage/default/28.gpio_stress_all.38602457942625164883993279347531644914773930675979689118789494137343635197138 Nov 22 12:27:13 PM PST 23 Nov 22 12:30:08 PM PST 23 21104521406 ps
T832 /workspace/coverage/default/36.gpio_random_dout_din.97679915011517443944048497730961219225966780947150376919607791774866070776188 Nov 22 12:26:18 PM PST 23 Nov 22 12:26:25 PM PST 23 81278879 ps
T833 /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.66786388394795864210151950118014121098483185238518622992851041076101861213813 Nov 22 12:26:14 PM PST 23 Nov 22 12:26:22 PM PST 23 572864232 ps
T834 /workspace/coverage/default/21.gpio_random_dout_din.13107531306495044978198010379745121392994543492617073522792806169116488943223 Nov 22 12:26:20 PM PST 23 Nov 22 12:26:27 PM PST 23 81278879 ps
T835 /workspace/coverage/default/39.gpio_alert_test.60293792728401862980634478942429797899933621612972202175072998932114530986585 Nov 22 12:25:53 PM PST 23 Nov 22 12:25:55 PM PST 23 22440064 ps
T836 /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.51220722713682008571198716398808240584313573982222023975507806282644896144085 Nov 22 12:23:08 PM PST 23 Nov 22 12:23:09 PM PST 23 57921923 ps
T837 /workspace/coverage/default/48.gpio_alert_test.44524526201580545156454195726789349290643900036544043262387670168185295788849 Nov 22 12:27:06 PM PST 23 Nov 22 12:27:12 PM PST 23 22440064 ps
T838 /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.37296307805665090488355465970253389138096801120347479651895317715397583206500 Nov 22 12:26:16 PM PST 23 Nov 22 12:44:13 PM PST 23 133069054254 ps
T839 /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.114351907917459709498629090712665050774280783731765368509469358565372439003390 Nov 22 12:26:31 PM PST 23 Nov 22 12:26:34 PM PST 23 57921923 ps
T840 /workspace/coverage/default/43.gpio_rand_intr_trigger.88088455349519727954748565188517794662960223060963677972256483824767533651191 Nov 22 12:24:15 PM PST 23 Nov 22 12:24:19 PM PST 23 228920555 ps
T841 /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.46559754402899505607220980043434820861648841314418362774405988361955953938913 Nov 22 12:25:54 PM PST 23 Nov 22 12:26:00 PM PST 23 572864232 ps
T842 /workspace/coverage/default/35.gpio_smoke.85653733213593165890318777751952207091944225029816229090238520862524377992469 Nov 22 12:26:05 PM PST 23 Nov 22 12:26:08 PM PST 23 112796484 ps
T843 /workspace/coverage/default/42.gpio_intr_rand_pgm.75480380801084363507658237213671269535105320697164296211260290353605818628423 Nov 22 12:27:11 PM PST 23 Nov 22 12:27:19 PM PST 23 119314289 ps
T844 /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.98083526256873665128047767147456944109586839334384390789064188831901320963257 Nov 22 12:26:16 PM PST 23 Nov 22 12:26:22 PM PST 23 134635595 ps
T845 /workspace/coverage/default/5.gpio_intr_rand_pgm.100589662604426873576311860155948240345939753347317818666980259954446922284018 Nov 22 12:22:19 PM PST 23 Nov 22 12:22:21 PM PST 23 119314289 ps
T846 /workspace/coverage/default/15.gpio_full_random.33129277415147058751377996903310222998609581538285435249441035598496235365958 Nov 22 12:23:45 PM PST 23 Nov 22 12:23:47 PM PST 23 137439144 ps
T847 /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.70414034932677186710236785919863132263283047868657978439251289226804123949455 Nov 22 12:26:11 PM PST 23 Nov 22 12:26:13 PM PST 23 112796484 ps
T848 /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.34408878871081792019096559529622834830848737540430280460512149324758036132199 Nov 22 12:26:58 PM PST 23 Nov 22 12:44:44 PM PST 23 133069054254 ps
T849 /workspace/coverage/default/39.gpio_filter_stress.30676484401190075686306385393073746203333119499146140225072117804728065480761 Nov 22 12:26:59 PM PST 23 Nov 22 12:27:28 PM PST 23 1135699015 ps
T850 /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.59593215504049358427055113703445790912276071269925878579420669651896499506913 Nov 22 12:26:07 PM PST 23 Nov 22 12:26:09 PM PST 23 81278879 ps
T851 /workspace/coverage/default/16.gpio_random_dout_din.193699745768491410223505347136628924483857486653239921189138057530579079396 Nov 22 12:23:53 PM PST 23 Nov 22 12:23:57 PM PST 23 81278879 ps
T852 /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.45609634705998978801249557942700222241274329748214984493703703531710508521593 Nov 22 12:26:03 PM PST 23 Nov 22 12:26:05 PM PST 23 57921923 ps
T853 /workspace/coverage/default/14.gpio_stress_all.49018258949461678272464863657841462568885535524045183383765727848587713169465 Nov 22 12:27:12 PM PST 23 Nov 22 12:29:59 PM PST 23 21104521406 ps
T854 /workspace/coverage/default/2.gpio_alert_test.39223447563512580340816534905777815692796136773002207953305719145638295148946 Nov 22 12:25:14 PM PST 23 Nov 22 12:25:15 PM PST 23 22440064 ps
T855 /workspace/coverage/default/14.gpio_full_random.33831287320346441545549569755573668638787007360280530233731289120868125143951 Nov 22 12:27:09 PM PST 23 Nov 22 12:27:17 PM PST 23 137439144 ps
T856 /workspace/coverage/default/11.gpio_smoke.26780662672031165990116835961438973281333130135090993948323422554369878823908 Nov 22 12:26:14 PM PST 23 Nov 22 12:26:18 PM PST 23 112796484 ps
T857 /workspace/coverage/default/15.gpio_stress_all.39698330627161746982962300578277441387583386852650549290260847938633394769202 Nov 22 12:26:15 PM PST 23 Nov 22 12:29:09 PM PST 23 21104521406 ps
T858 /workspace/coverage/default/44.gpio_full_random.5280557881476868915107029105938577225027842113709127796392905141796425987026 Nov 22 12:27:07 PM PST 23 Nov 22 12:27:14 PM PST 23 137439144 ps
T859 /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2810819446212246065648957424045994403685520577034960391803140917313705367682 Nov 22 12:26:21 PM PST 23 Nov 22 12:26:27 PM PST 23 81278879 ps
T860 /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.36783670612804880003367947458005548628478810168179562299876241918288421440441 Nov 22 12:24:11 PM PST 23 Nov 22 12:24:15 PM PST 23 134635595 ps
T861 /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.11749058357758823216710919961995990282199576460340709956861082802692529134834 Nov 22 12:26:19 PM PST 23 Nov 22 12:26:25 PM PST 23 57921923 ps
T862 /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.15915300998962403171117537555464233715291012969395319239486477032495001096680 Nov 22 12:26:50 PM PST 23 Nov 22 12:26:57 PM PST 23 572864232 ps
T863 /workspace/coverage/default/9.gpio_alert_test.112604924977526340862266828057549895215160461355121111448805511107937819539515 Nov 22 12:26:53 PM PST 23 Nov 22 12:26:56 PM PST 23 22440064 ps
T864 /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.54894473094473694016953514917919229509840743181512412923232265908293611097313 Nov 22 12:27:10 PM PST 23 Nov 22 12:27:18 PM PST 23 112796484 ps
T865 /workspace/coverage/default/46.gpio_random_dout_din.41282637524225886506016840660417344013936374317265740093541810512214257686399 Nov 22 12:26:21 PM PST 23 Nov 22 12:26:27 PM PST 23 81278879 ps
T866 /workspace/coverage/default/48.gpio_rand_intr_trigger.17366582896773710957912573227443522340993627973056772029846698384030690922297 Nov 22 12:25:57 PM PST 23 Nov 22 12:26:01 PM PST 23 228920555 ps
T867 /workspace/coverage/default/26.gpio_alert_test.9703484526413987218678835177161872603582445588643986501067400758893575621688 Nov 22 12:27:18 PM PST 23 Nov 22 12:27:26 PM PST 23 22440064 ps
T868 /workspace/coverage/default/9.gpio_smoke.30506584732041952681865665158287124502768241459919242292074824810008094707507 Nov 22 12:25:35 PM PST 23 Nov 22 12:25:43 PM PST 23 112796484 ps
T869 /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.48998028397271930991339306278178054992799212739563701779828682878392406199407 Nov 22 12:26:27 PM PST 23 Nov 22 12:45:36 PM PST 23 133069054254 ps
T870 /workspace/coverage/default/41.gpio_stress_all.85864546999889511070251709633746737367829856781419284012368114635118210779419 Nov 22 12:27:18 PM PST 23 Nov 22 12:30:01 PM PST 23 21104521406 ps
T871 /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.28785179868781588313599835507950165380375781352315671078914257678701730300407 Nov 22 12:25:31 PM PST 23 Nov 22 12:25:35 PM PST 23 134635595 ps
T872 /workspace/coverage/default/34.gpio_alert_test.60245028943469793259351674839699094011544830448428933959286548224653550193496 Nov 22 12:26:19 PM PST 23 Nov 22 12:26:24 PM PST 23 22440064 ps
T873 /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.50161398105040031641423956016344739259819542000579678973566890569197445242503 Nov 22 12:26:20 PM PST 23 Nov 22 12:26:26 PM PST 23 57921923 ps
T874 /workspace/coverage/default/18.gpio_rand_intr_trigger.67803903057358056979916867693889791571305413026082152070447310081265498181077 Nov 22 12:26:21 PM PST 23 Nov 22 12:26:29 PM PST 23 228920555 ps
T875 /workspace/coverage/default/20.gpio_random_dout_din.20263548278692227087846963063223764071431752332138291675476739239780951445362 Nov 22 12:22:42 PM PST 23 Nov 22 12:22:44 PM PST 23 81278879 ps
T876 /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4706126850914130268525411077606851226981971605768359149840062052454846900128 Nov 22 12:26:19 PM PST 23 Nov 22 12:26:25 PM PST 23 112796484 ps
T877 /workspace/coverage/default/15.gpio_alert_test.86781818956447787840116500451709663742728627285006923897126479783506105470570 Nov 22 12:22:14 PM PST 23 Nov 22 12:22:15 PM PST 23 22440064 ps
T50 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.33251088982915637804205864341451863070795186995502740051084840409038563561912 Nov 22 01:18:15 PM PST 23 Nov 22 01:18:21 PM PST 23 49261278 ps
T878 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.75276256206188415952469507431079390420510165310724767035711951193904435728387 Nov 22 01:18:22 PM PST 23 Nov 22 01:18:28 PM PST 23 185438760 ps
T879 /workspace/coverage/cover_reg_top/0.gpio_intr_test.64092474641135263845113720685786722159761538197001521780890999258943383704819 Nov 22 01:17:48 PM PST 23 Nov 22 01:17:50 PM PST 23 25975750 ps
T880 /workspace/coverage/cover_reg_top/23.gpio_intr_test.109493622198021727078581152748167211079470088712992413509960207660600243240599 Nov 22 01:18:41 PM PST 23 Nov 22 01:18:43 PM PST 23 25975750 ps
T881 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.36402151191810293491981736683738479006242313836851996696435300781342619940399 Nov 22 01:18:23 PM PST 23 Nov 22 01:18:28 PM PST 23 22993631 ps
T51 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.76640421503829361486978064166457564234908859784270240337173317677967842246631 Nov 22 01:18:08 PM PST 23 Nov 22 01:18:14 PM PST 23 49261278 ps
T882 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.88272488551429883439208100911688409469421337668049580491153043302386679527411 Nov 22 01:18:34 PM PST 23 Nov 22 01:18:37 PM PST 23 49261278 ps
T883 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.34684410377619113717323096557997432436171952479733431867820481183627991074865 Nov 22 01:18:11 PM PST 23 Nov 22 01:18:16 PM PST 23 50029129 ps
T884 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.26707989782076575748183197753862786373572740651829261355879204083881370184586 Nov 22 01:18:03 PM PST 23 Nov 22 01:18:10 PM PST 23 22993631 ps
T885 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.92560110109591223974696916617113748981103893289683141855656500247268948567209 Nov 22 01:18:02 PM PST 23 Nov 22 01:18:12 PM PST 23 245206139 ps
T886 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.47233713815604966782411608555874941665714614952808465825060629225223653079736 Nov 22 01:18:18 PM PST 23 Nov 22 01:18:26 PM PST 23 245206139 ps
T887 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.12084218027220354769382755440346769978108309430221401345735587524295849980255 Nov 22 01:18:23 PM PST 23 Nov 22 01:18:28 PM PST 23 185438760 ps
T888 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.108872295244789734797230019892349865738227517469463313950861615734065417584150 Nov 22 01:18:14 PM PST 23 Nov 22 01:18:19 PM PST 23 31279279 ps
T889 /workspace/coverage/cover_reg_top/4.gpio_intr_test.560413400658189483986615460982037302879468258467422696639979297773349533302 Nov 22 01:18:01 PM PST 23 Nov 22 01:18:10 PM PST 23 25975750 ps
T890 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.68835012894643591078988314520902421316159844505441022604110124307203791658701 Nov 22 01:18:21 PM PST 23 Nov 22 01:18:26 PM PST 23 50029129 ps
T891 /workspace/coverage/cover_reg_top/33.gpio_intr_test.89449882466110415288585746382355476860592579524221514843640304222513867166729 Nov 22 01:18:19 PM PST 23 Nov 22 01:18:24 PM PST 23 25975750 ps
T892 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.53446626226372127849571512196995468372143254763794155405491521653574488978983 Nov 22 01:19:21 PM PST 23 Nov 22 01:19:25 PM PST 23 245206139 ps
T893 /workspace/coverage/cover_reg_top/34.gpio_intr_test.100618485463909662573852605758181504578002182189298902593561729650216983870750 Nov 22 01:18:12 PM PST 23 Nov 22 01:18:17 PM PST 23 25975750 ps
T894 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.85683464186960243399696559322691556258823440200518491278022340185108071114424 Nov 22 01:18:18 PM PST 23 Nov 22 01:18:24 PM PST 23 50029129 ps
T895 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.68940419914454916008333765901246901647709679866325626487699028935609482015406 Nov 22 01:18:31 PM PST 23 Nov 22 01:18:36 PM PST 23 245206139 ps
T896 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.67477351200073687161448295714334650299377855671896070050930402761425360622452 Nov 22 01:18:08 PM PST 23 Nov 22 01:18:14 PM PST 23 49261278 ps
T897 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.29326438633061110122171642595770912273150614122340300653867355505607655341458 Nov 22 01:19:12 PM PST 23 Nov 22 01:19:14 PM PST 23 49261278 ps
T898 /workspace/coverage/cover_reg_top/3.gpio_intr_test.82233272564006468441885414659092526397601381124656924728941563542435256346236 Nov 22 01:17:57 PM PST 23 Nov 22 01:18:04 PM PST 23 25975750 ps
T899 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.13876061807237218586882864882426204512573118018409259452021437332689497493293 Nov 22 01:18:07 PM PST 23 Nov 22 01:18:13 PM PST 23 49261278 ps
T900 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.48896488610069398684137003424789721283092030291354075656963121101240725963356 Nov 22 01:18:55 PM PST 23 Nov 22 01:18:59 PM PST 23 185438760 ps
T901 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.93485436624225817686521828150580316041858347852545302520269348527695925709899 Nov 22 01:18:08 PM PST 23 Nov 22 01:18:16 PM PST 23 245206139 ps
T902 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.8917071093913628271017561271237513196678954753947392195447737920473170156513 Nov 22 01:17:58 PM PST 23 Nov 22 01:18:07 PM PST 23 31279279 ps
T903 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.104100185984658586908991746860399253476346284404218285472419386099218395294608 Nov 22 01:18:10 PM PST 23 Nov 22 01:18:16 PM PST 23 50029129 ps
T904 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.201041586636183577361341113615699064726504340603596173336955054292969746674 Nov 22 01:18:06 PM PST 23 Nov 22 01:18:14 PM PST 23 245206139 ps
T905 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.87209067684351981960096462894302801842794963918326567504092816151462530763698 Nov 22 01:18:13 PM PST 23 Nov 22 01:18:19 PM PST 23 49261278 ps
T906 /workspace/coverage/cover_reg_top/22.gpio_intr_test.90127980654702958477000660880915024769646453854094069772363386016662824168060 Nov 22 01:18:13 PM PST 23 Nov 22 01:18:18 PM PST 23 25975750 ps
T907 /workspace/coverage/cover_reg_top/43.gpio_intr_test.11002311620428886789332173355108744222958459985780255368496894171362348187717 Nov 22 01:18:14 PM PST 23 Nov 22 01:18:19 PM PST 23 25975750 ps
T908 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.87470829646830571543923160822005108256186615353087489262002413494513237456224 Nov 22 01:18:28 PM PST 23 Nov 22 01:18:31 PM PST 23 185438760 ps
T909 /workspace/coverage/cover_reg_top/44.gpio_intr_test.34966029666910754916116931086133267190672545598589284584106646396200284191626 Nov 22 01:18:56 PM PST 23 Nov 22 01:18:59 PM PST 23 25975750 ps
T910 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2491289109359788093092490482772215869787847222158650060151509381457527657482 Nov 22 01:18:55 PM PST 23 Nov 22 01:18:58 PM PST 23 22993631 ps
T911 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.92696532765015729245517383818526280958783887467062391049260159509743488377055 Nov 22 01:18:03 PM PST 23 Nov 22 01:18:10 PM PST 23 22993631 ps
T912 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.72477983991373277539583202385756932095305107672953502607848713109839157196037 Nov 22 01:18:29 PM PST 23 Nov 22 01:18:31 PM PST 23 49261278 ps
T913 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.114757018874030676144856880866297063127220981552946158771018034898496680042433 Nov 22 01:18:47 PM PST 23 Nov 22 01:18:50 PM PST 23 22993631 ps
T914 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.111063693409889967228048191360185804415133346806166101065809502792317009215959 Nov 22 01:18:04 PM PST 23 Nov 22 01:18:14 PM PST 23 245206139 ps
T915 /workspace/coverage/cover_reg_top/25.gpio_intr_test.36124020505346918565645818188206953488622709635436349546224779973255038052728 Nov 22 01:18:22 PM PST 23 Nov 22 01:18:27 PM PST 23 25975750 ps
T916 /workspace/coverage/cover_reg_top/17.gpio_intr_test.80441124211077956856415688359816938567921698599371210823913827822707473087818 Nov 22 01:18:18 PM PST 23 Nov 22 01:18:23 PM PST 23 25975750 ps
T917 /workspace/coverage/cover_reg_top/29.gpio_intr_test.33453753392085617019599727683346774930380751206667754577774829942382537523642 Nov 22 01:18:23 PM PST 23 Nov 22 01:18:27 PM PST 23 25975750 ps
T918 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.110724368469703572833950288530233288090549230907824152656241926258438489267788 Nov 22 01:18:03 PM PST 23 Nov 22 01:18:11 PM PST 23 49261278 ps
T919 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.114922667303401665473631621601183378379982072259134202369328773743171284151626 Nov 22 01:18:20 PM PST 23 Nov 22 01:18:25 PM PST 23 50029129 ps
T920 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.68207715665200931936305351108451371948610037786092210481043233205502762597727 Nov 22 01:18:35 PM PST 23 Nov 22 01:18:38 PM PST 23 49261278 ps
T921 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.68061547759129211743099349580103509344586679805158940285413805098371288580426 Nov 22 01:18:13 PM PST 23 Nov 22 01:18:20 PM PST 23 245206139 ps
T922 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.73609098600040550593773420715174191580411206321334708060444490365436101103385 Nov 22 01:18:14 PM PST 23 Nov 22 01:18:20 PM PST 23 185438760 ps
T923 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1534762672288734876511042246784212726614728620152322360030677501494310705973 Nov 22 01:18:14 PM PST 23 Nov 22 01:18:19 PM PST 23 25975750 ps
T924 /workspace/coverage/cover_reg_top/19.gpio_intr_test.37190795347389602798612334669326659267318759508454723918151964864672559741350 Nov 22 01:18:23 PM PST 23 Nov 22 01:18:28 PM PST 23 25975750 ps
T925 /workspace/coverage/cover_reg_top/35.gpio_intr_test.81394582110292590825636657812029019160903266649848881145212009362926815918453 Nov 22 01:18:35 PM PST 23 Nov 22 01:18:38 PM PST 23 25975750 ps
T926 /workspace/coverage/cover_reg_top/21.gpio_intr_test.5028066229636035801023894032873034418891377899881217056754893970161651552575 Nov 22 01:18:16 PM PST 23 Nov 22 01:18:21 PM PST 23 25975750 ps
T927 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.27644641735612863836635233807677616390602739321231049648023320495992959251489 Nov 22 01:18:48 PM PST 23 Nov 22 01:18:51 PM PST 23 185438760 ps
T928 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.90630183856452693330959974528456663031872097038852323091806166728540240589469 Nov 22 01:18:30 PM PST 23 Nov 22 01:18:34 PM PST 23 245206139 ps
T929 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.16415518999594970234373716422058474694362309268565712983197613892715538149173 Nov 22 01:18:21 PM PST 23 Nov 22 01:18:27 PM PST 23 185438760 ps
T930 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.41823155597862686934124206383913881555857263900765991885576255095013271243432 Nov 22 01:18:02 PM PST 23 Nov 22 01:18:11 PM PST 23 185438760 ps
T931 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.81861151432198544253448880700834292001587010812028244720013122035092136616111 Nov 22 01:18:02 PM PST 23 Nov 22 01:18:12 PM PST 23 245206139 ps
T932 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.47785533838842013439471179712260422469710666550104090089852894292835538092127 Nov 22 01:18:04 PM PST 23 Nov 22 01:18:11 PM PST 23 22993631 ps
T933 /workspace/coverage/cover_reg_top/7.gpio_intr_test.92978958189464721098324565953875151941494239958630674095385841048984709511154 Nov 22 01:18:08 PM PST 23 Nov 22 01:18:13 PM PST 23 25975750 ps
T934 /workspace/coverage/cover_reg_top/30.gpio_intr_test.13568389399872159825141359978307119530471927763253934396968059972166836514844 Nov 22 01:18:22 PM PST 23 Nov 22 01:18:27 PM PST 23 25975750 ps
T935 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.91261954345315317495006245522586553621832632235866156030458165169678820697946 Nov 22 01:18:37 PM PST 23 Nov 22 01:18:41 PM PST 23 185438760 ps
T936 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.99237925739108410345899316232432219334843358857801704927856799675705806459452 Nov 22 01:18:17 PM PST 23 Nov 22 01:18:22 PM PST 23 50029129 ps
T937 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.111482737233924145255955685749522625774111801172819488556900583281074183429463 Nov 22 01:18:14 PM PST 23 Nov 22 01:18:22 PM PST 23 245206139 ps
T938 /workspace/coverage/cover_reg_top/45.gpio_intr_test.10268665969521407379731258723793919741327152125138435614133472883075583072721 Nov 22 01:18:11 PM PST 23 Nov 22 01:18:16 PM PST 23 25975750 ps
T939 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.65451603498202441582609771802121037809233082619368499241406528144707682973192 Nov 22 01:18:03 PM PST 23 Nov 22 01:18:11 PM PST 23 50029129 ps
T940 /workspace/coverage/cover_reg_top/18.gpio_intr_test.66252276547656647515139694674903374862910937383824574970803289508299093992782 Nov 22 01:18:23 PM PST 23 Nov 22 01:18:27 PM PST 23 25975750 ps
T941 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.41281102386068129715023462961088542555529081245616450234015999036733992147487 Nov 22 01:18:16 PM PST 23 Nov 22 01:18:22 PM PST 23 22993631 ps
T942 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.61420289539506934764024790998909365383197800501735693705134797266639008558531 Nov 22 01:18:08 PM PST 23 Nov 22 01:18:13 PM PST 23 22993631 ps
T943 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.17241189222842149304790116811646785334314938695091781814028370477081028304700 Nov 22 01:18:02 PM PST 23 Nov 22 01:18:10 PM PST 23 53171961 ps
T944 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.67159030906994377034808469893186434213153285533200942591614820065540139632361 Nov 22 01:18:42 PM PST 23 Nov 22 01:18:45 PM PST 23 185438760 ps
T945 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.65280988100153424313592828040155678604340565758152544354435290809548546659161 Nov 22 01:18:09 PM PST 23 Nov 22 01:18:14 PM PST 23 50029129 ps
T946 /workspace/coverage/cover_reg_top/31.gpio_intr_test.7868553199465029508827813106245940748414006749128464039280675929805185939214 Nov 22 01:18:13 PM PST 23 Nov 22 01:18:18 PM PST 23 25975750 ps
T947 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.53580396930750881516246679950559514717388783275829355647177018111870904382472 Nov 22 01:18:15 PM PST 23 Nov 22 01:18:22 PM PST 23 185438760 ps
T948 /workspace/coverage/cover_reg_top/42.gpio_intr_test.61710452528925180856611535600336362073264094612078089593420424568251478551186 Nov 22 01:18:56 PM PST 23 Nov 22 01:18:59 PM PST 23 25975750 ps
T949 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.44166694474623214166752223497700760386591417942511602639156323740979352186917 Nov 22 01:18:04 PM PST 23 Nov 22 01:18:12 PM PST 23 31279279 ps
T950 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.28484129065790696529090135755021079472620907108830458775106963898669361187155 Nov 22 01:17:45 PM PST 23 Nov 22 01:17:47 PM PST 23 50029129 ps
T951 /workspace/coverage/cover_reg_top/15.gpio_intr_test.64675764111662994903495469915468552328978553168156000497113359708650339372684 Nov 22 01:18:17 PM PST 23 Nov 22 01:18:22 PM PST 23 25975750 ps
T952 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.20784942268488124360861056937093404417950462126555738028467751253441729403958 Nov 22 01:18:29 PM PST 23 Nov 22 01:18:34 PM PST 23 245206139 ps
T953 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.20207755198189582496053967683236931787591959907041284535186497774197303346528 Nov 22 01:18:22 PM PST 23 Nov 22 01:18:29 PM PST 23 245206139 ps
T954 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.62862329359149405536913130903511175089828131868635006355313407049489026510935 Nov 22 01:18:22 PM PST 23 Nov 22 01:18:27 PM PST 23 50029129 ps
T955 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.20794694459219050233598288108580044641261904055918356075659965773964563723331 Nov 22 01:17:46 PM PST 23 Nov 22 01:17:51 PM PST 23 245206139 ps
T956 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.64281374813162787019331638589399484448211177539463957553120912671760911406799 Nov 22 01:18:19 PM PST 23 Nov 22 01:18:25 PM PST 23 50029129 ps
T957 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.34707676877350368764393718657724682500701108889575918444929529019671176934358 Nov 22 01:18:13 PM PST 23 Nov 22 01:18:18 PM PST 23 22993631 ps
T958 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.108670564086907254513150510765673797951364023837048464054183777425740172957845 Nov 22 01:18:06 PM PST 23 Nov 22 01:18:12 PM PST 23 49261278 ps
T959 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.81712656726838373937346711527135668830751330023619144179113307060823422406095 Nov 22 01:19:05 PM PST 23 Nov 22 01:19:10 PM PST 23 50029129 ps
T960 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.9011629406619780093934120356459330147075242052684213542548162106094338245186 Nov 22 01:18:12 PM PST 23 Nov 22 01:18:19 PM PST 23 446472386 ps
T961 /workspace/coverage/cover_reg_top/40.gpio_intr_test.62228742193922751165111329227074600581627034730314883829020914190082118280906 Nov 22 01:18:17 PM PST 23 Nov 22 01:18:23 PM PST 23 25975750 ps
T962 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.102156189664650554104785152067115734496487653567069223753448969726276766247929 Nov 22 01:18:02 PM PST 23 Nov 22 01:18:10 PM PST 23 53171961 ps
T963 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.91334084040634217383344736025638565637412673609476242486913320899213832325258 Nov 22 01:18:14 PM PST 23 Nov 22 01:18:19 PM PST 23 50029129 ps
T964 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.62802145894812527655917231961279311066207254821396318804009029268877469625580 Nov 22 01:18:00 PM PST 23 Nov 22 01:18:11 PM PST 23 245206139 ps
T965 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.15126991845927391786217915830051349437523057126321091304252101619259897318598 Nov 22 01:18:12 PM PST 23 Nov 22 01:18:18 PM PST 23 53171961 ps
T966 /workspace/coverage/cover_reg_top/49.gpio_intr_test.31877881796580141012787047143794602203231746417520625579225737662593785331591 Nov 22 01:18:23 PM PST 23 Nov 22 01:18:28 PM PST 23 25975750 ps
T967 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.62607989209248657498289173843427539094981791159155462054895334795591975167373 Nov 22 01:18:18 PM PST 23 Nov 22 01:18:24 PM PST 23 22993631 ps
T968 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.75282784759386985609567586526652552269727118344636204896480013945708524809103 Nov 22 01:18:29 PM PST 23 Nov 22 01:18:32 PM PST 23 22993631 ps
T969 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.47408313062372146920071392584083588790354718355496090322934849090159456875582 Nov 22 01:18:04 PM PST 23 Nov 22 01:18:11 PM PST 23 49261278 ps
T970 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.102317473318954069014985036144580435301620499666903864197285629760668472573510 Nov 22 01:18:21 PM PST 23 Nov 22 01:18:26 PM PST 23 22993631 ps

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.39566067884702814576423011857798314767067941114795894240327690327010958170059
Short name T4
Test name
Test status
Simulation time 185438760 ps
CPU time 1.33 seconds
Started Nov 22 01:18:09 PM PST 23
Finished Nov 22 01:18:15 PM PST 23
Peak memory 198320 kb
Host smart-43b3fe55-f9b2-41b2-9143-784597e52c33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395660678847028145764230118577983147670679411147958942403276
90327010958170059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_intg_err.395660678847028145764230118577983147670679411147958942403
27690327010958170059
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.57269981641312543599672068419546555117334687406723883391895179732551652837806
Short name T70
Test name
Test status
Simulation time 115064323 ps
CPU time 1.39 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:33 PM PST 23
Peak memory 194128 kb
Host smart-7ded643a-db17-4c3b-ba0b-886e20f005d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=57269981641312543599672068419546555117334687406723883391895179732551652837806 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 1.gpio_smoke_en_cdc_prim.57269981641312543599672068419546555117334687406723883391895179732551652837806
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/2.gpio_full_random.7110937024551673678596946845055436630471643242944373530241841740977726720524
Short name T57
Test name
Test status
Simulation time 137439144 ps
CPU time 1.01 seconds
Started Nov 22 12:26:44 PM PST 23
Finished Nov 22 12:26:47 PM PST 23
Peak memory 196308 kb
Host smart-de93bbd8-1478-4907-8c37-d215ecd28106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7110937024551673678596946845055436630471643242944373530241841740977726720524 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.7110937024551673678596946845055436630471643242944373530241841740977726720524
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.72934566832440551331737852780325194895676143114109020352209792175173155916372
Short name T335
Test name
Test status
Simulation time 134635595 ps
CPU time 2.73 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 196828 kb
Host smart-e91bb426-410c-45f9-bcb9-c57502f60798
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72934566832440551331737852780325194895676143114109020352209792175173
155916372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.72934566832440551331737
852780325194895676143114109020352209792175173155916372
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.76805528582515378296495994228160243568911794433906929362657776602794873761489
Short name T3
Test name
Test status
Simulation time 245206139 ps
CPU time 2.72 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 198432 kb
Host smart-4dfab0fc-c692-479c-a8f3-3b6910e2e854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76805528582515378296495994228160243568911794433906929362657776602794873761489 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.76805528582515378296495994228160243568911794433906929362657776602794873761489
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.89125426040697458956484381379837125212512059293058643856978601115505991460356
Short name T16
Test name
Test status
Simulation time 133069054254 ps
CPU time 1065.52 seconds
Started Nov 22 12:27:43 PM PST 23
Finished Nov 22 12:45:35 PM PST 23
Peak memory 197924 kb
Host smart-d70df972-191f-4f1a-abad-06b23223e4fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=89125426040697458956484381379837125212512059293058643856978601115505991460356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_wit
h_rand_reset.89125426040697458956484381379837125212512059293058643856978601115505991460356
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.65795479963847893379532322515863427252566999329321841728724054620295232573293
Short name T8
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:23 PM PST 23
Peak memory 193992 kb
Host smart-d901d643-84e0-41fe-9658-b5cc714978dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65795479963847893379532322515863427252566999329321841728724054620295232573293 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.65795479963847893379532322515863427252566999329321841728724054620295232573293
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.5382879842183441304584430619922918623976400383908532812033962391467207373815
Short name T63
Test name
Test status
Simulation time 57921923 ps
CPU time 0.8 seconds
Started Nov 22 12:27:05 PM PST 23
Finished Nov 22 12:27:13 PM PST 23
Peak memory 195924 kb
Host smart-015bfc1d-1952-47e8-bc90-18ba0fe0bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5382879842183441304584430619922918623976400383908532812033962391467207373815 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.gpio_dout_din_regs_random_rw.5382879842183441304584430619922918623976400383908532812033962391467207373815
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.54515680924648903722416133733486375660826521216779352675504303542828588620128
Short name T7
Test name
Test status
Simulation time 53171961 ps
CPU time 0.82 seconds
Started Nov 22 01:17:46 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 196164 kb
Host smart-1fe9daed-b26f-4f92-a1f6-f33861e41dae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545156809246489037224161337334863756608265212167793526755043035
42828588620128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_aliasing.54515680924648903722416133733486375660826521216779352675504
303542828588620128
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.95813683882245906950809227784764899683953049435314096155638347621762722495891
Short name T52
Test name
Test status
Simulation time 134885593 ps
CPU time 1 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 213688 kb
Host smart-e10c9b44-f09e-4caf-889c-a7e2354ac6d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95813683882245906950809227784764899683953049435314096155638347621762722495891 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.gpio_sec_cm.95813683882245906950809227784764899683953049435314096155638347621762722495891
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.12836049901095722173724274533890550792186704049535602355798982961458704377865
Short name T46
Test name
Test status
Simulation time 49261278 ps
CPU time 0.83 seconds
Started Nov 22 01:17:45 PM PST 23
Finished Nov 22 01:17:47 PM PST 23
Peak memory 196476 kb
Host smart-137a27ce-77d6-4512-a4e9-9efae369104a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128360499010957221737242745338905507921867040495356
02355798982961458704377865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_same_csr_outstanding.128360499010957221737242745338905507921
86704049535602355798982961458704377865
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.gpio_alert_test.8479120976908212081449415967718181736151158749030870742452247686455920452080
Short name T60
Test name
Test status
Simulation time 22440064 ps
CPU time 0.54 seconds
Started Nov 22 12:26:14 PM PST 23
Finished Nov 22 12:26:18 PM PST 23
Peak memory 193756 kb
Host smart-29f411aa-2d54-40a1-aed1-6ae9ed99d080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8479120976908212081449415967718181736151158749030870742452247686455920452080 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.gpio_alert_test.8479120976908212081449415967718181736151158749030870742452247686455920452080
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.23090576925746960619511888042501834164231081869668544001318710597436795668326
Short name T80
Test name
Test status
Simulation time 572864232 ps
CPU time 5.25 seconds
Started Nov 22 12:20:53 PM PST 23
Finished Nov 22 12:20:59 PM PST 23
Peak memory 197708 kb
Host smart-124ad17c-666a-4d7f-8150-94f0547a586e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090576925746960619511888042501834164231081869668544001318710597436795668326 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_long_reg_writes_reg_reads.2309057692574696061951188804250183416423108186966
8544001318710597436795668326
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.29370268367579361866411985063833669799791348912707931720106924915415547793729
Short name T31
Test name
Test status
Simulation time 446472386 ps
CPU time 3.2 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 197060 kb
Host smart-c2b884d3-4f28-47db-b471-8d607679b196
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29370268367579361866411985063833669799791348912707931720106924915415547793729 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.29370268367579361866411985063833669799791348912707931720106924915415547793729
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.8917071093913628271017561271237513196678954753947392195447737920473170156513
Short name T902
Test name
Test status
Simulation time 31279279 ps
CPU time 0.68 seconds
Started Nov 22 01:17:58 PM PST 23
Finished Nov 22 01:18:07 PM PST 23
Peak memory 194904 kb
Host smart-b85dfcb3-4c28-41f1-90d2-b1e77562ab89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8917071093913628271017561271237513196678954753947392195447737920473170156513 -assert nopos
tproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.8917071093913628271017561271237513196678954753947392195447737920473170156513
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.12952298152438233707405481660187396380703790057491909487400571917825865705045
Short name T106
Test name
Test status
Simulation time 50029129 ps
CPU time 0.91 seconds
Started Nov 22 01:17:48 PM PST 23
Finished Nov 22 01:17:50 PM PST 23
Peak memory 198264 kb
Host smart-59981461-a5a0-486e-a252-5effc28f38c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295229815243823
3707405481660187396380703790057491909487400571917825865705045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_rese
t.12952298152438233707405481660187396380703790057491909487400571917825865705045
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2491289109359788093092490482772215869787847222158650060151509381457527657482
Short name T910
Test name
Test status
Simulation time 22993631 ps
CPU time 0.8 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:18:58 PM PST 23
Peak memory 192532 kb
Host smart-d3b66216-58da-46a8-9494-e268a2b782a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249128910935978809309249048277221586978784722215865006015150938145752
7657482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_rw.2491289109359788093092490482772215869787847222158650060151509381457527657482
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.64092474641135263845113720685786722159761538197001521780890999258943383704819
Short name T879
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:17:48 PM PST 23
Finished Nov 22 01:17:50 PM PST 23
Peak memory 194100 kb
Host smart-e2f338ac-a0b4-474f-a024-b16bfb5debe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64092474641135263845113720685786722159761538197001521780890999258943383704819 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.64092474641135263845113720685786722159761538197001521780890999258943383704819
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.62802145894812527655917231961279311066207254821396318804009029268877469625580
Short name T964
Test name
Test status
Simulation time 245206139 ps
CPU time 2.94 seconds
Started Nov 22 01:18:00 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 198396 kb
Host smart-afbe471f-55c8-4e88-90d9-2feb4f3c9a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62802145894812527655917231961279311066207254821396318804009029268877469625580 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.62802145894812527655917231961279311066207254821396318804009029268877469625580
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.91261954345315317495006245522586553621832632235866156030458165169678820697946
Short name T935
Test name
Test status
Simulation time 185438760 ps
CPU time 1.38 seconds
Started Nov 22 01:18:37 PM PST 23
Finished Nov 22 01:18:41 PM PST 23
Peak memory 198308 kb
Host smart-cff22612-2d87-4275-9ef1-29e78acd64f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912619543453153174950062455225865536218326322358661560304581
65169678820697946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_intg_err.912619543453153174950062455225865536218326322358661560304
58165169678820697946
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.15074087159143482649486264750348239922295510249942898362503444619719224807948
Short name T9
Test name
Test status
Simulation time 53171961 ps
CPU time 0.83 seconds
Started Nov 22 01:17:46 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 196192 kb
Host smart-a3044528-7a52-4cb9-905f-c5ba1414999a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150740871591434826494862647503482399222955102499428983625034446
19719224807948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_aliasing.15074087159143482649486264750348239922295510249942898362503
444619719224807948
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.9011629406619780093934120356459330147075242052684213542548162106094338245186
Short name T960
Test name
Test status
Simulation time 446472386 ps
CPU time 3.24 seconds
Started Nov 22 01:18:12 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 197088 kb
Host smart-46f5c1fc-7bee-460f-9735-99be2d3e0fe8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9011629406619780093934120356459330147075242052684213542548162106094338245186 -assert nopos
tproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.9011629406619780093934120356459330147075242052684213542548162106094338245186
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.44166694474623214166752223497700760386591417942511602639156323740979352186917
Short name T949
Test name
Test status
Simulation time 31279279 ps
CPU time 0.68 seconds
Started Nov 22 01:18:04 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 195004 kb
Host smart-d7d5236b-3259-4b05-ad89-d9d19d25f29c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44166694474623214166752223497700760386591417942511602639156323740979352186917 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.44166694474623214166752223497700760386591417942511602639156323740979352186917
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.28484129065790696529090135755021079472620907108830458775106963898669361187155
Short name T950
Test name
Test status
Simulation time 50029129 ps
CPU time 0.92 seconds
Started Nov 22 01:17:45 PM PST 23
Finished Nov 22 01:17:47 PM PST 23
Peak memory 198292 kb
Host smart-9e315fe8-64bd-48f3-bc39-25d1648ebaa8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848412906579069
6529090135755021079472620907108830458775106963898669361187155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_rese
t.28484129065790696529090135755021079472620907108830458775106963898669361187155
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.49703750773329454333645513016650830865031396772264689576940623777768593049463
Short name T102
Test name
Test status
Simulation time 22993631 ps
CPU time 0.62 seconds
Started Nov 22 01:17:57 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 194792 kb
Host smart-f785ba76-932e-4c8d-a210-f81e1e297579
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497037507733294543336455130166508308650313967722646895769406237777685
93049463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_rw.49703750773329454333645513016650830865031396772264689576940623777768593049463
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.95693563300967639744811453087695906368121555928857191825111611930374856310444
Short name T101
Test name
Test status
Simulation time 25975750 ps
CPU time 0.89 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:18:58 PM PST 23
Peak memory 191720 kb
Host smart-40235230-2846-465f-bb94-f7cf46e91dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95693563300967639744811453087695906368121555928857191825111611930374856310444 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.95693563300967639744811453087695906368121555928857191825111611930374856310444
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.68207715665200931936305351108451371948610037786092210481043233205502762597727
Short name T920
Test name
Test status
Simulation time 49261278 ps
CPU time 0.81 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 196416 kb
Host smart-e27c6fcf-18fe-4773-a4b0-70f694fef033
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682077156652009319363053511084513719486100377860922
10481043233205502762597727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_same_csr_outstanding.682077156652009319363053511084513719486
10037786092210481043233205502762597727
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.20794694459219050233598288108580044641261904055918356075659965773964563723331
Short name T955
Test name
Test status
Simulation time 245206139 ps
CPU time 2.83 seconds
Started Nov 22 01:17:46 PM PST 23
Finished Nov 22 01:17:51 PM PST 23
Peak memory 198424 kb
Host smart-0c7fa505-4f46-4d0f-85d9-3260a353ab5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20794694459219050233598288108580044641261904055918356075659965773964563723331 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.20794694459219050233598288108580044641261904055918356075659965773964563723331
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2997954337446069475102446353464187843754240162217471292641069965573191490983
Short name T24
Test name
Test status
Simulation time 185438760 ps
CPU time 1.61 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 196080 kb
Host smart-a0ef19da-a066-4b4f-9427-a88044bd1d97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299795433744606947510244635346418784375424016221747129264106
9965573191490983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_intg_err.2997954337446069475102446353464187843754240162217471292641
069965573191490983
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.85683464186960243399696559322691556258823440200518491278022340185108071114424
Short name T894
Test name
Test status
Simulation time 50029129 ps
CPU time 0.98 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 198164 kb
Host smart-4e9e3a06-fef0-47f0-9f37-82d05fafd1a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8568346418696024
3399696559322691556258823440200518491278022340185108071114424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_res
et.85683464186960243399696559322691556258823440200518491278022340185108071114424
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.114757018874030676144856880866297063127220981552946158771018034898496680042433
Short name T913
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:18:47 PM PST 23
Finished Nov 22 01:18:50 PM PST 23
Peak memory 194804 kb
Host smart-7b3fd587-6dd9-47eb-a3c7-80538fcd3843
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114757018874030676144856880866297063127220981552946158771018034898496
680042433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_rw.114757018874030676144856880866297063127220981552946158771018034898496680042433
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.24333553868771429970021829811669071385304344691400501954599265922944941289720
Short name T47
Test name
Test status
Simulation time 49261278 ps
CPU time 0.84 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 196240 kb
Host smart-80e5d977-812f-4387-9b01-f34e170081a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243335538687714299700218298116690713853043446914005
01954599265922944941289720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_same_csr_outstanding.24333553868771429970021829811669071385
304344691400501954599265922944941289720
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.111063693409889967228048191360185804415133346806166101065809502792317009215959
Short name T914
Test name
Test status
Simulation time 245206139 ps
CPU time 2.88 seconds
Started Nov 22 01:18:04 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 198464 kb
Host smart-12d2c104-c82f-4b25-9df2-a88303285a61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111063693409889967228048191360185804415133346806166101065809502792317009215959 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.111063693409889967228048191360185804415133346806166101065809502792317009215959
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.67159030906994377034808469893186434213153285533200942591614820065540139632361
Short name T944
Test name
Test status
Simulation time 185438760 ps
CPU time 1.39 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:18:45 PM PST 23
Peak memory 198468 kb
Host smart-ec8c469d-6d25-494c-ae19-aca5feaca93c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671590309069943770348084698931864342131532855332009425916148
20065540139632361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_intg_err.67159030906994377034808469893186434213153285533200942591
614820065540139632361
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.65280988100153424313592828040155678604340565758152544354435290809548546659161
Short name T945
Test name
Test status
Simulation time 50029129 ps
CPU time 0.85 seconds
Started Nov 22 01:18:09 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 198196 kb
Host smart-c40b739d-f953-4330-877a-ff09637cc7ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6528098810015342
4313592828040155678604340565758152544354435290809548546659161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_res
et.65280988100153424313592828040155678604340565758152544354435290809548546659161
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.102317473318954069014985036144580435301620499666903864197285629760668472573510
Short name T970
Test name
Test status
Simulation time 22993631 ps
CPU time 0.58 seconds
Started Nov 22 01:18:21 PM PST 23
Finished Nov 22 01:18:26 PM PST 23
Peak memory 194748 kb
Host smart-80d78851-9eb6-4fc4-99f4-090a0426b0a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102317473318954069014985036144580435301620499666903864197285629760668
472573510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_rw.102317473318954069014985036144580435301620499666903864197285629760668472573510
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.41708269349705232641365466629029785195124616579380197637107863806833855832927
Short name T88
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 193812 kb
Host smart-2291a390-845f-4892-a0d7-bcfc828d1f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708269349705232641365466629029785195124616579380197637107863806833855832927 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.41708269349705232641365466629029785195124616579380197637107863806833855832927
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.108670564086907254513150510765673797951364023837048464054183777425740172957845
Short name T958
Test name
Test status
Simulation time 49261278 ps
CPU time 0.79 seconds
Started Nov 22 01:18:06 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 196456 kb
Host smart-e946cf8d-9e9b-4875-8fd0-54d1b197e9ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108670564086907254513150510765673797951364023837048
464054183777425740172957845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_same_csr_outstanding.1086705640869072545131505107656737979
51364023837048464054183777425740172957845
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.20207755198189582496053967683236931787591959907041284535186497774197303346528
Short name T953
Test name
Test status
Simulation time 245206139 ps
CPU time 2.78 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:29 PM PST 23
Peak memory 198420 kb
Host smart-1528cf46-c591-4d77-a414-1b7f03d331a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20207755198189582496053967683236931787591959907041284535186497774197303346528 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.20207755198189582496053967683236931787591959907041284535186497774197303346528
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.12084218027220354769382755440346769978108309430221401345735587524295849980255
Short name T887
Test name
Test status
Simulation time 185438760 ps
CPU time 1.4 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 198360 kb
Host smart-34b1ec3d-93f5-4190-bdca-dc0f54eb4485
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120842180272203547693827554403467699781083094302214013457355
87524295849980255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_intg_err.12084218027220354769382755440346769978108309430221401345
735587524295849980255
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3512656771108827442455364934655386614392403042683949256073808366366015710899
Short name T95
Test name
Test status
Simulation time 50029129 ps
CPU time 0.87 seconds
Started Nov 22 01:19:11 PM PST 23
Finished Nov 22 01:19:14 PM PST 23
Peak memory 198104 kb
Host smart-0799b884-3472-47e4-892f-aa40ac63debe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512656771108827
442455364934655386614392403042683949256073808366366015710899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_rese
t.3512656771108827442455364934655386614392403042683949256073808366366015710899
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.8733899990750816313059610659808794813533433597136101622294285142076280460571
Short name T104
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 194716 kb
Host smart-3b7c3c69-30ef-4f5e-ae0b-4a995d7b2808
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873389999075081631305961065980879481353343359713610162229428514207628
0460571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_rw.8733899990750816313059610659808794813533433597136101622294285142076280460571
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.60218069307437891662659519587700340340190551295562260933733456840896338095485
Short name T43
Test name
Test status
Simulation time 25975750 ps
CPU time 0.59 seconds
Started Nov 22 01:18:28 PM PST 23
Finished Nov 22 01:18:30 PM PST 23
Peak memory 193980 kb
Host smart-f01361af-d23e-4c6b-aecf-bbdabd5f206c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60218069307437891662659519587700340340190551295562260933733456840896338095485 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.60218069307437891662659519587700340340190551295562260933733456840896338095485
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.42275936073238850250673408496161237077794914732400821743263673317606443475563
Short name T42
Test name
Test status
Simulation time 49261278 ps
CPU time 0.79 seconds
Started Nov 22 01:19:12 PM PST 23
Finished Nov 22 01:19:15 PM PST 23
Peak memory 196340 kb
Host smart-2d15acd7-5969-4497-9b41-1890705d162d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422759360732388502506734084961612370777949147324008
21743263673317606443475563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_same_csr_outstanding.42275936073238850250673408496161237077
794914732400821743263673317606443475563
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.53446626226372127849571512196995468372143254763794155405491521653574488978983
Short name T892
Test name
Test status
Simulation time 245206139 ps
CPU time 2.64 seconds
Started Nov 22 01:19:21 PM PST 23
Finished Nov 22 01:19:25 PM PST 23
Peak memory 198276 kb
Host smart-2d83033a-c6f4-48ff-8f28-050d79380308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53446626226372127849571512196995468372143254763794155405491521653574488978983 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.53446626226372127849571512196995468372143254763794155405491521653574488978983
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.72488697895715995529141295508626759842644253993026567290563016357627229303574
Short name T5
Test name
Test status
Simulation time 185438760 ps
CPU time 1.34 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 198460 kb
Host smart-9bca413a-babe-434d-b585-a0fcec3e925c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724886978957159955291412955086267598426442539930265672905630
16357627229303574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_intg_err.72488697895715995529141295508626759842644253993026567290
563016357627229303574
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.64281374813162787019331638589399484448211177539463957553120912671760911406799
Short name T956
Test name
Test status
Simulation time 50029129 ps
CPU time 0.91 seconds
Started Nov 22 01:18:19 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 198292 kb
Host smart-54def52e-27fb-4eeb-88c6-5265710e0156
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6428137481316278
7019331638589399484448211177539463957553120912671760911406799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_res
et.64281374813162787019331638589399484448211177539463957553120912671760911406799
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.62607989209248657498289173843427539094981791159155462054895334795591975167373
Short name T967
Test name
Test status
Simulation time 22993631 ps
CPU time 0.62 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 194604 kb
Host smart-a15b7f06-8393-4708-b2a2-ca31b5f3c451
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626079892092486574982891738434275390949817911591554620548953347955919
75167373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_rw.62607989209248657498289173843427539094981791159155462054895334795591975167373
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.30171714665512826332104260142995160848006326838273895350256954216625374608480
Short name T44
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:54 PM PST 23
Finished Nov 22 01:18:56 PM PST 23
Peak memory 194044 kb
Host smart-07cd031b-a077-4d6b-ac7c-e709fb1448ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30171714665512826332104260142995160848006326838273895350256954216625374608480 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.30171714665512826332104260142995160848006326838273895350256954216625374608480
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.29326438633061110122171642595770912273150614122340300653867355505607655341458
Short name T897
Test name
Test status
Simulation time 49261278 ps
CPU time 0.8 seconds
Started Nov 22 01:19:12 PM PST 23
Finished Nov 22 01:19:14 PM PST 23
Peak memory 196340 kb
Host smart-27a55f98-fd92-4fcc-be0a-35da7ba695cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293264386330611101221716425957709122731506141223403
00653867355505607655341458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_same_csr_outstanding.29326438633061110122171642595770912273
150614122340300653867355505607655341458
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.90630183856452693330959974528456663031872097038852323091806166728540240589469
Short name T928
Test name
Test status
Simulation time 245206139 ps
CPU time 2.71 seconds
Started Nov 22 01:18:30 PM PST 23
Finished Nov 22 01:18:34 PM PST 23
Peak memory 198324 kb
Host smart-9238ca5b-e041-43e0-83ca-8877387dc7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90630183856452693330959974528456663031872097038852323091806166728540240589469 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.90630183856452693330959974528456663031872097038852323091806166728540240589469
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.84669964927822724165838656514292975097463256798187368085520541327398334805343
Short name T22
Test name
Test status
Simulation time 185438760 ps
CPU time 1.34 seconds
Started Nov 22 01:18:29 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 198228 kb
Host smart-b10c10c5-d110-417c-9f57-f5ae991b4b07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846699649278227241658386565142929750974632567981873680855205
41327398334805343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_intg_err.84669964927822724165838656514292975097463256798187368085
520541327398334805343
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.81712656726838373937346711527135668830751330023619144179113307060823422406095
Short name T959
Test name
Test status
Simulation time 50029129 ps
CPU time 0.93 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:10 PM PST 23
Peak memory 198224 kb
Host smart-0f5f666b-4f85-4c43-a66f-02f6a073f33b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8171265672683837
3937346711527135668830751330023619144179113307060823422406095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_res
et.81712656726838373937346711527135668830751330023619144179113307060823422406095
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.60248540667988457915987797295420017027788466788113590823798481992179182701961
Short name T109
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:18:17 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 194748 kb
Host smart-1e5e54ea-0ff0-49e9-a370-3f46e9ac051d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602485406679884579159877972954200170277884667881135908237984819921791
82701961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_rw.60248540667988457915987797295420017027788466788113590823798481992179182701961
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.35915193319602729726014359079487310261585189873382859303935419605888484456312
Short name T26
Test name
Test status
Simulation time 25975750 ps
CPU time 0.59 seconds
Started Nov 22 01:18:16 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 194112 kb
Host smart-b721533a-1d1d-4ffe-975b-2b4944a5cd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35915193319602729726014359079487310261585189873382859303935419605888484456312 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.35915193319602729726014359079487310261585189873382859303935419605888484456312
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.58904739087610827752847769190267406907287004217474625634347739013529788686810
Short name T45
Test name
Test status
Simulation time 49261278 ps
CPU time 0.82 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:18:58 PM PST 23
Peak memory 196528 kb
Host smart-27111a6b-38c2-4aef-be76-4a4439e3ac05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589047390876108277528477691902674069072870042174746
25634347739013529788686810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_same_csr_outstanding.58904739087610827752847769190267406907
287004217474625634347739013529788686810
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.47233713815604966782411608555874941665714614952808465825060629225223653079736
Short name T886
Test name
Test status
Simulation time 245206139 ps
CPU time 2.84 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:26 PM PST 23
Peak memory 198392 kb
Host smart-986dbe2f-70e0-4fc5-a422-f37b3ed1522a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47233713815604966782411608555874941665714614952808465825060629225223653079736 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.47233713815604966782411608555874941665714614952808465825060629225223653079736
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.99962502684115210990576907050548332003635115053935877742456572569912875844159
Short name T97
Test name
Test status
Simulation time 185438760 ps
CPU time 1.4 seconds
Started Nov 22 01:19:07 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 198356 kb
Host smart-0fd95f77-2513-41c6-afe2-39bc2a3effd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999625026841152109905769070505483320036351150539358777424565
72569912875844159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_intg_err.99962502684115210990576907050548332003635115053935877742
456572569912875844159
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.99237925739108410345899316232432219334843358857801704927856799675705806459452
Short name T936
Test name
Test status
Simulation time 50029129 ps
CPU time 0.91 seconds
Started Nov 22 01:18:17 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 198288 kb
Host smart-3aa8e284-3893-4437-ac6d-a1fe76333d64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9923792573910841
0345899316232432219334843358857801704927856799675705806459452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_res
et.99237925739108410345899316232432219334843358857801704927856799675705806459452
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.41281102386068129715023462961088542555529081245616450234015999036733992147487
Short name T941
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:18:16 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 194672 kb
Host smart-6ae97201-dcf6-46b7-add9-46b0f6d35564
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412811023860681297150234629610885425555290812456164502340159990367339
92147487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_rw.41281102386068129715023462961088542555529081245616450234015999036733992147487
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.64675764111662994903495469915468552328978553168156000497113359708650339372684
Short name T951
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:17 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 194060 kb
Host smart-231a1587-df22-4c53-a40a-33bdef52a6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64675764111662994903495469915468552328978553168156000497113359708650339372684 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.64675764111662994903495469915468552328978553168156000497113359708650339372684
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.47566442038301952156845902375976107153332886386765842791704231843824399966335
Short name T48
Test name
Test status
Simulation time 49261278 ps
CPU time 0.79 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 196484 kb
Host smart-7ae5608d-18e6-473a-aefe-2bc0a2c4c062
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475664420383019521568459023759761071533328863867658
42791704231843824399966335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_same_csr_outstanding.47566442038301952156845902375976107153
332886386765842791704231843824399966335
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.20784942268488124360861056937093404417950462126555738028467751253441729403958
Short name T952
Test name
Test status
Simulation time 245206139 ps
CPU time 2.74 seconds
Started Nov 22 01:18:29 PM PST 23
Finished Nov 22 01:18:34 PM PST 23
Peak memory 198224 kb
Host smart-8b2a4afa-fad3-49fe-a3d0-015eb53f6f58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20784942268488124360861056937093404417950462126555738028467751253441729403958 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.20784942268488124360861056937093404417950462126555738028467751253441729403958
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.53580396930750881516246679950559514717388783275829355647177018111870904382472
Short name T947
Test name
Test status
Simulation time 185438760 ps
CPU time 1.38 seconds
Started Nov 22 01:18:15 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 198468 kb
Host smart-ec3eb62d-0464-43b6-8314-8a50daa759bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535803969307508815162466799505595147173887832758293556471770
18111870904382472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_intg_err.53580396930750881516246679950559514717388783275829355647
177018111870904382472
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.62862329359149405536913130903511175089828131868635006355313407049489026510935
Short name T954
Test name
Test status
Simulation time 50029129 ps
CPU time 0.88 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 198264 kb
Host smart-2ac158c5-89ae-45d0-b08c-866ac9fd9398
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6286232935914940
5536913130903511175089828131868635006355313407049489026510935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_res
et.62862329359149405536913130903511175089828131868635006355313407049489026510935
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.53416029293301134325434126282287127228829813240125089357299224555452702770579
Short name T33
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:18:30 PM PST 23
Finished Nov 22 01:18:33 PM PST 23
Peak memory 194668 kb
Host smart-ced3ae8b-93f5-4eab-a543-0ea7daee366f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534160292933011343254341262822871272288298132401250893572992245554527
02770579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_rw.53416029293301134325434126282287127228829813240125089357299224555452702770579
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.41321450397857362141636353915641430869596955265122163455169657790836619706028
Short name T12
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:30 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 193580 kb
Host smart-656525a2-7f59-4853-9729-1364c103b304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41321450397857362141636353915641430869596955265122163455169657790836619706028 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.41321450397857362141636353915641430869596955265122163455169657790836619706028
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.72477983991373277539583202385756932095305107672953502607848713109839157196037
Short name T912
Test name
Test status
Simulation time 49261278 ps
CPU time 0.79 seconds
Started Nov 22 01:18:29 PM PST 23
Finished Nov 22 01:18:31 PM PST 23
Peak memory 196392 kb
Host smart-52a45066-8536-4adb-929e-5fc6fff912cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724779839913732775395832023857569320953051076729535
02607848713109839157196037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_same_csr_outstanding.72477983991373277539583202385756932095
305107672953502607848713109839157196037
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.29216490960050415951205734269195385311354284188176638635810948214650717028405
Short name T20
Test name
Test status
Simulation time 245206139 ps
CPU time 3 seconds
Started Nov 22 01:18:30 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 197924 kb
Host smart-bd056a0a-0d76-44f9-b384-596b8724b0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29216490960050415951205734269195385311354284188176638635810948214650717028405 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.29216490960050415951205734269195385311354284188176638635810948214650717028405
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.87470829646830571543923160822005108256186615353087489262002413494513237456224
Short name T908
Test name
Test status
Simulation time 185438760 ps
CPU time 1.38 seconds
Started Nov 22 01:18:28 PM PST 23
Finished Nov 22 01:18:31 PM PST 23
Peak memory 198336 kb
Host smart-6a92c04f-ef86-42c4-9530-4ae4dccbd157
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874708296468305715439231608220051082561866153530874892620024
13494513237456224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_intg_err.87470829646830571543923160822005108256186615353087489262
002413494513237456224
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.114922667303401665473631621601183378379982072259134202369328773743171284151626
Short name T919
Test name
Test status
Simulation time 50029129 ps
CPU time 0.9 seconds
Started Nov 22 01:18:20 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 198300 kb
Host smart-d8fef43f-9221-4959-8e32-2e6777f5e74c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149226673034016
65473631621601183378379982072259134202369328773743171284151626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_re
set.114922667303401665473631621601183378379982072259134202369328773743171284151626
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.75282784759386985609567586526652552269727118344636204896480013945708524809103
Short name T968
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:18:29 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 194668 kb
Host smart-47f382f2-b90e-44bc-af54-cfd0019f639c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752827847593869856095675865266525522697271183446362048964800139457085
24809103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_rw.75282784759386985609567586526652552269727118344636204896480013945708524809103
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.80441124211077956856415688359816938567921698599371210823913827822707473087818
Short name T916
Test name
Test status
Simulation time 25975750 ps
CPU time 0.59 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:23 PM PST 23
Peak memory 193992 kb
Host smart-31e4d3ca-4245-459b-a106-2586f0a38534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80441124211077956856415688359816938567921698599371210823913827822707473087818 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.80441124211077956856415688359816938567921698599371210823913827822707473087818
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.88272488551429883439208100911688409469421337668049580491153043302386679527411
Short name T882
Test name
Test status
Simulation time 49261278 ps
CPU time 0.78 seconds
Started Nov 22 01:18:34 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 196484 kb
Host smart-e495cb78-4c29-44e9-b5fa-8880af3a995d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882724885514298834392081009116884094694213376680495
80491153043302386679527411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_same_csr_outstanding.88272488551429883439208100911688409469
421337668049580491153043302386679527411
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.81881992107105038700829421793339489928756875137696204663569609575795902342632
Short name T23
Test name
Test status
Simulation time 245206139 ps
CPU time 2.88 seconds
Started Nov 22 01:18:10 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 198456 kb
Host smart-c33a9eca-16dc-4892-812a-d9ba853c6990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81881992107105038700829421793339489928756875137696204663569609575795902342632 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.81881992107105038700829421793339489928756875137696204663569609575795902342632
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.17094388413293517602012325437810950598142213573807769630692870062792754073065
Short name T103
Test name
Test status
Simulation time 185438760 ps
CPU time 1.34 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 198192 kb
Host smart-7c38133d-cca6-4f84-8629-878a94d6bc6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170943884132935176020123254378109505981422135738077696306928
70062792754073065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_intg_err.17094388413293517602012325437810950598142213573807769630
692870062792754073065
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.87546146205410147403535333223708447358628975987846787856025848292523862699036
Short name T86
Test name
Test status
Simulation time 50029129 ps
CPU time 0.92 seconds
Started Nov 22 01:18:18 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 197912 kb
Host smart-2f94adee-99ff-4d09-8208-ae258350926f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8754614620541014
7403535333223708447358628975987846787856025848292523862699036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_res
et.87546146205410147403535333223708447358628975987846787856025848292523862699036
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.113219023792353174750767929436511672323456860991345234374468597511274484792849
Short name T105
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:18:41 PM PST 23
Finished Nov 22 01:18:43 PM PST 23
Peak memory 194812 kb
Host smart-e2785e38-2d30-4e24-9c31-5b4ddc2a5309
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113219023792353174750767929436511672323456860991345234374468597511274
484792849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_rw.113219023792353174750767929436511672323456860991345234374468597511274484792849
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.66252276547656647515139694674903374862910937383824574970803289508299093992782
Short name T940
Test name
Test status
Simulation time 25975750 ps
CPU time 0.59 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 194072 kb
Host smart-f16e26e0-2c9e-44db-a0f4-fcbb61210a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66252276547656647515139694674903374862910937383824574970803289508299093992782 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.66252276547656647515139694674903374862910937383824574970803289508299093992782
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.67477351200073687161448295714334650299377855671896070050930402761425360622452
Short name T896
Test name
Test status
Simulation time 49261278 ps
CPU time 0.81 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 196544 kb
Host smart-70488a05-b70e-4010-b6cd-4a0a8f836095
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674773512000736871614482957143346502993778556718960
70050930402761425360622452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_same_csr_outstanding.67477351200073687161448295714334650299
377855671896070050930402761425360622452
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.201041586636183577361341113615699064726504340603596173336955054292969746674
Short name T904
Test name
Test status
Simulation time 245206139 ps
CPU time 2.71 seconds
Started Nov 22 01:18:06 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 198368 kb
Host smart-a5a86426-f7f0-4af7-8c08-2296d3e63f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201041586636183577361341113615699064726504340603596173336955054292969746674 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.gpio_tl_errors.201041586636183577361341113615699064726504340603596173336955054292969746674
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.27644641735612863836635233807677616390602739321231049648023320495992959251489
Short name T927
Test name
Test status
Simulation time 185438760 ps
CPU time 1.36 seconds
Started Nov 22 01:18:48 PM PST 23
Finished Nov 22 01:18:51 PM PST 23
Peak memory 198372 kb
Host smart-a301ded3-21c5-4887-9899-7ff3bb11e1be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276446417356128638366352338076776163906027393212310496480233
20495992959251489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_intg_err.27644641735612863836635233807677616390602739321231049648
023320495992959251489
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.57975469118288157430217533916388501334012039933471542236823018096036735103077
Short name T10
Test name
Test status
Simulation time 50029129 ps
CPU time 0.9 seconds
Started Nov 22 01:18:09 PM PST 23
Finished Nov 22 01:18:15 PM PST 23
Peak memory 198292 kb
Host smart-c8f517e8-365e-4811-9cbd-27e041b88dce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5797546911828815
7430217533916388501334012039933471542236823018096036735103077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_res
et.57975469118288157430217533916388501334012039933471542236823018096036735103077
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.34707676877350368764393718657724682500701108889575918444929529019671176934358
Short name T957
Test name
Test status
Simulation time 22993631 ps
CPU time 0.63 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 194684 kb
Host smart-405b315f-9819-4529-aeaf-d112e8f81b43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347076768773503687643937186577246825007011088895759184449295290196711
76934358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_rw.34707676877350368764393718657724682500701108889575918444929529019671176934358
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.37190795347389602798612334669326659267318759508454723918151964864672559741350
Short name T924
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 194072 kb
Host smart-ab37f3e7-6a7a-4a4d-b857-1b0dc0714aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190795347389602798612334669326659267318759508454723918151964864672559741350 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.37190795347389602798612334669326659267318759508454723918151964864672559741350
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.114802110442898197887413847787842199304827297363449180449733045730686603538531
Short name T49
Test name
Test status
Simulation time 49261278 ps
CPU time 0.8 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 196476 kb
Host smart-824281c6-d1e5-4925-9979-cf5ed581c5e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114802110442898197887413847787842199304827297363449
180449733045730686603538531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_same_csr_outstanding.1148021104428981978874138477878421993
04827297363449180449733045730686603538531
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.83713207336193898571406483928353453838975535023286272250725967787427561036943
Short name T21
Test name
Test status
Simulation time 185438760 ps
CPU time 1.35 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 198360 kb
Host smart-d08049ad-8289-4884-ba44-2a46cbe400a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837132073361938985714064839283534538389755350232862722507259
67787427561036943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_intg_err.83713207336193898571406483928353453838975535023286272250
725967787427561036943
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.15126991845927391786217915830051349437523057126321091304252101619259897318598
Short name T965
Test name
Test status
Simulation time 53171961 ps
CPU time 0.91 seconds
Started Nov 22 01:18:12 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 196220 kb
Host smart-4f8ee3cc-8547-4f07-a604-06831037a712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151269918459273917862179158300513494375230571263210913042521016
19259897318598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_aliasing.15126991845927391786217915830051349437523057126321091304252
101619259897318598
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.29498256103649151328010029961538317279068103168523751946643028844390483013983
Short name T35
Test name
Test status
Simulation time 446472386 ps
CPU time 3.24 seconds
Started Nov 22 01:18:09 PM PST 23
Finished Nov 22 01:18:17 PM PST 23
Peak memory 197064 kb
Host smart-9666b854-14e9-4be8-af1f-f43511d4078a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498256103649151328010029961538317279068103168523751946643028844390483013983 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.29498256103649151328010029961538317279068103168523751946643028844390483013983
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.12667491046748459802569406844185661212342919107478387509185708341457207784056
Short name T55
Test name
Test status
Simulation time 31279279 ps
CPU time 0.65 seconds
Started Nov 22 01:18:04 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 195000 kb
Host smart-4250fbf2-8ac0-489a-bd16-5577f9635cea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12667491046748459802569406844185661212342919107478387509185708341457207784056 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.12667491046748459802569406844185661212342919107478387509185708341457207784056
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.104100185984658586908991746860399253476346284404218285472419386099218395294608
Short name T903
Test name
Test status
Simulation time 50029129 ps
CPU time 0.91 seconds
Started Nov 22 01:18:10 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 198260 kb
Host smart-6abd4980-d202-424a-9b24-127b0c29370c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041001859846585
86908991746860399253476346284404218285472419386099218395294608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_res
et.104100185984658586908991746860399253476346284404218285472419386099218395294608
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.61420289539506934764024790998909365383197800501735693705134797266639008558531
Short name T942
Test name
Test status
Simulation time 22993631 ps
CPU time 0.6 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 194764 kb
Host smart-c1f9b784-bdc2-45f1-b82e-81045aae0196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614202895395069347640247909989093653831978005017356937051347972666390
08558531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_rw.61420289539506934764024790998909365383197800501735693705134797266639008558531
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.89279704137000558578536260988724458548366331171796949966986750679728867838717
Short name T90
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:19:12 PM PST 23
Finished Nov 22 01:19:14 PM PST 23
Peak memory 193816 kb
Host smart-f2e9d1db-2f35-42d4-abdf-610bf894c65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89279704137000558578536260988724458548366331171796949966986750679728867838717 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.89279704137000558578536260988724458548366331171796949966986750679728867838717
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.76640421503829361486978064166457564234908859784270240337173317677967842246631
Short name T51
Test name
Test status
Simulation time 49261278 ps
CPU time 0.82 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 196196 kb
Host smart-823f2fb4-0117-4bc2-b486-162566411493
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766404215038293614869780641664575642349088597842702
40337173317677967842246631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_same_csr_outstanding.766404215038293614869780641664575642349
08859784270240337173317677967842246631
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.93485436624225817686521828150580316041858347852545302520269348527695925709899
Short name T901
Test name
Test status
Simulation time 245206139 ps
CPU time 3 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 198420 kb
Host smart-3ae4e575-1f83-4d60-a316-2db487a1bf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93485436624225817686521828150580316041858347852545302520269348527695925709899 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.93485436624225817686521828150580316041858347852545302520269348527695925709899
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.41823155597862686934124206383913881555857263900765991885576255095013271243432
Short name T930
Test name
Test status
Simulation time 185438760 ps
CPU time 1.46 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 198448 kb
Host smart-efc9c90f-3578-454c-915e-36f8efd94947
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418231555978626869341242063839138815558572639007659918855762
55095013271243432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_intg_err.418231555978626869341242063839138815558572639007659918855
76255095013271243432
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.100032145098208983876997078829935602205007628761695631537158110513356998842178
Short name T94
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 194080 kb
Host smart-9487b2ff-9108-4c29-a8f5-d4a7d0084c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100032145098208983876997078829935602205007628761695631537158110513356998842178 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.100032145098208983876997078829935602205007628761695631537158110513356998842178
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.5028066229636035801023894032873034418891377899881217056754893970161651552575
Short name T926
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:16 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 194124 kb
Host smart-a876ad00-0d7a-447f-ad25-caa554994022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5028066229636035801023894032873034418891377899881217056754893970161651552575 -assert nopostproc +UV
M_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 21.gpio_intr_test.5028066229636035801023894032873034418891377899881217056754893970161651552575
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.90127980654702958477000660880915024769646453854094069772363386016662824168060
Short name T906
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 194072 kb
Host smart-a5189ca4-4356-4fe3-b559-866ca68a0d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90127980654702958477000660880915024769646453854094069772363386016662824168060 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.90127980654702958477000660880915024769646453854094069772363386016662824168060
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.109493622198021727078581152748167211079470088712992413509960207660600243240599
Short name T880
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:41 PM PST 23
Finished Nov 22 01:18:43 PM PST 23
Peak memory 194004 kb
Host smart-fd375391-e128-42dd-9f77-b2c0ea127c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109493622198021727078581152748167211079470088712992413509960207660600243240599 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.109493622198021727078581152748167211079470088712992413509960207660600243240599
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.66608466040352295340320737106835030802412399086416189409533809075529127984299
Short name T84
Test name
Test status
Simulation time 25975750 ps
CPU time 0.66 seconds
Started Nov 22 01:18:17 PM PST 23
Finished Nov 22 01:18:23 PM PST 23
Peak memory 193800 kb
Host smart-514f33f7-3ccd-4695-adf7-8d007ed87855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66608466040352295340320737106835030802412399086416189409533809075529127984299 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.66608466040352295340320737106835030802412399086416189409533809075529127984299
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.36124020505346918565645818188206953488622709635436349546224779973255038052728
Short name T915
Test name
Test status
Simulation time 25975750 ps
CPU time 0.58 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 194072 kb
Host smart-88aa8c47-ae9f-4ad6-8860-5612b59f6b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124020505346918565645818188206953488622709635436349546224779973255038052728 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.36124020505346918565645818188206953488622709635436349546224779973255038052728
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.111193370585612189885943326457014815761961276403603195665665417166280847555723
Short name T110
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 194044 kb
Host smart-fa32d60a-2e53-4792-8a7b-8402cc8518e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111193370585612189885943326457014815761961276403603195665665417166280847555723 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.111193370585612189885943326457014815761961276403603195665665417166280847555723
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.62511548519835018132146129580275749775568483588876526176745204898316190465080
Short name T98
Test name
Test status
Simulation time 25975750 ps
CPU time 0.68 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 194064 kb
Host smart-91cc1a39-6c9e-4abc-835c-6a9c903a5285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62511548519835018132146129580275749775568483588876526176745204898316190465080 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.62511548519835018132146129580275749775568483588876526176745204898316190465080
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.81624597443192172042101447365160367519078719796041774661818936082131971865499
Short name T89
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:30 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 194068 kb
Host smart-1afdcf18-63d2-4f50-a1da-73d983e577dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81624597443192172042101447365160367519078719796041774661818936082131971865499 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.81624597443192172042101447365160367519078719796041774661818936082131971865499
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.33453753392085617019599727683346774930380751206667754577774829942382537523642
Short name T917
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 194072 kb
Host smart-435c2c8d-3537-48c1-9b13-f2bd528a26af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33453753392085617019599727683346774930380751206667754577774829942382537523642 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.33453753392085617019599727683346774930380751206667754577774829942382537523642
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.17241189222842149304790116811646785334314938695091781814028370477081028304700
Short name T943
Test name
Test status
Simulation time 53171961 ps
CPU time 0.81 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 196196 kb
Host smart-f8ef50fc-e941-4b91-9504-dbf511194ddb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172411892228421493047901168116467853343149386950917818140283704
77081028304700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_aliasing.17241189222842149304790116811646785334314938695091781814028
370477081028304700
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.92014245211573693997561165467962144646818184327298482745758431598908946912741
Short name T25
Test name
Test status
Simulation time 446472386 ps
CPU time 3.13 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 196956 kb
Host smart-3ac09ea7-0372-4fd3-98ad-dad31582f7fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92014245211573693997561165467962144646818184327298482745758431598908946912741 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.92014245211573693997561165467962144646818184327298482745758431598908946912741
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.108872295244789734797230019892349865738227517469463313950861615734065417584150
Short name T888
Test name
Test status
Simulation time 31279279 ps
CPU time 0.63 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 194856 kb
Host smart-f61a49e6-3b40-4475-9463-a58868e03eae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108872295244789734797230019892349865738227517469463313950861615734065417584150 -assert nop
ostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.108872295244789734797230019892349865738227517469463313950861615734065417584150
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.91334084040634217383344736025638565637412673609476242486913320899213832325258
Short name T963
Test name
Test status
Simulation time 50029129 ps
CPU time 0.92 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 198136 kb
Host smart-831cedbf-40ea-4d7f-9039-81c76ab0bbb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9133408404063421
7383344736025638565637412673609476242486913320899213832325258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_rese
t.91334084040634217383344736025638565637412673609476242486913320899213832325258
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.39736659259007540740550892008231076138267801265452110022370039729034376500010
Short name T100
Test name
Test status
Simulation time 22993631 ps
CPU time 0.61 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 194708 kb
Host smart-b98800f6-c7a2-48b3-ad04-4f7cd349b425
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397366592590075407405508920082310761382678012654521100223700397290343
76500010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_rw.39736659259007540740550892008231076138267801265452110022370039729034376500010
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.82233272564006468441885414659092526397601381124656924728941563542435256346236
Short name T898
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:17:57 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 194080 kb
Host smart-11e2becc-599a-49ec-8e49-ee98027f6da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82233272564006468441885414659092526397601381124656924728941563542435256346236 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.82233272564006468441885414659092526397601381124656924728941563542435256346236
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.25946116330847081411716928458652228319672975910636618361417279951452428040353
Short name T37
Test name
Test status
Simulation time 49261278 ps
CPU time 0.83 seconds
Started Nov 22 01:18:54 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 196468 kb
Host smart-49faf6be-f445-435e-892e-20590c011cba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259461163308470814117169284586522283196729759106366
18361417279951452428040353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_same_csr_outstanding.259461163308470814117169284586522283196
72975910636618361417279951452428040353
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.68061547759129211743099349580103509344586679805158940285413805098371288580426
Short name T921
Test name
Test status
Simulation time 245206139 ps
CPU time 2.71 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:20 PM PST 23
Peak memory 198300 kb
Host smart-4de65815-4acb-4526-a919-da8970f97b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68061547759129211743099349580103509344586679805158940285413805098371288580426 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.68061547759129211743099349580103509344586679805158940285413805098371288580426
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.13568389399872159825141359978307119530471927763253934396968059972166836514844
Short name T934
Test name
Test status
Simulation time 25975750 ps
CPU time 0.59 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 194072 kb
Host smart-edee81e4-9de2-4751-a4ad-4d17d0880eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568389399872159825141359978307119530471927763253934396968059972166836514844 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.13568389399872159825141359978307119530471927763253934396968059972166836514844
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.7868553199465029508827813106245940748414006749128464039280675929805185939214
Short name T946
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 193944 kb
Host smart-9ccc6c49-698d-4afd-b40c-163fc39a3829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7868553199465029508827813106245940748414006749128464039280675929805185939214 -assert nopostproc +UV
M_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 31.gpio_intr_test.7868553199465029508827813106245940748414006749128464039280675929805185939214
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.40573921382050726694587445144140170874192820665263280130241015372043825515264
Short name T91
Test name
Test status
Simulation time 25975750 ps
CPU time 0.64 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 194028 kb
Host smart-1af8c8c9-0b44-4141-880f-8c5de7e15d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40573921382050726694587445144140170874192820665263280130241015372043825515264 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.40573921382050726694587445144140170874192820665263280130241015372043825515264
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.89449882466110415288585746382355476860592579524221514843640304222513867166729
Short name T891
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:19 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 194124 kb
Host smart-74a43a10-9ff6-4611-8c9e-06536476896f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89449882466110415288585746382355476860592579524221514843640304222513867166729 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.89449882466110415288585746382355476860592579524221514843640304222513867166729
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.100618485463909662573852605758181504578002182189298902593561729650216983870750
Short name T893
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:12 PM PST 23
Finished Nov 22 01:18:17 PM PST 23
Peak memory 193992 kb
Host smart-11504ce1-b21a-499d-8ac5-2ca1112664b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100618485463909662573852605758181504578002182189298902593561729650216983870750 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.100618485463909662573852605758181504578002182189298902593561729650216983870750
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.81394582110292590825636657812029019160903266649848881145212009362926815918453
Short name T925
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 194024 kb
Host smart-218d4b23-fcbd-4f8e-ba7e-9a95f4517e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81394582110292590825636657812029019160903266649848881145212009362926815918453 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.81394582110292590825636657812029019160903266649848881145212009362926815918453
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.56913162224347118419493518392750441213981805132876365359932177633307300686992
Short name T108
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:10 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 194044 kb
Host smart-4c8d7901-8ca8-4cac-85bc-df02cea90960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56913162224347118419493518392750441213981805132876365359932177633307300686992 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.56913162224347118419493518392750441213981805132876365359932177633307300686992
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.27602374156270831793728427501611681514219894489646615662897488847429130405140
Short name T87
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 193980 kb
Host smart-6af294c5-9ad5-46cc-9532-b0a302312df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602374156270831793728427501611681514219894489646615662897488847429130405140 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.27602374156270831793728427501611681514219894489646615662897488847429130405140
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1336316602388517330235862614995868448950325295250045486904813408800651832651
Short name T92
Test name
Test status
Simulation time 25975750 ps
CPU time 0.58 seconds
Started Nov 22 01:18:21 PM PST 23
Finished Nov 22 01:18:26 PM PST 23
Peak memory 194072 kb
Host smart-2fc9aeaa-5083-48a6-902a-7be4b73a5ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336316602388517330235862614995868448950325295250045486904813408800651832651 -assert nopostproc +UV
M_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 38.gpio_intr_test.1336316602388517330235862614995868448950325295250045486904813408800651832651
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.112411159057300861787844209118218375563993493240543247273312824646371707885155
Short name T41
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 194044 kb
Host smart-ea65d921-dd4e-4a40-8c68-7cb438589b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112411159057300861787844209118218375563993493240543247273312824646371707885155 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.112411159057300861787844209118218375563993493240543247273312824646371707885155
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.102156189664650554104785152067115734496487653567069223753448969726276766247929
Short name T962
Test name
Test status
Simulation time 53171961 ps
CPU time 0.86 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 196148 kb
Host smart-84a9bd19-bb00-4e20-a9e6-1d7959c53487
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102156189664650554104785152067115734496487653567069223753448969
726276766247929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_aliasing.1021561896646505541047851520671157344964876535670692237534
48969726276766247929
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.82744898339920192468961907203875154326482510155192174208374327345218927250755
Short name T34
Test name
Test status
Simulation time 446472386 ps
CPU time 3.27 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 196828 kb
Host smart-ca0ef86b-ec23-4da3-867c-d8559ba842c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82744898339920192468961907203875154326482510155192174208374327345218927250755 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.82744898339920192468961907203875154326482510155192174208374327345218927250755
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.45596091907783339323449868415559899511693718708026110039231075028723301884748
Short name T36
Test name
Test status
Simulation time 31279279 ps
CPU time 0.65 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:17 PM PST 23
Peak memory 194988 kb
Host smart-8048738f-0967-400a-984f-43dba7ed10e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45596091907783339323449868415559899511693718708026110039231075028723301884748 -assert nopo
stproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.45596091907783339323449868415559899511693718708026110039231075028723301884748
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.65451603498202441582609771802121037809233082619368499241406528144707682973192
Short name T939
Test name
Test status
Simulation time 50029129 ps
CPU time 0.9 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 198260 kb
Host smart-d5381040-c8c4-4366-9a95-189ae1fb6ac8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6545160349820244
1582609771802121037809233082619368499241406528144707682973192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_rese
t.65451603498202441582609771802121037809233082619368499241406528144707682973192
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.36402151191810293491981736683738479006242313836851996696435300781342619940399
Short name T881
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 194796 kb
Host smart-38a7f6c3-6149-45cc-9517-1fd4dab0aa6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364021511918102934919817366837384790062423138368519966964353007813426
19940399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_rw.36402151191810293491981736683738479006242313836851996696435300781342619940399
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.560413400658189483986615460982037302879468258467422696639979297773349533302
Short name T889
Test name
Test status
Simulation time 25975750 ps
CPU time 0.64 seconds
Started Nov 22 01:18:01 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 194120 kb
Host smart-9dd5e3fc-eacd-4f3d-9bbd-8d631dc6681e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560413400658189483986615460982037302879468258467422696639979297773349533302 -assert nopostproc +UVM
_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.gpio_intr_test.560413400658189483986615460982037302879468258467422696639979297773349533302
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.33251088982915637804205864341451863070795186995502740051084840409038563561912
Short name T50
Test name
Test status
Simulation time 49261278 ps
CPU time 0.83 seconds
Started Nov 22 01:18:15 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 196520 kb
Host smart-39776acd-6001-4140-bd78-55117d7c4297
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332510889829156378042058643414518630707951869955027
40051084840409038563561912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_same_csr_outstanding.332510889829156378042058643414518630707
95186995502740051084840409038563561912
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.92560110109591223974696916617113748981103893289683141855656500247268948567209
Short name T885
Test name
Test status
Simulation time 245206139 ps
CPU time 2.79 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 198436 kb
Host smart-66517193-2f7f-44c5-9f79-18525cc0e2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92560110109591223974696916617113748981103893289683141855656500247268948567209 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.92560110109591223974696916617113748981103893289683141855656500247268948567209
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.16415518999594970234373716422058474694362309268565712983197613892715538149173
Short name T929
Test name
Test status
Simulation time 185438760 ps
CPU time 1.37 seconds
Started Nov 22 01:18:21 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 198192 kb
Host smart-07597624-4dda-4448-940f-f38c744760b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164155189995949702343737164220584746943623092685657129831976
13892715538149173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_intg_err.164155189995949702343737164220584746943623092685657129831
97613892715538149173
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.62228742193922751165111329227074600581627034730314883829020914190082118280906
Short name T961
Test name
Test status
Simulation time 25975750 ps
CPU time 0.66 seconds
Started Nov 22 01:18:17 PM PST 23
Finished Nov 22 01:18:23 PM PST 23
Peak memory 193796 kb
Host smart-2464f842-9989-45d7-9c6b-518c4c493f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62228742193922751165111329227074600581627034730314883829020914190082118280906 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.62228742193922751165111329227074600581627034730314883829020914190082118280906
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.64691144147691761583497067033039953355260729450699807941216235938144722342274
Short name T107
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 194028 kb
Host smart-7c0284f4-89d7-4c00-bdbb-cfda2669853c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64691144147691761583497067033039953355260729450699807941216235938144722342274 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.64691144147691761583497067033039953355260729450699807941216235938144722342274
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.61710452528925180856611535600336362073264094612078089593420424568251478551186
Short name T948
Test name
Test status
Simulation time 25975750 ps
CPU time 0.76 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 192072 kb
Host smart-3db948e7-fa03-4770-9ad6-c029d0975d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61710452528925180856611535600336362073264094612078089593420424568251478551186 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.61710452528925180856611535600336362073264094612078089593420424568251478551186
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.11002311620428886789332173355108744222958459985780255368496894171362348187717
Short name T907
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 194088 kb
Host smart-9c5cea79-0242-407b-95da-ed2a9c6680b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11002311620428886789332173355108744222958459985780255368496894171362348187717 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.11002311620428886789332173355108744222958459985780255368496894171362348187717
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.34966029666910754916116931086133267190672545598589284584106646396200284191626
Short name T909
Test name
Test status
Simulation time 25975750 ps
CPU time 0.73 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 192020 kb
Host smart-d5219205-871f-4688-9011-d0d1a6bb1da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34966029666910754916116931086133267190672545598589284584106646396200284191626 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.34966029666910754916116931086133267190672545598589284584106646396200284191626
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.10268665969521407379731258723793919741327152125138435614133472883075583072721
Short name T938
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 193988 kb
Host smart-b99a13ab-e88f-4be9-b9e9-bd31a7c91b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10268665969521407379731258723793919741327152125138435614133472883075583072721 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.10268665969521407379731258723793919741327152125138435614133472883075583072721
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.5217606072320831831356376058508258829801384628039790156142924476295120622129
Short name T38
Test name
Test status
Simulation time 25975750 ps
CPU time 0.63 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 192300 kb
Host smart-81dc7031-a5c2-4613-a35e-6f3909452e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5217606072320831831356376058508258829801384628039790156142924476295120622129 -assert nopostproc +UV
M_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 46.gpio_intr_test.5217606072320831831356376058508258829801384628039790156142924476295120622129
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.29110634355402640498572679381150712781825622909531538237300774554769828091265
Short name T111
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:15 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 194124 kb
Host smart-aa56fe6d-a498-42d3-8a95-748e748d523b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110634355402640498572679381150712781825622909531538237300774554769828091265 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.29110634355402640498572679381150712781825622909531538237300774554769828091265
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3817742920187414689763492686082514008152689246594713274522353692223569571697
Short name T85
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 194028 kb
Host smart-674af443-be30-4ca0-b563-e83df3a69269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817742920187414689763492686082514008152689246594713274522353692223569571697 -assert nopostproc +UV
M_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 48.gpio_intr_test.3817742920187414689763492686082514008152689246594713274522353692223569571697
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.31877881796580141012787047143794602203231746417520625579225737662593785331591
Short name T966
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:23 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 194072 kb
Host smart-cb32e0fc-9730-41d9-8fe8-199ef5a63c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877881796580141012787047143794602203231746417520625579225737662593785331591 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.31877881796580141012787047143794602203231746417520625579225737662593785331591
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.34684410377619113717323096557997432436171952479733431867820481183627991074865
Short name T883
Test name
Test status
Simulation time 50029129 ps
CPU time 0.89 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 198272 kb
Host smart-79cb4d39-2027-4744-886d-fb4bc0170851
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468441037761911
3717323096557997432436171952479733431867820481183627991074865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_rese
t.34684410377619113717323096557997432436171952479733431867820481183627991074865
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.26707989782076575748183197753862786373572740651829261355879204083881370184586
Short name T884
Test name
Test status
Simulation time 22993631 ps
CPU time 0.65 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 194708 kb
Host smart-fb49e701-7921-43cc-b31f-98338d101fd5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267079897820765757481831977538627863735727406518292613558792040838813
70184586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_rw.26707989782076575748183197753862786373572740651829261355879204083881370184586
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.19908973373462484553358962430184161452826690201860071631646795001327328431618
Short name T39
Test name
Test status
Simulation time 25975750 ps
CPU time 0.67 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 194104 kb
Host smart-a5c5ea87-db72-47aa-ad01-fed912d105be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19908973373462484553358962430184161452826690201860071631646795001327328431618 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.19908973373462484553358962430184161452826690201860071631646795001327328431618
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.47408313062372146920071392584083588790354718355496090322934849090159456875582
Short name T969
Test name
Test status
Simulation time 49261278 ps
CPU time 0.84 seconds
Started Nov 22 01:18:04 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 196520 kb
Host smart-7b408b72-394a-4098-9ab6-ed81e54a02d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474083130623721469200713925840835887903547183554960
90322934849090159456875582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_same_csr_outstanding.474083130623721469200713925840835887903
54718355496090322934849090159456875582
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.66666862018645486828874735724384486660728678744935339762307668156609872108881
Short name T19
Test name
Test status
Simulation time 245206139 ps
CPU time 2.83 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 198352 kb
Host smart-9b165cc2-6004-4013-adcc-073709251912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66666862018645486828874735724384486660728678744935339762307668156609872108881 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.66666862018645486828874735724384486660728678744935339762307668156609872108881
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.98073385043622189183335538984545907670301141606863015882691986414145779693393
Short name T6
Test name
Test status
Simulation time 185438760 ps
CPU time 1.56 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 196572 kb
Host smart-7f295d72-3871-4d15-8254-9dfbba892b6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980733850436221891833355389845459076703011416068630158826919
86414145779693393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_intg_err.980733850436221891833355389845459076703011416068630158826
91986414145779693393
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.35955953666440748081302480473885147086867970770278895902154825468850061230335
Short name T40
Test name
Test status
Simulation time 50029129 ps
CPU time 0.87 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 198152 kb
Host smart-5c963a31-c9e1-49b7-8926-aae15e307142
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595595366644074
8081302480473885147086867970770278895902154825468850061230335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_rese
t.35955953666440748081302480473885147086867970770278895902154825468850061230335
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.92696532765015729245517383818526280958783887467062391049260159509743488377055
Short name T911
Test name
Test status
Simulation time 22993631 ps
CPU time 0.6 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 194668 kb
Host smart-adb3b243-8c97-4d60-a666-3348a0c77625
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926965327650157292455173838185262809587838874670623910492601595097434
88377055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_rw.92696532765015729245517383818526280958783887467062391049260159509743488377055
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1534762672288734876511042246784212726614728620152322360030677501494310705973
Short name T923
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 194056 kb
Host smart-e6ada1fc-04fb-4bb3-95a5-232778b67373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534762672288734876511042246784212726614728620152322360030677501494310705973 -assert nopostproc +UV
M_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.gpio_intr_test.1534762672288734876511042246784212726614728620152322360030677501494310705973
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.110724368469703572833950288530233288090549230907824152656241926258438489267788
Short name T918
Test name
Test status
Simulation time 49261278 ps
CPU time 0.82 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 196468 kb
Host smart-a5bf1873-681f-4d21-b885-622ea4b481ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110724368469703572833950288530233288090549230907824
152656241926258438489267788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_same_csr_outstanding.11072436846970357283395028853023328809
0549230907824152656241926258438489267788
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.81861151432198544253448880700834292001587010812028244720013122035092136616111
Short name T931
Test name
Test status
Simulation time 245206139 ps
CPU time 2.83 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 198324 kb
Host smart-32c33930-38bd-40fe-add5-b63ec578862a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81861151432198544253448880700834292001587010812028244720013122035092136616111 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.81861151432198544253448880700834292001587010812028244720013122035092136616111
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.48896488610069398684137003424789721283092030291354075656963121101240725963356
Short name T900
Test name
Test status
Simulation time 185438760 ps
CPU time 1.62 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 196200 kb
Host smart-d1ee09c7-b549-403d-b721-b372c7ea8572
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488964886100693986841370034247897212830920302913540756569631
21101240725963356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_intg_err.488964886100693986841370034247897212830920302913540756569
63121101240725963356
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.86514805183062581524745741264549490672044064398572002971408036048501115289664
Short name T11
Test name
Test status
Simulation time 50029129 ps
CPU time 0.93 seconds
Started Nov 22 01:18:05 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 198288 kb
Host smart-eb7eb1a5-9e7d-40e1-90f9-89178e44244f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8651480518306258
1524745741264549490672044064398572002971408036048501115289664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_rese
t.86514805183062581524745741264549490672044064398572002971408036048501115289664
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.29652157182838100796139857425342889936545281910226146004912260125383540465279
Short name T1
Test name
Test status
Simulation time 22993631 ps
CPU time 0.59 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 194736 kb
Host smart-2680ca8d-6c51-4975-b5b8-180436561d5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296521571828381007961398574253428899365452819102261460049122601253835
40465279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_rw.29652157182838100796139857425342889936545281910226146004912260125383540465279
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.92978958189464721098324565953875151941494239958630674095385841048984709511154
Short name T933
Test name
Test status
Simulation time 25975750 ps
CPU time 0.62 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 194076 kb
Host smart-ae121366-24c3-4b0b-bd01-5dc58f86ef4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92978958189464721098324565953875151941494239958630674095385841048984709511154 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.92978958189464721098324565953875151941494239958630674095385841048984709511154
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.13876061807237218586882864882426204512573118018409259452021437332689497493293
Short name T899
Test name
Test status
Simulation time 49261278 ps
CPU time 0.79 seconds
Started Nov 22 01:18:07 PM PST 23
Finished Nov 22 01:18:13 PM PST 23
Peak memory 196464 kb
Host smart-fc251771-36da-432d-b3c6-a9682cf60829
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138760618072372185868828648824262045125731180184092
59452021437332689497493293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_same_csr_outstanding.138760618072372185868828648824262045125
73118018409259452021437332689497493293
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.92319215729564507955817534116709781288426557762951337919043061334193952682647
Short name T28
Test name
Test status
Simulation time 245206139 ps
CPU time 2.74 seconds
Started Nov 22 01:18:02 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 198324 kb
Host smart-0c92759b-c0ad-415a-a71b-81bf3511b188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92319215729564507955817534116709781288426557762951337919043061334193952682647 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.92319215729564507955817534116709781288426557762951337919043061334193952682647
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.108481133832475942360711335390893196243929178963228666607193932331254064031349
Short name T99
Test name
Test status
Simulation time 185438760 ps
CPU time 1.35 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:15 PM PST 23
Peak memory 198444 kb
Host smart-1c0fabb4-8a0d-4183-81d5-e31019286adb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108481133832475942360711335390893196243929178963228666607193
932331254064031349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_intg_err.10848113383247594236071133539089319624392917896322866660
7193932331254064031349
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.7391367746011612684161903923482161289274239797255881803505261824998378221380
Short name T96
Test name
Test status
Simulation time 50029129 ps
CPU time 0.9 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 198244 kb
Host smart-05f1db9f-55c0-46f3-91e6-ca81489f4808
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7391367746011612
684161903923482161289274239797255881803505261824998378221380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset
.7391367746011612684161903923482161289274239797255881803505261824998378221380
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.47785533838842013439471179712260422469710666550104090089852894292835538092127
Short name T932
Test name
Test status
Simulation time 22993631 ps
CPU time 0.62 seconds
Started Nov 22 01:18:04 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 194776 kb
Host smart-750f7919-a8a1-46b1-9c44-84b55e203723
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477855338388420134394711797122604224697106665501040900898528942928355
38092127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_rw.47785533838842013439471179712260422469710666550104090089852894292835538092127
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.32215848751596065754993390440654188079601227611090581721878091186322177434390
Short name T2
Test name
Test status
Simulation time 25975750 ps
CPU time 0.61 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 193960 kb
Host smart-e994fc1f-5fe5-47cd-a6bf-cd0059bd32db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32215848751596065754993390440654188079601227611090581721878091186322177434390 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.32215848751596065754993390440654188079601227611090581721878091186322177434390
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.30440728228313636118217518723346073164011448196032433215213003173658231843865
Short name T27
Test name
Test status
Simulation time 49261278 ps
CPU time 0.81 seconds
Started Nov 22 01:18:08 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 196464 kb
Host smart-971ec64c-468a-44d1-9b79-ac0667c78e81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304407282283136361182175187233460731640114481960324
33215213003173658231843865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_same_csr_outstanding.304407282283136361182175187233460731640
11448196032433215213003173658231843865
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.111482737233924145255955685749522625774111801172819488556900583281074183429463
Short name T937
Test name
Test status
Simulation time 245206139 ps
CPU time 2.83 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 198472 kb
Host smart-4fb661e8-64cd-42d4-9af3-6313b8def43f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111482737233924145255955685749522625774111801172819488556900583281074183429463 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.111482737233924145255955685749522625774111801172819488556900583281074183429463
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.75276256206188415952469507431079390420510165310724767035711951193904435728387
Short name T878
Test name
Test status
Simulation time 185438760 ps
CPU time 1.39 seconds
Started Nov 22 01:18:22 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 198360 kb
Host smart-4cc6ef7d-98e0-4068-b8f4-2733c5011b4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752762562061884159524695074310793904205101653107247670357119
51193904435728387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_intg_err.752762562061884159524695074310793904205101653107247670357
11951193904435728387
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.68835012894643591078988314520902421316159844505441022604110124307203791658701
Short name T890
Test name
Test status
Simulation time 50029129 ps
CPU time 0.88 seconds
Started Nov 22 01:18:21 PM PST 23
Finished Nov 22 01:18:26 PM PST 23
Peak memory 198272 kb
Host smart-e9e825b0-6e4c-4869-bfee-7fda7affde00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6883501289464359
1078988314520902421316159844505441022604110124307203791658701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_rese
t.68835012894643591078988314520902421316159844505441022604110124307203791658701
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.46342616894659233923835007573411831690915884712534109961687652205443112078619
Short name T32
Test name
Test status
Simulation time 22993631 ps
CPU time 0.65 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 194684 kb
Host smart-e6d68327-4eb9-4d73-9423-d6fa5af72084
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463426168946592339238350075734118316909158847125341099616876522054431
12078619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_rw.46342616894659233923835007573411831690915884712534109961687652205443112078619
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.78408899344258198760807712090786438316383961296644338234234715481215050071725
Short name T93
Test name
Test status
Simulation time 25975750 ps
CPU time 0.6 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 194048 kb
Host smart-cedd14a3-26be-4937-aeac-2be177b577fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78408899344258198760807712090786438316383961296644338234234715481215050071725 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.78408899344258198760807712090786438316383961296644338234234715481215050071725
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.87209067684351981960096462894302801842794963918326567504092816151462530763698
Short name T905
Test name
Test status
Simulation time 49261278 ps
CPU time 0.84 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 196412 kb
Host smart-7a1a529e-5c01-40bb-9e87-499cfdc09449
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872090676843519819600964628943028018427949639183265
67504092816151462530763698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_same_csr_outstanding.872090676843519819600964628943028018427
94963918326567504092816151462530763698
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.68940419914454916008333765901246901647709679866325626487699028935609482015406
Short name T895
Test name
Test status
Simulation time 245206139 ps
CPU time 2.83 seconds
Started Nov 22 01:18:31 PM PST 23
Finished Nov 22 01:18:36 PM PST 23
Peak memory 198412 kb
Host smart-fcb05afa-f559-42a5-bf30-58cf78f2aa68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68940419914454916008333765901246901647709679866325626487699028935609482015406 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.68940419914454916008333765901246901647709679866325626487699028935609482015406
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.73609098600040550593773420715174191580411206321334708060444490365436101103385
Short name T922
Test name
Test status
Simulation time 185438760 ps
CPU time 1.42 seconds
Started Nov 22 01:18:14 PM PST 23
Finished Nov 22 01:18:20 PM PST 23
Peak memory 198352 kb
Host smart-f7700553-230a-4a46-b860-5bbe3ba985ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736090986000405505937734207151741915804112063213347080604444
90365436101103385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_intg_err.736090986000405505937734207151741915804112063213347080604
44490365436101103385
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.37468849116796597752554589193640574134186575562455530955312241664001442304065
Short name T713
Test name
Test status
Simulation time 22440064 ps
CPU time 0.57 seconds
Started Nov 22 12:20:44 PM PST 23
Finished Nov 22 12:20:46 PM PST 23
Peak memory 193400 kb
Host smart-b3213e26-efc6-4153-814a-9ae72c63ab4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37468849116796597752554589193640574134186575562455530955312241664001442304065 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.gpio_alert_test.37468849116796597752554589193640574134186575562455530955312241664001442304065
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.85841803161456950516395927814763804079603767140949215500857836550090163320040
Short name T660
Test name
Test status
Simulation time 57921923 ps
CPU time 0.81 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:25 PM PST 23
Peak memory 195844 kb
Host smart-b2793b28-946d-4867-9c2a-7605d17c1459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85841803161456950516395927814763804079603767140949215500857836550090163320040 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.85841803161456950516395927814763804079603767140949215500857836550090163320040
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.99160549929915946030127326247591543867990107049171563030503623252438526279335
Short name T600
Test name
Test status
Simulation time 1135699015 ps
CPU time 22 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 195040 kb
Host smart-7150059c-23f0-4a7d-979c-52ec61e064d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99160549929915946030127326247591543867990107049171563030503623252438526279335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress.99160549929915946030127326247591543867990107049171563030503623252438526279335
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.16868549111879356314834998411434126487924806460539068445160686870234815028386
Short name T676
Test name
Test status
Simulation time 137439144 ps
CPU time 1 seconds
Started Nov 22 12:27:01 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 196140 kb
Host smart-54f713f5-2642-40fd-a53b-d1b01d2d8565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16868549111879356314834998411434126487924806460539068445160686870234815028386 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.16868549111879356314834998411434126487924806460539068445160686870234815028386
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.103337769071528493495486554422441429414696990452973066809873683762898368164791
Short name T74
Test name
Test status
Simulation time 119314289 ps
CPU time 1.21 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:27:24 PM PST 23
Peak memory 194196 kb
Host smart-99a76735-6d2c-4adb-8aed-622adbc899aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103337769071528493495486554422441429414696990452973066809873683762898368164791 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.103337769071528493495486554422441429414696990452973066809873683762898368164791
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.72835096764368690500728025913081895952147418689611564676562574477368415558149
Short name T364
Test name
Test status
Simulation time 134635595 ps
CPU time 3.12 seconds
Started Nov 22 12:22:10 PM PST 23
Finished Nov 22 12:22:14 PM PST 23
Peak memory 197000 kb
Host smart-d1a85213-d3d6-4b1e-8c93-6a5ed1ee27ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72835096764368690500728025913081895952147418689611564676562574477368
415558149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.728350967643686905007280
25913081895952147418689611564676562574477368415558149
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.71095082347850906927235268476635957621804087921000376316040693675310477820802
Short name T501
Test name
Test status
Simulation time 228920555 ps
CPU time 2.69 seconds
Started Nov 22 12:26:35 PM PST 23
Finished Nov 22 12:26:38 PM PST 23
Peak memory 195704 kb
Host smart-5a72822b-d984-437f-bbf3-862900c4532d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71095082347850906927235268476635957621804087921000376316040693675310477820802 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.71095082347850906927235268476635957621804087921000376316040693675310477820802
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.8005327382403692818965428372167600077375732285625226112978374366473429469268
Short name T474
Test name
Test status
Simulation time 81278879 ps
CPU time 1.09 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:27:24 PM PST 23
Peak memory 195144 kb
Host smart-9251e737-59b9-4db3-ab30-972d11209f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8005327382403692818965428372167600077375732285625226112978374366473429469268 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_random_dout_din.8005327382403692818965428372167600077375732285625226112978374366473429469268
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.99743697754859562676942378035587015804260403756823509857710387166773336663813
Short name T258
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:21:44 PM PST 23
Finished Nov 22 12:21:45 PM PST 23
Peak memory 195860 kb
Host smart-83dafcb8-56ad-45ef-be84-5ad2f81aa0e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99743697754859562676942378035587015804260403756823509857710387166773336663813 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_pulldown.99743697754859562676942378035587015804260403756823509857710387166773336663813
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.88670727954781275253766586287962356891964360217829521541078597136270715861270
Short name T550
Test name
Test status
Simulation time 572864232 ps
CPU time 5.02 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 197216 kb
Host smart-1cac130b-8b73-4489-ad1a-bd31c6c6c91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88670727954781275253766586287962356891964360217829521541078597136270715861270 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_long_reg_writes_reg_reads.8867072795478127525376658628796235689196436021782
9521541078597136270715861270
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.22393712020508843193892323322571868134417921226585658261278405483392284799017
Short name T739
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:21:51 PM PST 23
Finished Nov 22 12:21:53 PM PST 23
Peak memory 195384 kb
Host smart-8998a124-01e3-478e-8efe-86c99e5ba96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22393712020508843193892323322571868134417921226585658261278405483392284799017 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.gpio_smoke.22393712020508843193892323322571868134417921226585658261278405483392284799017
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.38649199488511962053647312972932657536709994323721772505201052192139989940444
Short name T372
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:20:39 PM PST 23
Finished Nov 22 12:20:41 PM PST 23
Peak memory 195412 kb
Host smart-3f90d124-330c-4d8e-a23b-b2e2866f3fb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649199488511962053647312972932657536709994323721772505201052192139989940444 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.38649199488511962053647312972932657536709994323721772505201052192139989940444
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.11715543009324291313857075513820069539885955083391239277752856713063038918827
Short name T643
Test name
Test status
Simulation time 21104521406 ps
CPU time 162.82 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:28:46 PM PST 23
Peak memory 197816 kb
Host smart-0b90ffd7-b67f-4ca3-9ed5-62e7600822d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171554300932429131385707551382006953988595508339123927775285671
3063038918827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all.1171554300932429131385707551382006953988595508339123927775285671
3063038918827
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.44750695313172941011030127280577604622251231935443512145347496461820904608474
Short name T707
Test name
Test status
Simulation time 133069054254 ps
CPU time 1092.75 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:45:20 PM PST 23
Peak memory 197960 kb
Host smart-1fedefee-7844-44ae-b484-7b1079d7b8d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=44750695313172941011030127280577604622251231935443512145347496461820904608474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_wit
h_rand_reset.44750695313172941011030127280577604622251231935443512145347496461820904608474
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.42732217865674145314419756465395948714489040723129847533408714675931539074676
Short name T622
Test name
Test status
Simulation time 22440064 ps
CPU time 0.61 seconds
Started Nov 22 12:20:35 PM PST 23
Finished Nov 22 12:20:37 PM PST 23
Peak memory 193496 kb
Host smart-89273b27-6d6d-4df1-9a45-1aff0ac46959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42732217865674145314419756465395948714489040723129847533408714675931539074676 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.gpio_alert_test.42732217865674145314419756465395948714489040723129847533408714675931539074676
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.26654636819628539046631304663357666367946954267013509637303380398554766178144
Short name T538
Test name
Test status
Simulation time 57921923 ps
CPU time 0.85 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 194784 kb
Host smart-0b5a74be-af30-49a5-ba91-4aeba2f7d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26654636819628539046631304663357666367946954267013509637303380398554766178144 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.26654636819628539046631304663357666367946954267013509637303380398554766178144
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.83348846888652463047060950707418098443271144856704429363696171657870392501899
Short name T652
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.47 seconds
Started Nov 22 12:22:05 PM PST 23
Finished Nov 22 12:22:29 PM PST 23
Peak memory 195424 kb
Host smart-85202cb5-e191-4101-9c95-1be3e149f4ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83348846888652463047060950707418098443271144856704429363696171657870392501899 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.83348846888652463047060950707418098443271144856704429363696171657870392501899
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.17474200973799451903640389672285288756159288507961384257289149662325284253916
Short name T219
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:25:59 PM PST 23
Peak memory 196020 kb
Host smart-df974f02-183c-400b-a0f6-75d5252c41af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17474200973799451903640389672285288756159288507961384257289149662325284253916 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.17474200973799451903640389672285288756159288507961384257289149662325284253916
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.45374710418840076038372987872011584055718890660764492755176361811479117115241
Short name T321
Test name
Test status
Simulation time 119314289 ps
CPU time 1.16 seconds
Started Nov 22 12:26:56 PM PST 23
Finished Nov 22 12:27:02 PM PST 23
Peak memory 195220 kb
Host smart-9a214d9a-647c-46be-8bf4-58c2204a4b32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45374710418840076038372987872011584055718890660764492755176361811479117115241 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.45374710418840076038372987872011584055718890660764492755176361811479117115241
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.22602485088805119102669189797336818828556596387901928595431297696692263279886
Short name T363
Test name
Test status
Simulation time 134635595 ps
CPU time 2.93 seconds
Started Nov 22 12:26:47 PM PST 23
Finished Nov 22 12:26:52 PM PST 23
Peak memory 197108 kb
Host smart-fd4c097d-2b8c-4ae3-a92b-af7318786004
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602485088805119102669189797336818828556596387901928595431297696692
263279886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.226024850888051191026691
89797336818828556596387901928595431297696692263279886
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.71512272214199349646348902297236446380854334514554694192067164618555615220641
Short name T554
Test name
Test status
Simulation time 228920555 ps
CPU time 2.91 seconds
Started Nov 22 12:21:44 PM PST 23
Finished Nov 22 12:21:48 PM PST 23
Peak memory 195856 kb
Host smart-00691106-d85f-4762-b2b3-35c98f31a935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71512272214199349646348902297236446380854334514554694192067164618555615220641 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.71512272214199349646348902297236446380854334514554694192067164618555615220641
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.58654876011387290360420964687680241705295002910352144785782864549099565368131
Short name T805
Test name
Test status
Simulation time 81278879 ps
CPU time 1.1 seconds
Started Nov 22 12:27:17 PM PST 23
Finished Nov 22 12:27:24 PM PST 23
Peak memory 195284 kb
Host smart-cf79fff0-bc12-4efa-9331-56b7444215d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58654876011387290360420964687680241705295002910352144785782864549099565368131 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.gpio_random_dout_din.58654876011387290360420964687680241705295002910352144785782864549099565368131
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.81983850056095179140338059386060090906815362540282521121939057258954856783994
Short name T829
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:23:47 PM PST 23
Finished Nov 22 12:23:50 PM PST 23
Peak memory 195732 kb
Host smart-ffdbb0cb-5dd1-498e-959c-ffbc136ffe18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81983850056095179140338059386060090906815362540282521121939057258954856783994 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_pulldown.81983850056095179140338059386060090906815362540282521121939057258954856783994
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4148244239699500727206909203690468915432402094949975243203819607078161763512
Short name T373
Test name
Test status
Simulation time 572864232 ps
CPU time 5.02 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:05 PM PST 23
Peak memory 195412 kb
Host smart-4fd9e4df-9eae-45b2-a264-7f62c8cfe513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148244239699500727206909203690468915432402094949975243203819607078161763512 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_long_reg_writes_reg_reads.41482442396995007272069092036904689154324020949499
75243203819607078161763512
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.24201442229378692547427895345331364558995688512601968284335753791238002773745
Short name T72
Test name
Test status
Simulation time 134885593 ps
CPU time 0.92 seconds
Started Nov 22 12:22:42 PM PST 23
Finished Nov 22 12:22:43 PM PST 23
Peak memory 214736 kb
Host smart-9638ab0c-00a4-4e7d-88ad-078112a70835
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24201442229378692547427895345331364558995688512601968284335753791238002773745 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.gpio_sec_cm.24201442229378692547427895345331364558995688512601968284335753791238002773745
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.68814122917653118601346693895756522719780300421155293645830492627919817292947
Short name T512
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:03 PM PST 23
Peak memory 195100 kb
Host smart-84316d71-682d-40dd-a13b-d42925476ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68814122917653118601346693895756522719780300421155293645830492627919817292947 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.gpio_smoke.68814122917653118601346693895756522719780300421155293645830492627919817292947
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.31030611449248264058382943868624084779875272510269499067617558903469391491602
Short name T611
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:23:29 PM PST 23
Finished Nov 22 12:23:30 PM PST 23
Peak memory 195492 kb
Host smart-e6cf3f71-8318-4529-8351-73e5e13cfece
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030611449248264058382943868624084779875272510269499067617558903469391491602 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.31030611449248264058382943868624084779875272510269499067617558903469391491602
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.111870825400379904576696042503576997311486269589323412263601616074725805872614
Short name T441
Test name
Test status
Simulation time 21104521406 ps
CPU time 170.75 seconds
Started Nov 22 12:26:54 PM PST 23
Finished Nov 22 12:29:48 PM PST 23
Peak memory 197516 kb
Host smart-cc56d281-fc6e-439c-bf57-20a9fa322b78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118708254003799045766960425035769973114862695893234122636016160
74725805872614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all.111870825400379904576696042503576997311486269589323412263601616
074725805872614
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.95689114867951602522767138837088201558169253601084267017394062926788381658638
Short name T803
Test name
Test status
Simulation time 133069054254 ps
CPU time 1073.31 seconds
Started Nov 22 12:27:17 PM PST 23
Finished Nov 22 12:45:19 PM PST 23
Peak memory 197840 kb
Host smart-e2e22a7d-6a8f-4aca-bffd-d994ee316e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=95689114867951602522767138837088201558169253601084267017394062926788381658638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_wit
h_rand_reset.95689114867951602522767138837088201558169253601084267017394062926788381658638
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.115549588616482552473433655010853763297371910754738609248127792914444414217585
Short name T759
Test name
Test status
Simulation time 22440064 ps
CPU time 0.61 seconds
Started Nov 22 12:26:54 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 192968 kb
Host smart-cf89845b-e88f-46f6-a773-429e791a9606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115549588616482552473433655010853763297371910754738609248127792914444414217585 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.115549588616482552473433655010853763297371910754738609248127792914444414217585
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.80454761455644122777353464430748921406872687983840693468478137006682755269582
Short name T766
Test name
Test status
Simulation time 57921923 ps
CPU time 0.83 seconds
Started Nov 22 12:21:24 PM PST 23
Finished Nov 22 12:21:27 PM PST 23
Peak memory 196152 kb
Host smart-8aee6cd2-601a-487b-be7e-b3e42836595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80454761455644122777353464430748921406872687983840693468478137006682755269582 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.80454761455644122777353464430748921406872687983840693468478137006682755269582
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.68165149290477106844522682019848618441217184926156877679046125390942402481073
Short name T579
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.49 seconds
Started Nov 22 12:23:02 PM PST 23
Finished Nov 22 12:23:25 PM PST 23
Peak memory 195376 kb
Host smart-9560a435-4034-433a-bdd6-a5a02dc24dcb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68165149290477106844522682019848618441217184926156877679046125390942402481073 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stress.68165149290477106844522682019848618441217184926156877679046125390942402481073
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.86264003437742124343694496116797314449508947674783654130619398143657743562203
Short name T332
Test name
Test status
Simulation time 137439144 ps
CPU time 1 seconds
Started Nov 22 12:21:06 PM PST 23
Finished Nov 22 12:21:08 PM PST 23
Peak memory 196268 kb
Host smart-d666eb64-0083-4563-b234-7b644823df01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86264003437742124343694496116797314449508947674783654130619398143657743562203 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.86264003437742124343694496116797314449508947674783654130619398143657743562203
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.90455456724957836609017955370484569755745426595772011612250161214591263616421
Short name T615
Test name
Test status
Simulation time 119314289 ps
CPU time 1.23 seconds
Started Nov 22 12:24:33 PM PST 23
Finished Nov 22 12:24:35 PM PST 23
Peak memory 195700 kb
Host smart-e403a997-966f-4c91-a1b1-958372e4a4c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90455456724957836609017955370484569755745426595772011612250161214591263616421 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.90455456724957836609017955370484569755745426595772011612250161214591263616421
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.60614180863364729147473246232905365539349573118846237171098209604383143754097
Short name T435
Test name
Test status
Simulation time 134635595 ps
CPU time 3.13 seconds
Started Nov 22 12:24:50 PM PST 23
Finished Nov 22 12:24:54 PM PST 23
Peak memory 197068 kb
Host smart-20b16c69-2c99-4e20-936a-2409593318c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60614180863364729147473246232905365539349573118846237171098209604383
143754097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.60614180863364729147473
246232905365539349573118846237171098209604383143754097
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.29683362974472952681907619276750802165137094596867917697769818348513095712302
Short name T224
Test name
Test status
Simulation time 228920555 ps
CPU time 2.93 seconds
Started Nov 22 12:22:23 PM PST 23
Finished Nov 22 12:22:27 PM PST 23
Peak memory 195740 kb
Host smart-29642f87-4024-477d-9f74-6f75582c5626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683362974472952681907619276750802165137094596867917697769818348513095712302 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.29683362974472952681907619276750802165137094596867917697769818348513095712302
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.100241718462266528170564826599331933322480056432452563870054457652157529118079
Short name T295
Test name
Test status
Simulation time 81278879 ps
CPU time 1.23 seconds
Started Nov 22 12:27:04 PM PST 23
Finished Nov 22 12:27:12 PM PST 23
Peak memory 194188 kb
Host smart-fae4335d-9601-4e1c-a06b-ab0871e0bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100241718462266528170564826599331933322480056432452563870054457652157529118079 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_random_dout_din.100241718462266528170564826599331933322480056432452563870054457652157529118079
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.93166479185992657251391610419089076711862233523019863181845288472866409293069
Short name T587
Test name
Test status
Simulation time 81278879 ps
CPU time 1.16 seconds
Started Nov 22 12:21:08 PM PST 23
Finished Nov 22 12:21:10 PM PST 23
Peak memory 195432 kb
Host smart-1e7353bf-abeb-48aa-9016-c911025972bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93166479185992657251391610419089076711862233523019863181845288472866409293069 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup_pulldown.93166479185992657251391610419089076711862233523019863181845288472866409293069
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.46480050375349884000305324522035620245164121083277495058300677788816221193107
Short name T664
Test name
Test status
Simulation time 572864232 ps
CPU time 5.19 seconds
Started Nov 22 12:25:30 PM PST 23
Finished Nov 22 12:25:36 PM PST 23
Peak memory 197736 kb
Host smart-6bf13466-f2ea-4461-893a-2e668b97bcc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46480050375349884000305324522035620245164121083277495058300677788816221193107 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_long_reg_writes_reg_reads.464800503753498840003053245220356202451641210832
77495058300677788816221193107
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.102065218227079959942816582706064626278608330108219364112087576476899966258893
Short name T312
Test name
Test status
Simulation time 112796484 ps
CPU time 1.31 seconds
Started Nov 22 12:20:57 PM PST 23
Finished Nov 22 12:20:59 PM PST 23
Peak memory 195568 kb
Host smart-21830929-0941-4bad-8a3d-d2e223b3e0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102065218227079959942816582706064626278608330108219364112087576476899966258893 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.gpio_smoke.102065218227079959942816582706064626278608330108219364112087576476899966258893
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.63453829805651542506971930811474088876722341959064997408429101073314368817256
Short name T715
Test name
Test status
Simulation time 112796484 ps
CPU time 1.2 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:01 PM PST 23
Peak memory 195424 kb
Host smart-06adb362-cb14-44aa-8cb5-cc0e3a5ff9c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63453829805651542506971930811474088876722341959064997408429101073314368817256 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.63453829805651542506971930811474088876722341959064997408429101073314368817256
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.56653691966438767856926746758190362748404452973573062369123212154201032482946
Short name T293
Test name
Test status
Simulation time 21104521406 ps
CPU time 179.64 seconds
Started Nov 22 12:24:16 PM PST 23
Finished Nov 22 12:27:16 PM PST 23
Peak memory 198016 kb
Host smart-18edff41-c953-40ea-9063-417d972f3fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5665369196643876785692674675819036274840445297357306236912321215
4201032482946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all.566536919664387678569267467581903627484044529735730623691232121
54201032482946
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.97426800960823582874053499775752221056636383297146379737420417454408441977603
Short name T672
Test name
Test status
Simulation time 133069054254 ps
CPU time 1103.06 seconds
Started Nov 22 12:26:35 PM PST 23
Finished Nov 22 12:44:59 PM PST 23
Peak memory 197296 kb
Host smart-a33fbab3-c0b2-4c35-b3de-6de1f71b5a32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=97426800960823582874053499775752221056636383297146379737420417454408441977603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_wi
th_rand_reset.97426800960823582874053499775752221056636383297146379737420417454408441977603
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.62086500480777846296657906725498805193136508197673601768858356044620889943659
Short name T209
Test name
Test status
Simulation time 57921923 ps
CPU time 0.83 seconds
Started Nov 22 12:27:02 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 196132 kb
Host smart-23b76dea-dc92-486b-a4a7-b31dc88559ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62086500480777846296657906725498805193136508197673601768858356044620889943659 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.62086500480777846296657906725498805193136508197673601768858356044620889943659
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.14778788360450907125681179359911629394132765920166737382151720896776154143293
Short name T810
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.33 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:21 PM PST 23
Peak memory 195392 kb
Host smart-00dbd542-a75c-467e-a2a9-648872343f28
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778788360450907125681179359911629394132765920166737382151720896776154143293 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stress.14778788360450907125681179359911629394132765920166737382151720896776154143293
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.17856743826488318022464755716250689018403681568557227869473806576324582950041
Short name T382
Test name
Test status
Simulation time 137439144 ps
CPU time 0.95 seconds
Started Nov 22 12:26:56 PM PST 23
Finished Nov 22 12:27:03 PM PST 23
Peak memory 196232 kb
Host smart-0af54dd6-7153-4f57-b341-9323d6533f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856743826488318022464755716250689018403681568557227869473806576324582950041 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.17856743826488318022464755716250689018403681568557227869473806576324582950041
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.98385376595298392608687353968198870680569226580591892369571532542886649996711
Short name T208
Test name
Test status
Simulation time 119314289 ps
CPU time 1.25 seconds
Started Nov 22 12:21:24 PM PST 23
Finished Nov 22 12:21:27 PM PST 23
Peak memory 195664 kb
Host smart-24ffae54-f07c-44f3-830b-0ba6888264f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98385376595298392608687353968198870680569226580591892369571532542886649996711 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.98385376595298392608687353968198870680569226580591892369571532542886649996711
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.37829084322105612838538654833704693991253915141457580950307960403894344847539
Short name T508
Test name
Test status
Simulation time 134635595 ps
CPU time 2.98 seconds
Started Nov 22 12:23:45 PM PST 23
Finished Nov 22 12:23:49 PM PST 23
Peak memory 197116 kb
Host smart-d3453e6a-cf5d-443f-83f6-fbb3da3206f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37829084322105612838538654833704693991253915141457580950307960403894
344847539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.37829084322105612838538
654833704693991253915141457580950307960403894344847539
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.43999433080569390741587491691425508070718048751483089035924560539187661366106
Short name T333
Test name
Test status
Simulation time 228920555 ps
CPU time 2.64 seconds
Started Nov 22 12:27:30 PM PST 23
Finished Nov 22 12:27:42 PM PST 23
Peak memory 195628 kb
Host smart-f637536d-7025-413b-a00d-be3d39ba2df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43999433080569390741587491691425508070718048751483089035924560539187661366106 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.43999433080569390741587491691425508070718048751483089035924560539187661366106
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.98590284159614011905693774861885032830728856258333275292193647809924288871756
Short name T527
Test name
Test status
Simulation time 81278879 ps
CPU time 1.18 seconds
Started Nov 22 12:25:41 PM PST 23
Finished Nov 22 12:25:45 PM PST 23
Peak memory 195648 kb
Host smart-0d990395-14da-49d5-b9f6-1c170ce73d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98590284159614011905693774861885032830728856258333275292193647809924288871756 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_random_dout_din.98590284159614011905693774861885032830728856258333275292193647809924288871756
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.71693540208391694016859159924825425499986993014546036597629195498580537123180
Short name T252
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:23:18 PM PST 23
Finished Nov 22 12:23:19 PM PST 23
Peak memory 195704 kb
Host smart-ae6a7569-7102-4bae-ada2-3bb3ca9021b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71693540208391694016859159924825425499986993014546036597629195498580537123180 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup_pulldown.71693540208391694016859159924825425499986993014546036597629195498580537123180
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.43946204194610884583279381081042446140830790624292363205165506586158347323937
Short name T735
Test name
Test status
Simulation time 572864232 ps
CPU time 5.12 seconds
Started Nov 22 12:26:58 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 197588 kb
Host smart-d7717661-51a2-45c2-92f0-397bd7513893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43946204194610884583279381081042446140830790624292363205165506586158347323937 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_long_reg_writes_reg_reads.439462041946108845832793810810424461408307906242
92363205165506586158347323937
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.26780662672031165990116835961438973281333130135090993948323422554369878823908
Short name T856
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:26:14 PM PST 23
Finished Nov 22 12:26:18 PM PST 23
Peak memory 195340 kb
Host smart-fcfd3bd7-1ce2-4312-a249-82df29fa3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26780662672031165990116835961438973281333130135090993948323422554369878823908 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.gpio_smoke.26780662672031165990116835961438973281333130135090993948323422554369878823908
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.76946931391720620367994725881321359944010625987049573177981355256968628495333
Short name T797
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:23:19 PM PST 23
Finished Nov 22 12:23:20 PM PST 23
Peak memory 195660 kb
Host smart-66a721b6-1e49-4dd9-9d4c-10d01d164a1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76946931391720620367994725881321359944010625987049573177981355256968628495333 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.76946931391720620367994725881321359944010625987049573177981355256968628495333
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.34860154422899689041694614968755514581134667757830395681398284907374091926827
Short name T442
Test name
Test status
Simulation time 21104521406 ps
CPU time 164.6 seconds
Started Nov 22 12:23:18 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 198224 kb
Host smart-e655d6a4-79f7-40e4-9f22-b6ddc4ec27f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486015442289968904169461496875551458113466775783039568139828490
7374091926827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all.348601544228996890416946149687555145811346677578303956813982849
07374091926827
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.96673396558441476280367258841708496707965177079679106298201300706898492201275
Short name T812
Test name
Test status
Simulation time 133069054254 ps
CPU time 1099.93 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:45:20 PM PST 23
Peak memory 197884 kb
Host smart-650cfbfd-4413-43a8-a528-4f2b0b8fadb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=96673396558441476280367258841708496707965177079679106298201300706898492201275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_wi
th_rand_reset.96673396558441476280367258841708496707965177079679106298201300706898492201275
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.58379960135562528227654757851904970902122984056763222511575253013334255937815
Short name T308
Test name
Test status
Simulation time 22440064 ps
CPU time 0.62 seconds
Started Nov 22 12:26:51 PM PST 23
Finished Nov 22 12:26:54 PM PST 23
Peak memory 193820 kb
Host smart-3a03bc4d-bd38-43f1-9ff7-7b976972b88a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58379960135562528227654757851904970902122984056763222511575253013334255937815 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.gpio_alert_test.58379960135562528227654757851904970902122984056763222511575253013334255937815
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.37902080827963352476785252422211138786314246529921536555457582238487878261688
Short name T572
Test name
Test status
Simulation time 57921923 ps
CPU time 0.88 seconds
Started Nov 22 12:21:08 PM PST 23
Finished Nov 22 12:21:10 PM PST 23
Peak memory 195872 kb
Host smart-20a4c2b5-8422-436b-b7a9-9d0f7ece8742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37902080827963352476785252422211138786314246529921536555457582238487878261688 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.37902080827963352476785252422211138786314246529921536555457582238487878261688
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.41056989787216266027755555307627677203606507002310090516906792289074450928724
Short name T285
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.77 seconds
Started Nov 22 12:23:57 PM PST 23
Finished Nov 22 12:24:23 PM PST 23
Peak memory 195416 kb
Host smart-ad3f9a79-9143-40b8-aa9a-f221a1b48d2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056989787216266027755555307627677203606507002310090516906792289074450928724 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stress.41056989787216266027755555307627677203606507002310090516906792289074450928724
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.75648668649451754135252217160599447892746349424780224213128543993869032822432
Short name T528
Test name
Test status
Simulation time 137439144 ps
CPU time 0.92 seconds
Started Nov 22 12:26:08 PM PST 23
Finished Nov 22 12:26:11 PM PST 23
Peak memory 196212 kb
Host smart-c664d256-e247-49e1-ae72-8f37df026921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75648668649451754135252217160599447892746349424780224213128543993869032822432 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.75648668649451754135252217160599447892746349424780224213128543993869032822432
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.68626741523331837882043799330818412466158405515207311692744523970312277801211
Short name T380
Test name
Test status
Simulation time 119314289 ps
CPU time 1.25 seconds
Started Nov 22 12:23:46 PM PST 23
Finished Nov 22 12:23:49 PM PST 23
Peak memory 195708 kb
Host smart-1fb9bf93-180a-4aff-a40e-32c32d43934b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68626741523331837882043799330818412466158405515207311692744523970312277801211 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.68626741523331837882043799330818412466158405515207311692744523970312277801211
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.29171344459972330474331059832655444380400858249531196911156507220518077617199
Short name T462
Test name
Test status
Simulation time 134635595 ps
CPU time 2.91 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:09 PM PST 23
Peak memory 196996 kb
Host smart-04d4c783-2bea-45a3-83ad-8b4a51390b7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29171344459972330474331059832655444380400858249531196911156507220518
077617199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.29171344459972330474331
059832655444380400858249531196911156507220518077617199
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3101576466589210889472230669110387597800636317055309034118867015893929277284
Short name T370
Test name
Test status
Simulation time 228920555 ps
CPU time 2.9 seconds
Started Nov 22 12:21:59 PM PST 23
Finished Nov 22 12:22:05 PM PST 23
Peak memory 195684 kb
Host smart-aaa3bd50-5a4f-4d19-8755-8502fe79ec7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101576466589210889472230669110387597800636317055309034118867015893929277284 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.3101576466589210889472230669110387597800636317055309034118867015893929277284
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.102509682316879409174382716103577252163487822770186734397772408422449545545862
Short name T357
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:26:54 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 195752 kb
Host smart-69f731da-5738-44e7-881a-5b7789a2c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102509682316879409174382716103577252163487822770186734397772408422449545545862 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_random_dout_din.102509682316879409174382716103577252163487822770186734397772408422449545545862
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.110975875527827919771015357834389304704238125774450293781961694102679349518592
Short name T274
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:25:28 PM PST 23
Finished Nov 22 12:25:30 PM PST 23
Peak memory 195700 kb
Host smart-90945782-2435-4d3f-b028-07f0e8c9c679
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110975875527827919771015357834389304704238125774450293781961694102679349518592 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup_pulldown.110975875527827919771015357834389304704238125774450293781961694102679349518592
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.73371551871610572996746707093338327099283787320049796640046030741650753138773
Short name T281
Test name
Test status
Simulation time 572864232 ps
CPU time 5.16 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:57 PM PST 23
Peak memory 197776 kb
Host smart-0b2fc54a-2395-4a62-a34e-ae30b5cf5d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73371551871610572996746707093338327099283787320049796640046030741650753138773 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_long_reg_writes_reg_reads.733715518716105729967467070933383270992837873200
49796640046030741650753138773
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.41986506270060085670621641724267221692820725926335006810427329250958086716767
Short name T564
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 195160 kb
Host smart-3eb3496a-9012-4b6b-b1b0-8c4b15378fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41986506270060085670621641724267221692820725926335006810427329250958086716767 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.gpio_smoke.41986506270060085670621641724267221692820725926335006810427329250958086716767
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.79215094283589211154014512903419226972684138288179813771342757863037498496370
Short name T531
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 193800 kb
Host smart-28250b43-bec3-43d3-986d-bb4f3f5289ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79215094283589211154014512903419226972684138288179813771342757863037498496370 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.79215094283589211154014512903419226972684138288179813771342757863037498496370
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.77822600871279488653920978720546729896168980380004218924986248231424940150705
Short name T236
Test name
Test status
Simulation time 21104521406 ps
CPU time 170.27 seconds
Started Nov 22 12:22:10 PM PST 23
Finished Nov 22 12:25:01 PM PST 23
Peak memory 198008 kb
Host smart-e28ad27c-3e36-4013-8fc4-b5c102312074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7782260087127948865392097872054672989616898038000421892498624823
1424940150705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all.778226008712794886539209787205467298961689803800042189249862482
31424940150705
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.115254681644650073002026326768211001864312920967593749044576154696992081435083
Short name T683
Test name
Test status
Simulation time 133069054254 ps
CPU time 1159.74 seconds
Started Nov 22 12:25:51 PM PST 23
Finished Nov 22 12:45:12 PM PST 23
Peak memory 198184 kb
Host smart-e6b07cd5-6bbe-41bd-9a01-c30d002fb847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=115254681644650073002026326768211001864312920967593749044576154696992081435083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_w
ith_rand_reset.115254681644650073002026326768211001864312920967593749044576154696992081435083
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.30630317410846411510810937181118103215263118781427766732034438234584582160417
Short name T500
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:21:22 PM PST 23
Finished Nov 22 12:21:23 PM PST 23
Peak memory 193820 kb
Host smart-73b803bc-b2f0-4c6a-a9c0-15ebf3262d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30630317410846411510810937181118103215263118781427766732034438234584582160417 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.gpio_alert_test.30630317410846411510810937181118103215263118781427766732034438234584582160417
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.99877770588142914094894421434310822300773763164648829267708594320719047396976
Short name T802
Test name
Test status
Simulation time 57921923 ps
CPU time 0.76 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 195928 kb
Host smart-43aaf8a8-2ee8-4b9f-8ee2-f0b9430bb8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99877770588142914094894421434310822300773763164648829267708594320719047396976 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.99877770588142914094894421434310822300773763164648829267708594320719047396976
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.94189401480650494227396305940170435064613042394249324910881519120470306735978
Short name T778
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.27 seconds
Started Nov 22 12:27:40 PM PST 23
Finished Nov 22 12:28:11 PM PST 23
Peak memory 193772 kb
Host smart-9d1c706f-b1f2-4a83-8d8b-e6f1e6fb39cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94189401480650494227396305940170435064613042394249324910881519120470306735978 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stress.94189401480650494227396305940170435064613042394249324910881519120470306735978
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.67031781828851687000883624510024665370088364943240747855519711440487509695456
Short name T748
Test name
Test status
Simulation time 137439144 ps
CPU time 1.03 seconds
Started Nov 22 12:25:05 PM PST 23
Finished Nov 22 12:25:06 PM PST 23
Peak memory 196396 kb
Host smart-5a9456bf-d3d0-4b0c-b7fd-178dc0b2aa80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67031781828851687000883624510024665370088364943240747855519711440487509695456 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.67031781828851687000883624510024665370088364943240747855519711440487509695456
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.102321689937674352056030903096612688451001923215270474787186348215966359622862
Short name T569
Test name
Test status
Simulation time 119314289 ps
CPU time 1.18 seconds
Started Nov 22 12:26:42 PM PST 23
Finished Nov 22 12:26:44 PM PST 23
Peak memory 195748 kb
Host smart-7cf68346-86ae-4ce0-8aa0-ebc436f5101c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102321689937674352056030903096612688451001923215270474787186348215966359622862 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.102321689937674352056030903096612688451001923215270474787186348215966359622862
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.10778046281913085518810893030167121103643629487515919064248121855450171272606
Short name T229
Test name
Test status
Simulation time 228920555 ps
CPU time 3.05 seconds
Started Nov 22 12:25:25 PM PST 23
Finished Nov 22 12:25:29 PM PST 23
Peak memory 195740 kb
Host smart-c39a6fb3-73e2-4850-a4b9-fce12fa9812b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10778046281913085518810893030167121103643629487515919064248121855450171272606 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.10778046281913085518810893030167121103643629487515919064248121855450171272606
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.64224728025396651151219795390803797740502701663397128432177257428403931198404
Short name T616
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:28 PM PST 23
Peak memory 195684 kb
Host smart-9ab06a4b-5fd0-48f8-8821-31115465224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64224728025396651151219795390803797740502701663397128432177257428403931198404 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.gpio_random_dout_din.64224728025396651151219795390803797740502701663397128432177257428403931198404
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.39992274721704830323339562033745803092277448730304486004203182170893829552677
Short name T489
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:04 PM PST 23
Peak memory 194156 kb
Host smart-dd41e9c0-8c84-4a51-ac2c-66609e1c064d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992274721704830323339562033745803092277448730304486004203182170893829552677 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup_pulldown.39992274721704830323339562033745803092277448730304486004203182170893829552677
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.114336278796647858835065028779649024360367257016249148536150215779179448241442
Short name T452
Test name
Test status
Simulation time 572864232 ps
CPU time 5.36 seconds
Started Nov 22 12:26:08 PM PST 23
Finished Nov 22 12:26:16 PM PST 23
Peak memory 197712 kb
Host smart-924d91c6-6eca-4715-b814-fd96257718cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114336278796647858835065028779649024360367257016249148536150215779179448241442 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_long_reg_writes_reg_reads.11433627879664785883506502877964902436036725701
6249148536150215779179448241442
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.62203160717015892536151532358958896060325516778951189777422375277870799737323
Short name T534
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:21:11 PM PST 23
Finished Nov 22 12:21:13 PM PST 23
Peak memory 195412 kb
Host smart-297e4e5f-4ace-428a-8214-688903c4ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62203160717015892536151532358958896060325516778951189777422375277870799737323 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.gpio_smoke.62203160717015892536151532358958896060325516778951189777422375277870799737323
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.24043791113181681274883187115388192484403999899522764812027215779070487293835
Short name T712
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:05 PM PST 23
Peak memory 193872 kb
Host smart-a2981ed5-2f23-4465-8b6b-e73f07a497b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043791113181681274883187115388192484403999899522764812027215779070487293835 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.24043791113181681274883187115388192484403999899522764812027215779070487293835
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.28184312488585928720469283458401705333493667960860557076507182898426366124546
Short name T437
Test name
Test status
Simulation time 21104521406 ps
CPU time 159.84 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:28:54 PM PST 23
Peak memory 197128 kb
Host smart-5a7b4b94-3c9d-436b-9c4e-31020332694a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818431248858592872046928345840170533349366796086055707650718289
8426366124546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all.281843124885859287204692834584017053334936679608605570765071828
98426366124546
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.17154133954297381260507268067350089003752903716688779923713109168169370832919
Short name T470
Test name
Test status
Simulation time 133069054254 ps
CPU time 1116.04 seconds
Started Nov 22 12:26:44 PM PST 23
Finished Nov 22 12:45:22 PM PST 23
Peak memory 198164 kb
Host smart-539ccb29-ad5b-478d-b0e0-24924f0413ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=17154133954297381260507268067350089003752903716688779923713109168169370832919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_wi
th_rand_reset.17154133954297381260507268067350089003752903716688779923713109168169370832919
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.19593388107417191884950388625858163020227291090338425897835579789437561667249
Short name T487
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:16 PM PST 23
Peak memory 192980 kb
Host smart-5ee004a7-714e-4224-8450-8f21dc5b2646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19593388107417191884950388625858163020227291090338425897835579789437561667249 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.gpio_alert_test.19593388107417191884950388625858163020227291090338425897835579789437561667249
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.50161398105040031641423956016344739259819542000579678973566890569197445242503
Short name T873
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 195852 kb
Host smart-dd515419-d9b8-43e8-b45a-393fa68f5d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50161398105040031641423956016344739259819542000579678973566890569197445242503 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.50161398105040031641423956016344739259819542000579678973566890569197445242503
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.98285659864000183816830781770543016011013708581615462302711291435136095023478
Short name T220
Test name
Test status
Simulation time 1135699015 ps
CPU time 23.35 seconds
Started Nov 22 12:25:03 PM PST 23
Finished Nov 22 12:25:27 PM PST 23
Peak memory 195416 kb
Host smart-32641601-2577-424c-85a1-bdb48ff22035
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98285659864000183816830781770543016011013708581615462302711291435136095023478 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stress.98285659864000183816830781770543016011013708581615462302711291435136095023478
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.33831287320346441545549569755573668638787007360280530233731289120868125143951
Short name T855
Test name
Test status
Simulation time 137439144 ps
CPU time 0.92 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:17 PM PST 23
Peak memory 195880 kb
Host smart-e736a29e-1296-48d7-ac25-2b01b07af8c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33831287320346441545549569755573668638787007360280530233731289120868125143951 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.33831287320346441545549569755573668638787007360280530233731289120868125143951
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.25793262514640952740160839946047321212398803990558997379559382238847337050242
Short name T434
Test name
Test status
Simulation time 119314289 ps
CPU time 1.21 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 194788 kb
Host smart-51712cb9-b149-46f5-bbca-1e80fcf333a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25793262514640952740160839946047321212398803990558997379559382238847337050242 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.25793262514640952740160839946047321212398803990558997379559382238847337050242
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.32546657689790367523319488589490146402348954657164413220038136888966233371514
Short name T815
Test name
Test status
Simulation time 134635595 ps
CPU time 3.01 seconds
Started Nov 22 12:26:58 PM PST 23
Finished Nov 22 12:27:08 PM PST 23
Peak memory 196784 kb
Host smart-c1737a3f-3ab7-440f-8f1e-9bf43d010062
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546657689790367523319488589490146402348954657164413220038136888966
233371514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.32546657689790367523319
488589490146402348954657164413220038136888966233371514
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.88399919476224537082049415929055314079444381106249987799662326847520376368225
Short name T304
Test name
Test status
Simulation time 228920555 ps
CPU time 2.92 seconds
Started Nov 22 12:25:05 PM PST 23
Finished Nov 22 12:25:08 PM PST 23
Peak memory 195796 kb
Host smart-b15db4cb-dfa5-4d14-b987-efd5b619d2ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88399919476224537082049415929055314079444381106249987799662326847520376368225 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.88399919476224537082049415929055314079444381106249987799662326847520376368225
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.13640722683500225003650402010663654834186361660443571021654141268684788478997
Short name T272
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:27:37 PM PST 23
Finished Nov 22 12:27:48 PM PST 23
Peak memory 195716 kb
Host smart-795d203a-ed5c-4c2d-8f9e-1ad8e8281c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13640722683500225003650402010663654834186361660443571021654141268684788478997 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.gpio_random_dout_din.13640722683500225003650402010663654834186361660443571021654141268684788478997
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.44159428598803617658944590389783928286871040774369894967281294764068578856949
Short name T250
Test name
Test status
Simulation time 81278879 ps
CPU time 1.16 seconds
Started Nov 22 12:22:06 PM PST 23
Finished Nov 22 12:22:08 PM PST 23
Peak memory 195720 kb
Host smart-274e9cc3-5be6-4b9b-9fbb-945b840ca853
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44159428598803617658944590389783928286871040774369894967281294764068578856949 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_pulldown.44159428598803617658944590389783928286871040774369894967281294764068578856949
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.33719394031565103952785480980391039890170290504200071224268442548511778529117
Short name T377
Test name
Test status
Simulation time 572864232 ps
CPU time 5.28 seconds
Started Nov 22 12:21:31 PM PST 23
Finished Nov 22 12:21:37 PM PST 23
Peak memory 197676 kb
Host smart-9cf6f279-46aa-434a-8c1a-e24576ce8381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719394031565103952785480980391039890170290504200071224268442548511778529117 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_long_reg_writes_reg_reads.337193940315651039527854809803910398901702905042
00071224268442548511778529117
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.94314710180795148326204611633399531637288522436620615727043931217242408887772
Short name T359
Test name
Test status
Simulation time 112796484 ps
CPU time 1.3 seconds
Started Nov 22 12:26:43 PM PST 23
Finished Nov 22 12:26:46 PM PST 23
Peak memory 195496 kb
Host smart-9b662458-7ef9-4e44-83a4-dcb02c29171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94314710180795148326204611633399531637288522436620615727043931217242408887772 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.gpio_smoke.94314710180795148326204611633399531637288522436620615727043931217242408887772
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.31639557705528612820968615514930493245802907550998317624556051210119871939142
Short name T275
Test name
Test status
Simulation time 112796484 ps
CPU time 1.19 seconds
Started Nov 22 12:27:36 PM PST 23
Finished Nov 22 12:27:47 PM PST 23
Peak memory 195424 kb
Host smart-98d33702-4e7c-47eb-b4a6-f02b5cc2a0bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639557705528612820968615514930493245802907550998317624556051210119871939142 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.31639557705528612820968615514930493245802907550998317624556051210119871939142
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.49018258949461678272464863657841462568885535524045183383765727848587713169465
Short name T853
Test name
Test status
Simulation time 21104521406 ps
CPU time 160.19 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:29:59 PM PST 23
Peak memory 196852 kb
Host smart-22b01178-c6b8-4d3a-a7c6-8db66f096b0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4901825894946167827246486365784146256888553552404518338376572784
8587713169465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all.490182589494616782724648636578414625688855355240451833837657278
48587713169465
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.34408878871081792019096559529622834830848737540430280460512149324758036132199
Short name T848
Test name
Test status
Simulation time 133069054254 ps
CPU time 1060 seconds
Started Nov 22 12:26:58 PM PST 23
Finished Nov 22 12:44:44 PM PST 23
Peak memory 197376 kb
Host smart-84d02130-3c77-4fe7-93ae-b75184fa2741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=34408878871081792019096559529622834830848737540430280460512149324758036132199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_wi
th_rand_reset.34408878871081792019096559529622834830848737540430280460512149324758036132199
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.86781818956447787840116500451709663742728627285006923897126479783506105470570
Short name T877
Test name
Test status
Simulation time 22440064 ps
CPU time 0.58 seconds
Started Nov 22 12:22:14 PM PST 23
Finished Nov 22 12:22:15 PM PST 23
Peak memory 193820 kb
Host smart-969d0d9f-9dac-41ba-8fc1-395981b2882d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86781818956447787840116500451709663742728627285006923897126479783506105470570 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.gpio_alert_test.86781818956447787840116500451709663742728627285006923897126479783506105470570
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.51111480697010151634907169531273973135681402548001150028011510225554283584285
Short name T746
Test name
Test status
Simulation time 57921923 ps
CPU time 0.89 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 196164 kb
Host smart-85a3ca8c-53c2-4061-bf34-900aa7a09579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51111480697010151634907169531273973135681402548001150028011510225554283584285 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.51111480697010151634907169531273973135681402548001150028011510225554283584285
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.57691593098524030650502317498688770962073115077943763667100344386227814400711
Short name T726
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.63 seconds
Started Nov 22 12:21:34 PM PST 23
Finished Nov 22 12:21:57 PM PST 23
Peak memory 195400 kb
Host smart-d1587658-a0c4-442b-b9f1-eec987d7875e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57691593098524030650502317498688770962073115077943763667100344386227814400711 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stress.57691593098524030650502317498688770962073115077943763667100344386227814400711
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.33129277415147058751377996903310222998609581538285435249441035598496235365958
Short name T846
Test name
Test status
Simulation time 137439144 ps
CPU time 0.97 seconds
Started Nov 22 12:23:45 PM PST 23
Finished Nov 22 12:23:47 PM PST 23
Peak memory 196332 kb
Host smart-9e53d2b1-c091-4862-b8d2-cac9f91815db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129277415147058751377996903310222998609581538285435249441035598496235365958 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.33129277415147058751377996903310222998609581538285435249441035598496235365958
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.5840974794588730915036712348977392961212046290765150675677124963499777005044
Short name T606
Test name
Test status
Simulation time 119314289 ps
CPU time 1.11 seconds
Started Nov 22 12:27:24 PM PST 23
Finished Nov 22 12:27:34 PM PST 23
Peak memory 195676 kb
Host smart-72d1fde3-1cca-40f5-86de-e884baa8c577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5840974794588730915036712348977392961212046290765150675677124963499777005044 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.5840974794588730915036712348977392961212046290765150675677124963499777005044
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.6657085153995766201705524556621767861992173010175429976807201767130047291961
Short name T407
Test name
Test status
Simulation time 134635595 ps
CPU time 3.11 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 195496 kb
Host smart-02c027b1-f3be-4caa-a2ae-77f08de699cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66570851539957662017055245566217678619921730101754299768072017671300
47291961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.665708515399576620170552
4556621767861992173010175429976807201767130047291961
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.63353481373713529779598360547727617485960813690229499428526429358673727139726
Short name T251
Test name
Test status
Simulation time 228920555 ps
CPU time 2.73 seconds
Started Nov 22 12:25:53 PM PST 23
Finished Nov 22 12:25:57 PM PST 23
Peak memory 195288 kb
Host smart-f4bdb918-7741-4155-8ae8-fa8b9315f1d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63353481373713529779598360547727617485960813690229499428526429358673727139726 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.63353481373713529779598360547727617485960813690229499428526429358673727139726
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.56557797187325891480045929162141298098986566834440510141811574737600746268472
Short name T757
Test name
Test status
Simulation time 81278879 ps
CPU time 1.13 seconds
Started Nov 22 12:26:25 PM PST 23
Finished Nov 22 12:26:31 PM PST 23
Peak memory 195784 kb
Host smart-d5d747f3-9419-4b6f-b1f5-31dde6e94787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56557797187325891480045929162141298098986566834440510141811574737600746268472 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.gpio_random_dout_din.56557797187325891480045929162141298098986566834440510141811574737600746268472
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.12656563711758878369433457485633188429166949474790949975970108642468065521933
Short name T557
Test name
Test status
Simulation time 81278879 ps
CPU time 1.26 seconds
Started Nov 22 12:23:56 PM PST 23
Finished Nov 22 12:24:02 PM PST 23
Peak memory 195688 kb
Host smart-785277bf-b962-4563-9093-08fe49190c84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12656563711758878369433457485633188429166949474790949975970108642468065521933 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup_pulldown.12656563711758878369433457485633188429166949474790949975970108642468065521933
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.10238986594358940045083523448135179459253086012840165655938152043325804575820
Short name T714
Test name
Test status
Simulation time 572864232 ps
CPU time 5.2 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 197368 kb
Host smart-ea30ee23-250c-4bc7-91df-230ccf8a55f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238986594358940045083523448135179459253086012840165655938152043325804575820 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_long_reg_writes_reg_reads.102389865943589400450835234481351794592530860128
40165655938152043325804575820
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.113327395847446861815850723711001571300932163652730183580739643566476185519066
Short name T276
Test name
Test status
Simulation time 112796484 ps
CPU time 1.29 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 195444 kb
Host smart-3e61b745-4240-458f-8a29-ea9145822743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113327395847446861815850723711001571300932163652730183580739643566476185519066 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.gpio_smoke.113327395847446861815850723711001571300932163652730183580739643566476185519066
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.70414034932677186710236785919863132263283047868657978439251289226804123949455
Short name T847
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:26:11 PM PST 23
Finished Nov 22 12:26:13 PM PST 23
Peak memory 195432 kb
Host smart-f500d92f-660c-414d-9e2b-b40089a74342
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70414034932677186710236785919863132263283047868657978439251289226804123949455 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.70414034932677186710236785919863132263283047868657978439251289226804123949455
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.39698330627161746982962300578277441387583386852650549290260847938633394769202
Short name T857
Test name
Test status
Simulation time 21104521406 ps
CPU time 170.19 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:29:09 PM PST 23
Peak memory 197652 kb
Host smart-7af5c6aa-43bf-4e61-a968-e8a2696d5795
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969833062716174698296230057827744138758338685265054929026084793
8633394769202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all.396983306271617469829623005782774413875833868526505492902608479
38633394769202
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2528098631996057089218972024843816188105854415367009091765555625775880596435
Short name T524
Test name
Test status
Simulation time 133069054254 ps
CPU time 1133.79 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:45:14 PM PST 23
Peak memory 198188 kb
Host smart-3bec8770-a4b4-492f-ad71-eec6e660a686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2528098631996057089218972024843816188105854415367009091765555625775880596435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_wit
h_rand_reset.2528098631996057089218972024843816188105854415367009091765555625775880596435
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3341441974067832834960510050007226441907389471441891187831391317889001023986
Short name T327
Test name
Test status
Simulation time 22440064 ps
CPU time 0.57 seconds
Started Nov 22 12:25:34 PM PST 23
Finished Nov 22 12:25:40 PM PST 23
Peak memory 193824 kb
Host smart-84edd15f-9403-4e83-a4dc-18fb83afb1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341441974067832834960510050007226441907389471441891187831391317889001023986 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.gpio_alert_test.3341441974067832834960510050007226441907389471441891187831391317889001023986
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.51220722713682008571198716398808240584313573982222023975507806282644896144085
Short name T836
Test name
Test status
Simulation time 57921923 ps
CPU time 0.87 seconds
Started Nov 22 12:23:08 PM PST 23
Finished Nov 22 12:23:09 PM PST 23
Peak memory 196188 kb
Host smart-50c12ef3-9639-4cf3-8d99-a8c030a25207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51220722713682008571198716398808240584313573982222023975507806282644896144085 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.51220722713682008571198716398808240584313573982222023975507806282644896144085
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.97529679109808327409929945570908177624572519751999197390123349757826721411415
Short name T638
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.19 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:45 PM PST 23
Peak memory 195176 kb
Host smart-a296b2d9-c08d-4659-8c05-42371a4bc11c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97529679109808327409929945570908177624572519751999197390123349757826721411415 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stress.97529679109808327409929945570908177624572519751999197390123349757826721411415
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.66851408541694634101088133198917215359948350819809524764952793077938229189133
Short name T307
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:25:53 PM PST 23
Finished Nov 22 12:25:55 PM PST 23
Peak memory 195424 kb
Host smart-43d81027-d435-43c5-8cb8-dcbce5e868bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66851408541694634101088133198917215359948350819809524764952793077938229189133 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.66851408541694634101088133198917215359948350819809524764952793077938229189133
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.59338479412854968199343521352004775327580187460457242233754393336078048376137
Short name T706
Test name
Test status
Simulation time 119314289 ps
CPU time 1.15 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 195536 kb
Host smart-aaddeb86-07e7-42ca-9287-2ae3f15ae053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59338479412854968199343521352004775327580187460457242233754393336078048376137 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.59338479412854968199343521352004775327580187460457242233754393336078048376137
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.14718768821279399241269961615632144309022709250172132253601356273370840902464
Short name T669
Test name
Test status
Simulation time 134635595 ps
CPU time 2.81 seconds
Started Nov 22 12:26:06 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 197080 kb
Host smart-45ec3b37-1010-4607-8b94-970d12d1dc23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14718768821279399241269961615632144309022709250172132253601356273370
840902464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.14718768821279399241269
961615632144309022709250172132253601356273370840902464
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.65398837155604513138731452819258849953411383462375920403216255912398997393368
Short name T448
Test name
Test status
Simulation time 228920555 ps
CPU time 2.62 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 195708 kb
Host smart-e0f28efe-a0e4-46dd-8c02-3edf8ce700a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65398837155604513138731452819258849953411383462375920403216255912398997393368 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.65398837155604513138731452819258849953411383462375920403216255912398997393368
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.193699745768491410223505347136628924483857486653239921189138057530579079396
Short name T851
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:23:53 PM PST 23
Finished Nov 22 12:23:57 PM PST 23
Peak memory 195664 kb
Host smart-ec72150e-3dae-422a-86aa-4a00631936d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193699745768491410223505347136628924483857486653239921189138057530579079396 -assert nopostproc +UVM_TESTNAME=gpio_base_t
est +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.gpio_random_dout_din.193699745768491410223505347136628924483857486653239921189138057530579079396
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.9785588173363961765854943524553398664132269322861675979603769494769549406752
Short name T204
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:26:35 PM PST 23
Finished Nov 22 12:26:37 PM PST 23
Peak memory 195704 kb
Host smart-655f335f-e8d6-4720-9061-736f1d00f37b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9785588173363961765854943524553398664132269322861675979603769494769549406752 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup_pulldown.9785588173363961765854943524553398664132269322861675979603769494769549406752
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.9921464775456745885852816918261072244128625515721933450848960722250115961527
Short name T725
Test name
Test status
Simulation time 572864232 ps
CPU time 5 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 197288 kb
Host smart-388f7d02-59b7-4b3e-9d2e-8a07dd420282
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9921464775456745885852816918261072244128625515721933450848960722250115961527 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_long_reg_writes_reg_reads.9921464775456745885852816918261072244128625515721
933450848960722250115961527
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.78114145218180024784790893900945254204674483635152716692478683531593814939334
Short name T294
Test name
Test status
Simulation time 112796484 ps
CPU time 1.24 seconds
Started Nov 22 12:22:08 PM PST 23
Finished Nov 22 12:22:10 PM PST 23
Peak memory 195252 kb
Host smart-042bc049-c069-4238-9520-7ca11b383244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78114145218180024784790893900945254204674483635152716692478683531593814939334 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.gpio_smoke.78114145218180024784790893900945254204674483635152716692478683531593814939334
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.7560970588978635226047181385913533123218167111740228094853834942273405495248
Short name T717
Test name
Test status
Simulation time 112796484 ps
CPU time 1.24 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 195428 kb
Host smart-88c59e49-609c-4711-85c3-d4a4efe427d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7560970588978635226047181385913533123218167111740228094853834942273405495248 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.7560970588978635226047181385913533123218167111740228094853834942273405495248
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.14300600962123914714394323007217368362715453031558033511755763718063818512202
Short name T673
Test name
Test status
Simulation time 21104521406 ps
CPU time 172.99 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:29:19 PM PST 23
Peak memory 198012 kb
Host smart-c965a5f7-fc65-48d3-af95-886e5b83be10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430060096212391471439432300721736836271545303155803351175576371
8063818512202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all.143006009621239147143943230072173683627154530315580335117557637
18063818512202
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.87992547743178243944850912753996977418221061398717582834859866575079798938265
Short name T371
Test name
Test status
Simulation time 133069054254 ps
CPU time 1057.31 seconds
Started Nov 22 12:25:54 PM PST 23
Finished Nov 22 12:43:32 PM PST 23
Peak memory 197812 kb
Host smart-219d01af-9056-4d56-911d-c5c597c50494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=87992547743178243944850912753996977418221061398717582834859866575079798938265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_wi
th_rand_reset.87992547743178243944850912753996977418221061398717582834859866575079798938265
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.42398446366294877334583622589946997403291703595295675387837948888847787453282
Short name T514
Test name
Test status
Simulation time 22440064 ps
CPU time 0.58 seconds
Started Nov 22 12:22:19 PM PST 23
Finished Nov 22 12:22:21 PM PST 23
Peak memory 193372 kb
Host smart-4acf18d6-60ac-4483-b2b0-72663b6e9bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42398446366294877334583622589946997403291703595295675387837948888847787453282 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.gpio_alert_test.42398446366294877334583622589946997403291703595295675387837948888847787453282
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.39951117109746193923777977683553681718767357232212031168820782085546297112549
Short name T740
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 194788 kb
Host smart-5f84189b-7e29-499f-a7d5-6dc55f6f460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39951117109746193923777977683553681718767357232212031168820782085546297112549 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.39951117109746193923777977683553681718767357232212031168820782085546297112549
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.47809551545258170447519216388130963445060041629260569194063449350491030096146
Short name T546
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.23 seconds
Started Nov 22 12:26:22 PM PST 23
Finished Nov 22 12:26:50 PM PST 23
Peak memory 195412 kb
Host smart-3fc62223-1b85-4108-a4e7-22b017a18e81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47809551545258170447519216388130963445060041629260569194063449350491030096146 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress.47809551545258170447519216388130963445060041629260569194063449350491030096146
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.33122484396737569417733743298064382646184663869129220891967565080950604978025
Short name T775
Test name
Test status
Simulation time 137439144 ps
CPU time 0.96 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 195016 kb
Host smart-60e90053-06f3-4ef5-8ae1-5f2b7e1684f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33122484396737569417733743298064382646184663869129220891967565080950604978025 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.33122484396737569417733743298064382646184663869129220891967565080950604978025
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.15191967660599165005264792272283188141497165472653025599315555374935149732793
Short name T360
Test name
Test status
Simulation time 119314289 ps
CPU time 1.26 seconds
Started Nov 22 12:23:32 PM PST 23
Finished Nov 22 12:23:34 PM PST 23
Peak memory 195672 kb
Host smart-5b0e5b89-49e8-44df-9f17-efbe89180446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191967660599165005264792272283188141497165472653025599315555374935149732793 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.15191967660599165005264792272283188141497165472653025599315555374935149732793
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.83401488776456126090454860177740168654080969303904369571761732168077576366331
Short name T694
Test name
Test status
Simulation time 134635595 ps
CPU time 2.83 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 196712 kb
Host smart-3ff2346d-2cad-4f46-9cc8-6703bc5543a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83401488776456126090454860177740168654080969303904369571761732168077
576366331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.83401488776456126090454
860177740168654080969303904369571761732168077576366331
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.113791261938446738251529221785032266487334006674277547484897192279808015115322
Short name T702
Test name
Test status
Simulation time 228920555 ps
CPU time 2.71 seconds
Started Nov 22 12:24:56 PM PST 23
Finished Nov 22 12:24:59 PM PST 23
Peak memory 195640 kb
Host smart-8fc60651-ad34-4687-865e-7d487a45989b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113791261938446738251529221785032266487334006674277547484897192279808015115322 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.113791261938446738251529221785032266487334006674277547484897192279808015115322
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.94741364995826233495241425252385048654024631591918828756622906858974778153568
Short name T543
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:25:34 PM PST 23
Finished Nov 22 12:25:41 PM PST 23
Peak memory 195708 kb
Host smart-01b5d3e1-14be-4381-88f0-b19ec7cf2b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94741364995826233495241425252385048654024631591918828756622906858974778153568 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.gpio_random_dout_din.94741364995826233495241425252385048654024631591918828756622906858974778153568
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.92692677031873705504305565120900477978543984726587329709652174830761887203952
Short name T633
Test name
Test status
Simulation time 81278879 ps
CPU time 1.26 seconds
Started Nov 22 12:23:56 PM PST 23
Finished Nov 22 12:24:01 PM PST 23
Peak memory 195708 kb
Host smart-c2370402-22f5-4237-9f36-7cf6ee7c03dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92692677031873705504305565120900477978543984726587329709652174830761887203952 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup_pulldown.92692677031873705504305565120900477978543984726587329709652174830761887203952
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.58613790161685551571055593525678157595833296554759350235129909383060931353368
Short name T773
Test name
Test status
Simulation time 572864232 ps
CPU time 4.84 seconds
Started Nov 22 12:26:23 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 197360 kb
Host smart-38a9a4d5-0326-49f9-b129-4b213cb21077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58613790161685551571055593525678157595833296554759350235129909383060931353368 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_long_reg_writes_reg_reads.586137901616855515710555935256781575958332965547
59350235129909383060931353368
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.75328764886326013599519737685871286721086017920628814700430548422762615069541
Short name T226
Test name
Test status
Simulation time 112796484 ps
CPU time 1.3 seconds
Started Nov 22 12:24:45 PM PST 23
Finished Nov 22 12:24:47 PM PST 23
Peak memory 195448 kb
Host smart-ff20c7d2-5073-430c-ba8d-dc4a757c035a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75328764886326013599519737685871286721086017920628814700430548422762615069541 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.gpio_smoke.75328764886326013599519737685871286721086017920628814700430548422762615069541
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.97650038163679507647950964191331181227880784383155216521872289698568623133321
Short name T751
Test name
Test status
Simulation time 112796484 ps
CPU time 1.47 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:27 PM PST 23
Peak memory 192924 kb
Host smart-1fa0d76c-fca8-44ec-b3fc-f34ea46362b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97650038163679507647950964191331181227880784383155216521872289698568623133321 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.97650038163679507647950964191331181227880784383155216521872289698568623133321
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.34598059091330027654832720574756172668644696582457807990213313471674435628601
Short name T320
Test name
Test status
Simulation time 21104521406 ps
CPU time 160.62 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:29:06 PM PST 23
Peak memory 197572 kb
Host smart-00a680f6-e025-4ea4-b28f-aefea824f5a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459805909133002765483272057475617266864469658245780799021331347
1674435628601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all.345980590913300276548327205747561726686446965824578079902133134
71674435628601
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.319493807606904192467592962573468202688439902995525442201312493409330173239
Short name T521
Test name
Test status
Simulation time 133069054254 ps
CPU time 1110.84 seconds
Started Nov 22 12:26:23 PM PST 23
Finished Nov 22 12:45:00 PM PST 23
Peak memory 198172 kb
Host smart-0a53f34a-5e07-4892-9e78-e3dd39ab4c9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=319493807606904192467592962573468202688439902995525442201312493409330173239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with
_rand_reset.319493807606904192467592962573468202688439902995525442201312493409330173239
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2675119495527072465842264981434269103680458611035456394741165440014647328038
Short name T752
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:22:34 PM PST 23
Finished Nov 22 12:22:35 PM PST 23
Peak memory 193868 kb
Host smart-0892f3a9-e20d-45f3-9a5c-9ed7b336c45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675119495527072465842264981434269103680458611035456394741165440014647328038 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.gpio_alert_test.2675119495527072465842264981434269103680458611035456394741165440014647328038
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.99669184113032444371655609585854961143578424605835636695118609559500643234617
Short name T656
Test name
Test status
Simulation time 57921923 ps
CPU time 0.82 seconds
Started Nov 22 12:26:38 PM PST 23
Finished Nov 22 12:26:40 PM PST 23
Peak memory 196140 kb
Host smart-535ad234-6ad2-456a-88cc-3eb2af5f11b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99669184113032444371655609585854961143578424605835636695118609559500643234617 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.99669184113032444371655609585854961143578424605835636695118609559500643234617
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.110590676284356451970085336983774091419617931318410481838389383458535791931784
Short name T731
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.6 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:50 PM PST 23
Peak memory 195064 kb
Host smart-db4e215e-866a-4048-8129-57a317e67fc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110590676284356451970085336983774091419617931318410481838389383458535791931784 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stress.110590676284356451970085336983774091419617931318410481838389383458535791931784
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.16520023104174875622665833018088414480280496903013601278941666692634006223029
Short name T246
Test name
Test status
Simulation time 137439144 ps
CPU time 1.02 seconds
Started Nov 22 12:24:13 PM PST 23
Finished Nov 22 12:24:14 PM PST 23
Peak memory 196240 kb
Host smart-565e0b0b-676d-4c61-9844-5fdf1052c823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520023104174875622665833018088414480280496903013601278941666692634006223029 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.16520023104174875622665833018088414480280496903013601278941666692634006223029
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.110547289592155535663390049216684686040336287418088652399218782084519012687706
Short name T479
Test name
Test status
Simulation time 119314289 ps
CPU time 1.23 seconds
Started Nov 22 12:25:28 PM PST 23
Finished Nov 22 12:25:30 PM PST 23
Peak memory 195672 kb
Host smart-567fb7d2-46fc-41b6-af4f-6b699850d99f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110547289592155535663390049216684686040336287418088652399218782084519012687706 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.110547289592155535663390049216684686040336287418088652399218782084519012687706
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.63210791948828361146349953683649004220845747418477976765418921026388266869927
Short name T432
Test name
Test status
Simulation time 134635595 ps
CPU time 2.77 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:29 PM PST 23
Peak memory 196588 kb
Host smart-6e33b1e1-869c-4924-93d6-3d570e220b61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63210791948828361146349953683649004220845747418477976765418921026388
266869927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.63210791948828361146349
953683649004220845747418477976765418921026388266869927
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.67803903057358056979916867693889791571305413026082152070447310081265498181077
Short name T874
Test name
Test status
Simulation time 228920555 ps
CPU time 2.66 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:29 PM PST 23
Peak memory 195324 kb
Host smart-a327da8a-1141-4d1f-8072-2c9e6909e174
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67803903057358056979916867693889791571305413026082152070447310081265498181077 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.67803903057358056979916867693889791571305413026082152070447310081265498181077
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.14384595071948977839570037986919742168293222361718568534892978926235925406340
Short name T244
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:26:23 PM PST 23
Finished Nov 22 12:26:30 PM PST 23
Peak memory 195672 kb
Host smart-96f0886b-4732-48b9-a0dd-800d1eaf2c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14384595071948977839570037986919742168293222361718568534892978926235925406340 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.gpio_random_dout_din.14384595071948977839570037986919742168293222361718568534892978926235925406340
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.102819166560075331090441739609221294611202967692246440851301862389534855831243
Short name T764
Test name
Test status
Simulation time 81278879 ps
CPU time 1.19 seconds
Started Nov 22 12:26:05 PM PST 23
Finished Nov 22 12:26:08 PM PST 23
Peak memory 194832 kb
Host smart-8f0fbb55-2ae6-445a-98e6-aa0aaa4c15d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102819166560075331090441739609221294611202967692246440851301862389534855831243 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup_pulldown.102819166560075331090441739609221294611202967692246440851301862389534855831243
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.27484189006710927105860106312371159588835436320593277689910430755509323865922
Short name T749
Test name
Test status
Simulation time 572864232 ps
CPU time 5.13 seconds
Started Nov 22 12:24:17 PM PST 23
Finished Nov 22 12:24:23 PM PST 23
Peak memory 197712 kb
Host smart-32124cb9-1e7b-40d9-ab12-3e86fee017b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27484189006710927105860106312371159588835436320593277689910430755509323865922 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_long_reg_writes_reg_reads.274841890067109271058601063123711595888354363205
93277689910430755509323865922
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.93180810255710811436139619048423156027805382122541402155081388325554395858963
Short name T361
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 194512 kb
Host smart-cb20a32d-ee79-491e-9135-0cce82615af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93180810255710811436139619048423156027805382122541402155081388325554395858963 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.gpio_smoke.93180810255710811436139619048423156027805382122541402155081388325554395858963
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.27789807518464833399073658131777580988175219811319548384292966896533311383598
Short name T365
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:22:39 PM PST 23
Finished Nov 22 12:22:40 PM PST 23
Peak memory 195368 kb
Host smart-7b133fbc-51bc-415a-91bc-fb28925cf61d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789807518464833399073658131777580988175219811319548384292966896533311383598 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.27789807518464833399073658131777580988175219811319548384292966896533311383598
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.108676063057744411405399707402418191576518664809961093485477141600996825989459
Short name T75
Test name
Test status
Simulation time 21104521406 ps
CPU time 166.91 seconds
Started Nov 22 12:23:02 PM PST 23
Finished Nov 22 12:25:50 PM PST 23
Peak memory 197968 kb
Host smart-5c57ee52-c92e-42b8-8410-a3af2d8910ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086760630577444114053997074024181915765186648099610934854771416
00996825989459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all.10867606305774441140539970740241819157651866480996109348547714
1600996825989459
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.92407197670282551812756043757774673556267178351043754305632519393931638152685
Short name T795
Test name
Test status
Simulation time 133069054254 ps
CPU time 1065.36 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:44:11 PM PST 23
Peak memory 196172 kb
Host smart-fc6c15c7-2bc2-4a63-b478-184ef76f8df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=92407197670282551812756043757774673556267178351043754305632519393931638152685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_wi
th_rand_reset.92407197670282551812756043757774673556267178351043754305632519393931638152685
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.14140080471625409240668579235478143122082136783164415992941082704728158989475
Short name T566
Test name
Test status
Simulation time 22440064 ps
CPU time 0.6 seconds
Started Nov 22 12:21:48 PM PST 23
Finished Nov 22 12:21:49 PM PST 23
Peak memory 193932 kb
Host smart-ebcf03cb-e0ff-4a89-a2c3-e607a1ead4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140080471625409240668579235478143122082136783164415992941082704728158989475 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.gpio_alert_test.14140080471625409240668579235478143122082136783164415992941082704728158989475
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.67300264043696786911916988147835493644529404966516583909692722847828269982952
Short name T378
Test name
Test status
Simulation time 57921923 ps
CPU time 0.99 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 194152 kb
Host smart-49a28f72-d90a-4fd9-8ff5-9905e1ebdb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67300264043696786911916988147835493644529404966516583909692722847828269982952 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.67300264043696786911916988147835493644529404966516583909692722847828269982952
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.30251401959437475986244347973829858675061712614896997290333028754530479188993
Short name T588
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.01 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:32 PM PST 23
Peak memory 194360 kb
Host smart-5b9e0ad2-2ed9-4361-a076-80f91b89b521
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251401959437475986244347973829858675061712614896997290333028754530479188993 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stress.30251401959437475986244347973829858675061712614896997290333028754530479188993
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.79813532533662498549549355567482518652984881475550657286241590491404652387042
Short name T269
Test name
Test status
Simulation time 137439144 ps
CPU time 1.05 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:33 PM PST 23
Peak memory 194116 kb
Host smart-ab8bd4cf-bef4-4672-87cb-2af758fb97ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79813532533662498549549355567482518652984881475550657286241590491404652387042 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.79813532533662498549549355567482518652984881475550657286241590491404652387042
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.70728346827068601594112687464815696200128291831581114892639587310619367486013
Short name T429
Test name
Test status
Simulation time 119314289 ps
CPU time 1.22 seconds
Started Nov 22 12:26:08 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 194084 kb
Host smart-bafd61f1-d4a4-405c-a2e3-a8be648ccfe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70728346827068601594112687464815696200128291831581114892639587310619367486013 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.70728346827068601594112687464815696200128291831581114892639587310619367486013
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.80968310507367378797544527849960069619734779899924377423988597292980721269842
Short name T257
Test name
Test status
Simulation time 134635595 ps
CPU time 3.02 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:28 PM PST 23
Peak memory 195684 kb
Host smart-615fc1f5-fb2f-44aa-b613-e1495ddcc81f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80968310507367378797544527849960069619734779899924377423988597292980
721269842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.80968310507367378797544
527849960069619734779899924377423988597292980721269842
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.10393850205412903923121798478328229939448324670181819040230762419909992478268
Short name T813
Test name
Test status
Simulation time 228920555 ps
CPU time 2.8 seconds
Started Nov 22 12:21:39 PM PST 23
Finished Nov 22 12:21:42 PM PST 23
Peak memory 195668 kb
Host smart-fe2cbb89-6019-4b28-825e-062831906afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393850205412903923121798478328229939448324670181819040230762419909992478268 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.10393850205412903923121798478328229939448324670181819040230762419909992478268
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.32400099950793534121701173996698058825377800338248980189080382905964192718852
Short name T79
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:26:50 PM PST 23
Finished Nov 22 12:26:53 PM PST 23
Peak memory 195172 kb
Host smart-b95aa0e3-e7e2-421e-b5b8-a79e8d0ed37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32400099950793534121701173996698058825377800338248980189080382905964192718852 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.gpio_random_dout_din.32400099950793534121701173996698058825377800338248980189080382905964192718852
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.23448712704934855179125026493778051889337305517108141804176620849016196019155
Short name T688
Test name
Test status
Simulation time 81278879 ps
CPU time 1.06 seconds
Started Nov 22 12:26:22 PM PST 23
Finished Nov 22 12:26:29 PM PST 23
Peak memory 195352 kb
Host smart-530a2340-3d2d-4955-a0f5-092c9eaa2cad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448712704934855179125026493778051889337305517108141804176620849016196019155 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup_pulldown.23448712704934855179125026493778051889337305517108141804176620849016196019155
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.8624031304110388834132955983473558862235028974159890978525826160364031517998
Short name T464
Test name
Test status
Simulation time 572864232 ps
CPU time 5.27 seconds
Started Nov 22 12:21:39 PM PST 23
Finished Nov 22 12:21:45 PM PST 23
Peak memory 197684 kb
Host smart-3e2a0871-03a7-4bff-be9f-0a4125e9095b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8624031304110388834132955983473558862235028974159890978525826160364031517998 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_long_reg_writes_reg_reads.8624031304110388834132955983473558862235028974159
890978525826160364031517998
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.76001474886445122095872283881221311905833544383070273915282908322723706265742
Short name T790
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 195144 kb
Host smart-9baff7fb-c101-4ef5-8011-3ac631f2ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76001474886445122095872283881221311905833544383070273915282908322723706265742 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.gpio_smoke.76001474886445122095872283881221311905833544383070273915282908322723706265742
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.62157813542679843812644020419287339636336128715595570344922995997976045094130
Short name T203
Test name
Test status
Simulation time 112796484 ps
CPU time 1.35 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 192548 kb
Host smart-76ad82e3-d26d-423a-856a-28aa3e0c9add
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62157813542679843812644020419287339636336128715595570344922995997976045094130 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.62157813542679843812644020419287339636336128715595570344922995997976045094130
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.24378571448325133692804318205546257863241883793327897401604927851118513149720
Short name T589
Test name
Test status
Simulation time 21104521406 ps
CPU time 174.37 seconds
Started Nov 22 12:22:23 PM PST 23
Finished Nov 22 12:25:18 PM PST 23
Peak memory 197992 kb
Host smart-5efe936c-7d9c-47c6-8d6f-eca170a74977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437857144832513369280431820554625786324188379332789740160492785
1118513149720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all.243785714483251336928043182055462578632418837933278974016049278
51118513149720
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.58614394347949464905039200401116103539066318547134814797941749349087199850650
Short name T741
Test name
Test status
Simulation time 133069054254 ps
CPU time 1058.88 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:44:05 PM PST 23
Peak memory 197728 kb
Host smart-9c182783-490e-4894-966d-6c85ea74f9e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=58614394347949464905039200401116103539066318547134814797941749349087199850650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_wi
th_rand_reset.58614394347949464905039200401116103539066318547134814797941749349087199850650
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.39223447563512580340816534905777815692796136773002207953305719145638295148946
Short name T854
Test name
Test status
Simulation time 22440064 ps
CPU time 0.57 seconds
Started Nov 22 12:25:14 PM PST 23
Finished Nov 22 12:25:15 PM PST 23
Peak memory 193820 kb
Host smart-2567ae13-6dac-42f5-b23d-fc8f72c25594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39223447563512580340816534905777815692796136773002207953305719145638295148946 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.gpio_alert_test.39223447563512580340816534905777815692796136773002207953305719145638295148946
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.115667475133161010413278913611032667846596380532562894177849911114318596027303
Short name T221
Test name
Test status
Simulation time 57921923 ps
CPU time 0.92 seconds
Started Nov 22 12:20:49 PM PST 23
Finished Nov 22 12:20:51 PM PST 23
Peak memory 194988 kb
Host smart-201c5260-ad33-4e66-849f-c1e70db403e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115667475133161010413278913611032667846596380532562894177849911114318596027303 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.115667475133161010413278913611032667846596380532562894177849911114318596027303
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.30305212903864136502190218181628673877293390236052323505630212633375914393332
Short name T771
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.72 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 195104 kb
Host smart-ed640ec4-a3ee-401a-8b9a-67689106150f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30305212903864136502190218181628673877293390236052323505630212633375914393332 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress.30305212903864136502190218181628673877293390236052323505630212633375914393332
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.11998418990066263414740093262215621881668250592658024912972010321273413287049
Short name T446
Test name
Test status
Simulation time 119314289 ps
CPU time 1.22 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 193928 kb
Host smart-b7c4ca73-49fe-4a1d-8bcf-0d69fde3014d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11998418990066263414740093262215621881668250592658024912972010321273413287049 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.11998418990066263414740093262215621881668250592658024912972010321273413287049
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.61511435668884695824487958047597845431237620790412197029394566361305338022898
Short name T765
Test name
Test status
Simulation time 134635595 ps
CPU time 2.99 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:26:08 PM PST 23
Peak memory 196156 kb
Host smart-daee3363-10fe-4ae4-911e-786094b961b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61511435668884695824487958047597845431237620790412197029394566361305
338022898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.615114356688846958244879
58047597845431237620790412197029394566361305338022898
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.61577142719803993619380677340319361392173266198339422719935827777451527998453
Short name T801
Test name
Test status
Simulation time 228920555 ps
CPU time 2.79 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:03 PM PST 23
Peak memory 193552 kb
Host smart-1bc676fa-740d-4f20-aade-8564c5f758c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61577142719803993619380677340319361392173266198339422719935827777451527998453 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.61577142719803993619380677340319361392173266198339422719935827777451527998453
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.13940749936265530766808493097217512447859813351942310170698671473472082007730
Short name T367
Test name
Test status
Simulation time 81278879 ps
CPU time 1.16 seconds
Started Nov 22 12:22:42 PM PST 23
Finished Nov 22 12:22:44 PM PST 23
Peak memory 195656 kb
Host smart-da6f751b-535f-4c22-a75f-6555cb1a7da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13940749936265530766808493097217512447859813351942310170698671473472082007730 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.gpio_random_dout_din.13940749936265530766808493097217512447859813351942310170698671473472082007730
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.26428607854276934219406834340637903928291610549341823552152229497397144856829
Short name T348
Test name
Test status
Simulation time 81278879 ps
CPU time 1.09 seconds
Started Nov 22 12:23:29 PM PST 23
Finished Nov 22 12:23:30 PM PST 23
Peak memory 195760 kb
Host smart-e8c40dd0-2513-4518-b26a-fe0379f562db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26428607854276934219406834340637903928291610549341823552152229497397144856829 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_pulldown.26428607854276934219406834340637903928291610549341823552152229497397144856829
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.7558227039549315349319757202242338266217890277514819969401053421349715178161
Short name T458
Test name
Test status
Simulation time 572864232 ps
CPU time 4.85 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:11 PM PST 23
Peak memory 197424 kb
Host smart-a5be78d3-29d2-44c5-9679-ad52fc1cfd51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7558227039549315349319757202242338266217890277514819969401053421349715178161 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_long_reg_writes_reg_reads.75582270395493153493197572022423382662178902775148
19969401053421349715178161
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.31232975361745512820390244764892313912145384781915677916450721776900158707505
Short name T53
Test name
Test status
Simulation time 134885593 ps
CPU time 0.97 seconds
Started Nov 22 12:21:44 PM PST 23
Finished Nov 22 12:21:46 PM PST 23
Peak memory 214928 kb
Host smart-a276629d-3a02-489a-a815-589c172f9235
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31232975361745512820390244764892313912145384781915677916450721776900158707505 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.gpio_sec_cm.31232975361745512820390244764892313912145384781915677916450721776900158707505
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.54579537084567456934869867923450917802961302377278052235499199305871009736648
Short name T331
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:07 PM PST 23
Peak memory 195452 kb
Host smart-3c7492e8-6a0b-4b00-a328-93c6a99f456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54579537084567456934869867923450917802961302377278052235499199305871009736648 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.gpio_smoke.54579537084567456934869867923450917802961302377278052235499199305871009736648
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.9416309021921050546731347967708884455414941748109037589243738628018525549121
Short name T231
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:20:34 PM PST 23
Finished Nov 22 12:20:36 PM PST 23
Peak memory 195040 kb
Host smart-0be84388-5dcb-4297-b2fc-e0a3ff33ee40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9416309021921050546731347967708884455414941748109037589243738628018525549121 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.9416309021921050546731347967708884455414941748109037589243738628018525549121
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.87537283413731319714226719060546938102247275138378220973154125842355873287841
Short name T654
Test name
Test status
Simulation time 21104521406 ps
CPU time 172.6 seconds
Started Nov 22 12:24:29 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 197948 kb
Host smart-5a357ecc-9024-4e3b-b55d-5bc814b8db5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8753728341373131971422671906054693810224727513837822097315412584
2355873287841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all.8753728341373131971422671906054693810224727513837822097315412584
2355873287841
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.86018764116572827766900224653057545109966826705103860469056177987572832848032
Short name T302
Test name
Test status
Simulation time 133069054254 ps
CPU time 1108.6 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:45:43 PM PST 23
Peak memory 196496 kb
Host smart-7b029e87-443d-474d-80c8-10a55f9b3436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=86018764116572827766900224653057545109966826705103860469056177987572832848032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_wit
h_rand_reset.86018764116572827766900224653057545109966826705103860469056177987572832848032
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.24503708494819182231086027511992938408916933346764971138140721723113198133226
Short name T526
Test name
Test status
Simulation time 22440064 ps
CPU time 0.61 seconds
Started Nov 22 12:27:25 PM PST 23
Finished Nov 22 12:27:35 PM PST 23
Peak memory 192920 kb
Host smart-891921d6-6a62-4328-ac0e-16bbbfdf37e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503708494819182231086027511992938408916933346764971138140721723113198133226 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.gpio_alert_test.24503708494819182231086027511992938408916933346764971138140721723113198133226
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.85984067437331933953252829438957663635134944351739127448402988099703003685968
Short name T344
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:25:53 PM PST 23
Finished Nov 22 12:25:55 PM PST 23
Peak memory 196236 kb
Host smart-8248f329-de35-4139-b8fe-c05e23a86788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85984067437331933953252829438957663635134944351739127448402988099703003685968 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.85984067437331933953252829438957663635134944351739127448402988099703003685968
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1649990904587645155672419027341115323827117655897770028148880724758645618928
Short name T264
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.49 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:33 PM PST 23
Peak memory 194000 kb
Host smart-74420870-7441-4011-9593-4458258d4f36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649990904587645155672419027341115323827117655897770028148880724758645618928 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stress.1649990904587645155672419027341115323827117655897770028148880724758645618928
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3688397901420686228576396757492517698052313571271007389480732182900919863969
Short name T330
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:23:49 PM PST 23
Finished Nov 22 12:23:57 PM PST 23
Peak memory 196332 kb
Host smart-47419baf-33f8-4804-b100-ef0c90237387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688397901420686228576396757492517698052313571271007389480732182900919863969 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3688397901420686228576396757492517698052313571271007389480732182900919863969
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.54775877164538614805130119571757886345629896578150823004233248041515720788729
Short name T303
Test name
Test status
Simulation time 119314289 ps
CPU time 1.25 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:33 PM PST 23
Peak memory 193516 kb
Host smart-bd4332af-a79e-47e6-84e3-61f566a515b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54775877164538614805130119571757886345629896578150823004233248041515720788729 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.54775877164538614805130119571757886345629896578150823004233248041515720788729
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.75766867670382500894851232067082614729428841341602695933111686157275856944111
Short name T540
Test name
Test status
Simulation time 134635595 ps
CPU time 2.96 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:13 PM PST 23
Peak memory 195332 kb
Host smart-071419f6-b87a-475e-97c9-a8b23037d1ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75766867670382500894851232067082614729428841341602695933111686157275
856944111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.75766867670382500894851
232067082614729428841341602695933111686157275856944111
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.102620200357461965164679869896975105690534134339648328674728080161021556091781
Short name T686
Test name
Test status
Simulation time 228920555 ps
CPU time 2.64 seconds
Started Nov 22 12:26:54 PM PST 23
Finished Nov 22 12:27:01 PM PST 23
Peak memory 195716 kb
Host smart-5524a14d-1486-4c9c-9555-509e6d73fd4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102620200357461965164679869896975105690534134339648328674728080161021556091781 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.102620200357461965164679869896975105690534134339648328674728080161021556091781
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.20263548278692227087846963063223764071431752332138291675476739239780951445362
Short name T875
Test name
Test status
Simulation time 81278879 ps
CPU time 1.18 seconds
Started Nov 22 12:22:42 PM PST 23
Finished Nov 22 12:22:44 PM PST 23
Peak memory 195600 kb
Host smart-daacf43a-182a-456e-9c28-9dc715dec37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20263548278692227087846963063223764071431752332138291675476739239780951445362 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.gpio_random_dout_din.20263548278692227087846963063223764071431752332138291675476739239780951445362
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.32668270289433695963556821386333987123217510619061508234840493444756415630767
Short name T299
Test name
Test status
Simulation time 81278879 ps
CPU time 1.2 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 194152 kb
Host smart-a0fdcf9a-0d94-41c4-a064-88a9f3f66d60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32668270289433695963556821386333987123217510619061508234840493444756415630767 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup_pulldown.32668270289433695963556821386333987123217510619061508234840493444756415630767
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.51853633464852283398133244194852919473749758000825612936242623916032625056192
Short name T262
Test name
Test status
Simulation time 572864232 ps
CPU time 5.05 seconds
Started Nov 22 12:27:21 PM PST 23
Finished Nov 22 12:27:31 PM PST 23
Peak memory 197604 kb
Host smart-a741a116-3c03-484d-951a-96bd679ac5ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51853633464852283398133244194852919473749758000825612936242623916032625056192 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_long_reg_writes_reg_reads.518536334648522833981332441948529194737497580008
25612936242623916032625056192
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.57240786321913518403786377652402604312554257545964252459815354469047747954679
Short name T730
Test name
Test status
Simulation time 112796484 ps
CPU time 1.39 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:12 PM PST 23
Peak memory 193804 kb
Host smart-f7a43bb7-9cc2-4816-936f-7708974f2fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57240786321913518403786377652402604312554257545964252459815354469047747954679 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.gpio_smoke.57240786321913518403786377652402604312554257545964252459815354469047747954679
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.51183700544994681991142583588466001540245606122599390833112708319970069289253
Short name T338
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:27:47 PM PST 23
Finished Nov 22 12:27:54 PM PST 23
Peak memory 195428 kb
Host smart-b3611157-0e3a-45d5-b46c-141ff8138729
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51183700544994681991142583588466001540245606122599390833112708319970069289253 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.51183700544994681991142583588466001540245606122599390833112708319970069289253
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.106419841155252384856979975353848203058867532512496623071756560379557542879279
Short name T375
Test name
Test status
Simulation time 21104521406 ps
CPU time 165.89 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:30:07 PM PST 23
Peak memory 197600 kb
Host smart-f38bfea9-e5c9-4b2a-9187-2328a6f743b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064198411552523848569799753538482030588675325124966230717565603
79557542879279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all.10641984115525238485697997535384820305886753251249662307175656
0379557542879279
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.6831492173504172812659148637810198170730946667157161833537380408819407447582
Short name T734
Test name
Test status
Simulation time 133069054254 ps
CPU time 1080.35 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:45:23 PM PST 23
Peak memory 197760 kb
Host smart-0909a13d-356e-470f-a753-99050bac662d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=6831492173504172812659148637810198170730946667157161833537380408819407447582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_wit
h_rand_reset.6831492173504172812659148637810198170730946667157161833537380408819407447582
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.103400756386987380282989306820991467546154221838785906202754171599440616234144
Short name T328
Test name
Test status
Simulation time 22440064 ps
CPU time 0.59 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 193460 kb
Host smart-b1a6278d-fc5e-4f61-afa6-a0f6aab1a4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103400756386987380282989306820991467546154221838785906202754171599440616234144 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.103400756386987380282989306820991467546154221838785906202754171599440616234144
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.33993945324385911616391917240045136508659820602251808482196120720276122468741
Short name T235
Test name
Test status
Simulation time 57921923 ps
CPU time 0.83 seconds
Started Nov 22 12:24:16 PM PST 23
Finished Nov 22 12:24:18 PM PST 23
Peak memory 196196 kb
Host smart-38f0fe40-64ba-4522-ba4a-4a75b2ec502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33993945324385911616391917240045136508659820602251808482196120720276122468741 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.33993945324385911616391917240045136508659820602251808482196120720276122468741
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.64533404838413186872565635372007024773455393210367562104108901518891130267056
Short name T280
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.91 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:47 PM PST 23
Peak memory 195008 kb
Host smart-ca148552-b1e4-4505-a48d-954a1afd55b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64533404838413186872565635372007024773455393210367562104108901518891130267056 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stress.64533404838413186872565635372007024773455393210367562104108901518891130267056
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.47092027837015454291812979579299406347149495605089135743189896504763522763748
Short name T639
Test name
Test status
Simulation time 137439144 ps
CPU time 0.96 seconds
Started Nov 22 12:26:12 PM PST 23
Finished Nov 22 12:26:13 PM PST 23
Peak memory 196256 kb
Host smart-249f50f9-1d9f-428a-91cf-e9f28eb506a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47092027837015454291812979579299406347149495605089135743189896504763522763748 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.47092027837015454291812979579299406347149495605089135743189896504763522763748
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.64213469160296217081049012696759341873125895783870608716047973291498510652931
Short name T488
Test name
Test status
Simulation time 119314289 ps
CPU time 1.29 seconds
Started Nov 22 12:25:02 PM PST 23
Finished Nov 22 12:25:04 PM PST 23
Peak memory 195672 kb
Host smart-378abcff-cf76-4a98-903c-6f79f303c674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64213469160296217081049012696759341873125895783870608716047973291498510652931 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.64213469160296217081049012696759341873125895783870608716047973291498510652931
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.23329291995477540409275418670546358713568442377698581539674456478730565819728
Short name T387
Test name
Test status
Simulation time 134635595 ps
CPU time 2.98 seconds
Started Nov 22 12:22:25 PM PST 23
Finished Nov 22 12:22:29 PM PST 23
Peak memory 197092 kb
Host smart-4a2a570a-e042-465f-98b5-31641b0a681f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23329291995477540409275418670546358713568442377698581539674456478730
565819728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.23329291995477540409275
418670546358713568442377698581539674456478730565819728
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.110558907561608743667139248636592800536585709003370644187353639583758339846074
Short name T353
Test name
Test status
Simulation time 228920555 ps
CPU time 2.79 seconds
Started Nov 22 12:22:09 PM PST 23
Finished Nov 22 12:22:13 PM PST 23
Peak memory 195628 kb
Host smart-e572a382-1e37-40fe-8a42-fe602062e6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110558907561608743667139248636592800536585709003370644187353639583758339846074 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.110558907561608743667139248636592800536585709003370644187353639583758339846074
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.13107531306495044978198010379745121392994543492617073522792806169116488943223
Short name T834
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 194684 kb
Host smart-87ce541b-0614-45c3-99f4-3c10d92ac018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13107531306495044978198010379745121392994543492617073522792806169116488943223 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.gpio_random_dout_din.13107531306495044978198010379745121392994543492617073522792806169116488943223
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.62799995953916392186179779452794398979635852111176951648910682109810796442629
Short name T629
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:27:17 PM PST 23
Finished Nov 22 12:27:25 PM PST 23
Peak memory 195292 kb
Host smart-1ce13a9d-03d3-4b94-910d-3e85f636a465
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62799995953916392186179779452794398979635852111176951648910682109810796442629 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup_pulldown.62799995953916392186179779452794398979635852111176951648910682109810796442629
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.81246643584886815436925387301782778041199078162843466594507363206500535718559
Short name T719
Test name
Test status
Simulation time 572864232 ps
CPU time 4.76 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:24 PM PST 23
Peak memory 196856 kb
Host smart-de7d1206-03e9-44f0-abb9-9e64cf1dbc83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81246643584886815436925387301782778041199078162843466594507363206500535718559 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_long_reg_writes_reg_reads.812466435848868154369253873017827780411990781628
43466594507363206500535718559
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.108382907939356219904611593805825603092846976707352454084566938628844341070324
Short name T284
Test name
Test status
Simulation time 112796484 ps
CPU time 1.2 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:41 PM PST 23
Peak memory 195452 kb
Host smart-e74e6546-9451-4530-9282-7c71c8cfb250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108382907939356219904611593805825603092846976707352454084566938628844341070324 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.gpio_smoke.108382907939356219904611593805825603092846976707352454084566938628844341070324
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.70095331675412433710606032565340230446533329460461546824830326644985691715398
Short name T212
Test name
Test status
Simulation time 112796484 ps
CPU time 1.35 seconds
Started Nov 22 12:25:23 PM PST 23
Finished Nov 22 12:25:25 PM PST 23
Peak memory 195448 kb
Host smart-f1cf9a22-a51b-4156-8c80-702a7f94084c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70095331675412433710606032565340230446533329460461546824830326644985691715398 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.70095331675412433710606032565340230446533329460461546824830326644985691715398
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.51229746099179204956547822224006575124229827781942528310068237339303747010177
Short name T644
Test name
Test status
Simulation time 21104521406 ps
CPU time 177.5 seconds
Started Nov 22 12:21:52 PM PST 23
Finished Nov 22 12:24:50 PM PST 23
Peak memory 197992 kb
Host smart-aa7098a8-6800-49aa-a44e-83fa085640e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5122974609917920495654782222400657512422982778194252831006823733
9303747010177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all.512297460991792049565478222240065751242298277819425283100682373
39303747010177
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.16704115891296496647534063339979290977373489284806160468506147213269899638065
Short name T18
Test name
Test status
Simulation time 133069054254 ps
CPU time 1053.73 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:43:38 PM PST 23
Peak memory 196140 kb
Host smart-0fe009c0-9f05-4f54-8ac3-2b4c89adf8bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=16704115891296496647534063339979290977373489284806160468506147213269899638065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_wi
th_rand_reset.16704115891296496647534063339979290977373489284806160468506147213269899638065
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.92869376191842447422921332232003207676293079976860249108746662312351554502908
Short name T319
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:23:28 PM PST 23
Finished Nov 22 12:23:29 PM PST 23
Peak memory 193892 kb
Host smart-f2fa7422-2f07-47ff-bf7f-1c3794d57dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92869376191842447422921332232003207676293079976860249108746662312351554502908 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.gpio_alert_test.92869376191842447422921332232003207676293079976860249108746662312351554502908
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.114351907917459709498629090712665050774280783731765368509469358565372439003390
Short name T839
Test name
Test status
Simulation time 57921923 ps
CPU time 0.95 seconds
Started Nov 22 12:26:31 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 193700 kb
Host smart-c306746e-b776-4608-b145-2132a3f45c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114351907917459709498629090712665050774280783731765368509469358565372439003390 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.114351907917459709498629090712665050774280783731765368509469358565372439003390
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.39741501607180261481127470750180639126749772432611080598541300493992470421988
Short name T780
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.34 seconds
Started Nov 22 12:26:27 PM PST 23
Finished Nov 22 12:26:52 PM PST 23
Peak memory 195300 kb
Host smart-fb632854-f2f5-4331-9a7c-968617ef777c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39741501607180261481127470750180639126749772432611080598541300493992470421988 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stress.39741501607180261481127470750180639126749772432611080598541300493992470421988
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.90046748296000438224246446135105476312672802144682195250688124490245307294387
Short name T817
Test name
Test status
Simulation time 137439144 ps
CPU time 0.93 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:05 PM PST 23
Peak memory 196016 kb
Host smart-d9be1aa5-b9d9-4234-acd4-1dcb3d053772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90046748296000438224246446135105476312672802144682195250688124490245307294387 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.90046748296000438224246446135105476312672802144682195250688124490245307294387
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.111426244698028259023868854143455028440529607418130164386636346686794686570218
Short name T259
Test name
Test status
Simulation time 119314289 ps
CPU time 1.23 seconds
Started Nov 22 12:26:51 PM PST 23
Finished Nov 22 12:26:54 PM PST 23
Peak memory 195544 kb
Host smart-3414e83f-577b-4d01-adfd-536d96c729a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111426244698028259023868854143455028440529607418130164386636346686794686570218 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.111426244698028259023868854143455028440529607418130164386636346686794686570218
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.11249759775620496287176002365506242023493668076340356998831102496264194578055
Short name T651
Test name
Test status
Simulation time 134635595 ps
CPU time 2.92 seconds
Started Nov 22 12:24:42 PM PST 23
Finished Nov 22 12:24:45 PM PST 23
Peak memory 197116 kb
Host smart-5acc5743-b38d-403c-a23e-ec71d6297545
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249759775620496287176002365506242023493668076340356998831102496264
194578055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.11249759775620496287176
002365506242023493668076340356998831102496264194578055
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.82003172127111348811345294564575102222602315284605852415243303751759136047061
Short name T576
Test name
Test status
Simulation time 228920555 ps
CPU time 2.81 seconds
Started Nov 22 12:26:48 PM PST 23
Finished Nov 22 12:26:52 PM PST 23
Peak memory 194812 kb
Host smart-20b8f9ef-7b92-4df8-b823-0d37c7d69240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82003172127111348811345294564575102222602315284605852415243303751759136047061 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.82003172127111348811345294564575102222602315284605852415243303751759136047061
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.18810497828073739352442017510989562696885204856878014815434574023499440044365
Short name T356
Test name
Test status
Simulation time 81278879 ps
CPU time 1.09 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:07 PM PST 23
Peak memory 195396 kb
Host smart-e4d2ea5d-0585-4c57-9477-4fb0b5404778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18810497828073739352442017510989562696885204856878014815434574023499440044365 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.gpio_random_dout_din.18810497828073739352442017510989562696885204856878014815434574023499440044365
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.25690095716961788290787384665306630752145389209143745382773309095353654180329
Short name T553
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:09 PM PST 23
Peak memory 195672 kb
Host smart-520b3870-d718-44ae-a3c4-37cd08ba4553
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690095716961788290787384665306630752145389209143745382773309095353654180329 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup_pulldown.25690095716961788290787384665306630752145389209143745382773309095353654180329
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.84834940632432552941921746967827114496088676094093703704145050489407864078227
Short name T671
Test name
Test status
Simulation time 572864232 ps
CPU time 5.09 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 195444 kb
Host smart-f94f1ff7-e965-4873-939d-e4b63b9dc4d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84834940632432552941921746967827114496088676094093703704145050489407864078227 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_long_reg_writes_reg_reads.848349406324325529419217469678271144960886760940
93703704145050489407864078227
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.8050725981343285223916391899316761773566051108753266707002908058810595102165
Short name T426
Test name
Test status
Simulation time 112796484 ps
CPU time 1.3 seconds
Started Nov 22 12:26:32 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 194980 kb
Host smart-fe40a02b-77d8-40d5-8c52-f8d4aef93eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8050725981343285223916391899316761773566051108753266707002908058810595102165 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.gpio_smoke.8050725981343285223916391899316761773566051108753266707002908058810595102165
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.95117660893934343962147996875468057852354894800987385131695357291494533316737
Short name T592
Test name
Test status
Simulation time 112796484 ps
CPU time 1.21 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 195428 kb
Host smart-e36c0a80-7bfb-4702-84bf-a40d7cb7e088
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95117660893934343962147996875468057852354894800987385131695357291494533316737 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.95117660893934343962147996875468057852354894800987385131695357291494533316737
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.115659892930692657419094262350970734254986724567886183109152836324096647287191
Short name T745
Test name
Test status
Simulation time 21104521406 ps
CPU time 154.05 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:29:01 PM PST 23
Peak memory 197744 kb
Host smart-39307163-d0d6-4069-8de0-ef136f2b621b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156598929306926574190942623509707342549867245678861831091528363
24096647287191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all.11565989293069265741909426235097073425498672456788618310915283
6324096647287191
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.29257330457467378102231544759334962881216243665879277834644989762104735870614
Short name T30
Test name
Test status
Simulation time 133069054254 ps
CPU time 1083.07 seconds
Started Nov 22 12:22:36 PM PST 23
Finished Nov 22 12:40:40 PM PST 23
Peak memory 198308 kb
Host smart-9dac428d-39dc-4737-9b54-ca54e9ea0540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=29257330457467378102231544759334962881216243665879277834644989762104735870614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_wi
th_rand_reset.29257330457467378102231544759334962881216243665879277834644989762104735870614
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.110395511521424974207952871563302050382306992729523071462641576785358911048984
Short name T424
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:27:08 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 193824 kb
Host smart-b231ce98-2b27-4508-9411-98003da4db16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110395511521424974207952871563302050382306992729523071462641576785358911048984 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.110395511521424974207952871563302050382306992729523071462641576785358911048984
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.61809439664235029713001930651942584652227548464765136134781556655818786662705
Short name T721
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:27:02 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 196012 kb
Host smart-514fc44d-3637-47c6-bece-3efc2138b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61809439664235029713001930651942584652227548464765136134781556655818786662705 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.61809439664235029713001930651942584652227548464765136134781556655818786662705
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.112919605146692826219133550227001581099794115671117551836585213320275970729329
Short name T545
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.22 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 194564 kb
Host smart-03479b98-1dec-42ea-8186-f8aa1d4bca61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112919605146692826219133550227001581099794115671117551836585213320275970729329 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stress.112919605146692826219133550227001581099794115671117551836585213320275970729329
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.14569188604998886143118488236575397293779162868846781373389807234646900533319
Short name T419
Test name
Test status
Simulation time 137439144 ps
CPU time 1.01 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:26:06 PM PST 23
Peak memory 193812 kb
Host smart-83fc53f1-ceea-4d82-9e06-27c2d7cd4877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14569188604998886143118488236575397293779162868846781373389807234646900533319 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.14569188604998886143118488236575397293779162868846781373389807234646900533319
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.98068325250916353697043186557298176954912963483125533883374430171351066470181
Short name T416
Test name
Test status
Simulation time 119314289 ps
CPU time 1.16 seconds
Started Nov 22 12:26:50 PM PST 23
Finished Nov 22 12:26:52 PM PST 23
Peak memory 195408 kb
Host smart-d46802ef-84b5-4701-853f-ec72af09b71f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98068325250916353697043186557298176954912963483125533883374430171351066470181 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.98068325250916353697043186557298176954912963483125533883374430171351066470181
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.28785179868781588313599835507950165380375781352315671078914257678701730300407
Short name T871
Test name
Test status
Simulation time 134635595 ps
CPU time 2.95 seconds
Started Nov 22 12:25:31 PM PST 23
Finished Nov 22 12:25:35 PM PST 23
Peak memory 197052 kb
Host smart-6ea0c432-7c6b-44ab-a3a3-7e6e419eece6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28785179868781588313599835507950165380375781352315671078914257678701
730300407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.28785179868781588313599
835507950165380375781352315671078914257678701730300407
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.72890710312643344143005924000338089766067030022238170687618525182889736162737
Short name T234
Test name
Test status
Simulation time 228920555 ps
CPU time 2.74 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:11 PM PST 23
Peak memory 195676 kb
Host smart-ba12a1b4-eb1e-487e-910d-ff3b75abcd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72890710312643344143005924000338089766067030022238170687618525182889736162737 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.72890710312643344143005924000338089766067030022238170687618525182889736162737
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.32210513982417229135405798314607002678807251781951007606317954547575390341355
Short name T362
Test name
Test status
Simulation time 81278879 ps
CPU time 1.21 seconds
Started Nov 22 12:26:31 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 193748 kb
Host smart-ed010820-139d-4ea3-b810-587dabc3cd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32210513982417229135405798314607002678807251781951007606317954547575390341355 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.gpio_random_dout_din.32210513982417229135405798314607002678807251781951007606317954547575390341355
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.30629844031189777849777019392505245560986883845783563057476900139358378509183
Short name T263
Test name
Test status
Simulation time 81278879 ps
CPU time 1.28 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 194824 kb
Host smart-82108c58-cf74-4c2d-9648-863404560c28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30629844031189777849777019392505245560986883845783563057476900139358378509183 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup_pulldown.30629844031189777849777019392505245560986883845783563057476900139358378509183
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.68749782880528955181607806461111431723389512487969349011330521634023359147389
Short name T698
Test name
Test status
Simulation time 572864232 ps
CPU time 5.08 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:57 PM PST 23
Peak memory 197776 kb
Host smart-f38840dc-5438-4953-923b-8dbfd24f1e3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68749782880528955181607806461111431723389512487969349011330521634023359147389 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_long_reg_writes_reg_reads.687497828805289551816078064611114317233895124879
69349011330521634023359147389
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.32670306263529009241684602791266767202717365550563597174676415642823406195249
Short name T279
Test name
Test status
Simulation time 112796484 ps
CPU time 1.23 seconds
Started Nov 22 12:26:56 PM PST 23
Finished Nov 22 12:27:03 PM PST 23
Peak memory 194564 kb
Host smart-e985e0fe-d6c0-4335-a10d-6c84cd7b1174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32670306263529009241684602791266767202717365550563597174676415642823406195249 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.gpio_smoke.32670306263529009241684602791266767202717365550563597174676415642823406195249
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4547720941359921122952503222710203472090228888812787938269727996653746305637
Short name T241
Test name
Test status
Simulation time 112796484 ps
CPU time 1.32 seconds
Started Nov 22 12:21:44 PM PST 23
Finished Nov 22 12:21:46 PM PST 23
Peak memory 195344 kb
Host smart-50a34e45-8a37-44c7-9818-cc40e656ebc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4547720941359921122952503222710203472090228888812787938269727996653746305637 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4547720941359921122952503222710203472090228888812787938269727996653746305637
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.68740420574563047795700968016506808286568494651636960106474618046339468560471
Short name T809
Test name
Test status
Simulation time 21104521406 ps
CPU time 148.91 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:28:48 PM PST 23
Peak memory 197620 kb
Host smart-7825b85e-bc59-49ab-8f33-5901ae62bc59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6874042057456304779570096801650680828656849465163696010647461804
6339468560471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all.687404205745630477957009680165068082865684946516369601064746180
46339468560471
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2885890034546200634109970218091006336333961572268325461487424521653047750897
Short name T519
Test name
Test status
Simulation time 133069054254 ps
CPU time 1058.66 seconds
Started Nov 22 12:26:05 PM PST 23
Finished Nov 22 12:43:46 PM PST 23
Peak memory 197980 kb
Host smart-aeb3c1d4-68dd-4dc8-bf0b-afebbd52bd45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2885890034546200634109970218091006336333961572268325461487424521653047750897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_wit
h_rand_reset.2885890034546200634109970218091006336333961572268325461487424521653047750897
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3872913496919372129253794390915810485311580415710217398924244575922224872948
Short name T590
Test name
Test status
Simulation time 22440064 ps
CPU time 0.54 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 193828 kb
Host smart-f6406029-3c0d-4260-ae32-cccbd4b938e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872913496919372129253794390915810485311580415710217398924244575922224872948 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.gpio_alert_test.3872913496919372129253794390915810485311580415710217398924244575922224872948
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.80731283935990166634590281522595877519110345249639385346212727765326931611525
Short name T681
Test name
Test status
Simulation time 57921923 ps
CPU time 0.81 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 196168 kb
Host smart-92c66c58-2966-4f27-862a-491a7485a25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80731283935990166634590281522595877519110345249639385346212727765326931611525 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.80731283935990166634590281522595877519110345249639385346212727765326931611525
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.112494789765770689542554373781665702637625053573160208571971526518365791737914
Short name T607
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.76 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 194260 kb
Host smart-515264cc-d121-4575-a1a8-3317e0447d0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112494789765770689542554373781665702637625053573160208571971526518365791737914 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stress.112494789765770689542554373781665702637625053573160208571971526518365791737914
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.44946385020718138526114581002735385326373356736615835426343305881858988145024
Short name T403
Test name
Test status
Simulation time 137439144 ps
CPU time 0.94 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 196308 kb
Host smart-ce2b8b13-9b23-476c-800b-a57b2a5b79de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44946385020718138526114581002735385326373356736615835426343305881858988145024 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.44946385020718138526114581002735385326373356736615835426343305881858988145024
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.31376711884102279039324467676370956730409532726666321346571456906046843740913
Short name T445
Test name
Test status
Simulation time 119314289 ps
CPU time 1.27 seconds
Started Nov 22 12:24:47 PM PST 23
Finished Nov 22 12:24:49 PM PST 23
Peak memory 195908 kb
Host smart-11c3e2a6-15ac-415c-9494-a878917c6475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31376711884102279039324467676370956730409532726666321346571456906046843740913 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.31376711884102279039324467676370956730409532726666321346571456906046843740913
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.46240989225109642242937423471844692943764015008362204300469660932248394607587
Short name T632
Test name
Test status
Simulation time 134635595 ps
CPU time 3.06 seconds
Started Nov 22 12:25:22 PM PST 23
Finished Nov 22 12:25:25 PM PST 23
Peak memory 197036 kb
Host smart-73058fc6-0b7d-4381-af37-c20b171bb88b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46240989225109642242937423471844692943764015008362204300469660932248
394607587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.46240989225109642242937
423471844692943764015008362204300469660932248394607587
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.66529876077076297319803919749653055902481787885384679704004632576771903633575
Short name T498
Test name
Test status
Simulation time 228920555 ps
CPU time 2.8 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:09 PM PST 23
Peak memory 195392 kb
Host smart-79548835-e541-43a5-afbc-ecb82bcc9143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66529876077076297319803919749653055902481787885384679704004632576771903633575 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.66529876077076297319803919749653055902481787885384679704004632576771903633575
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.79963613904423701692003750656817077663452650522475324425671572582191027234324
Short name T539
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:08 PM PST 23
Peak memory 195396 kb
Host smart-3b8acd68-7897-4ecc-960d-aedade50147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79963613904423701692003750656817077663452650522475324425671572582191027234324 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.gpio_random_dout_din.79963613904423701692003750656817077663452650522475324425671572582191027234324
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.57725363639470767153876703324141211878621185200719382967536652931654270619349
Short name T440
Test name
Test status
Simulation time 81278879 ps
CPU time 1.24 seconds
Started Nov 22 12:26:31 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 193212 kb
Host smart-d9ecc1c3-ee62-48c0-b602-90ad779f1849
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57725363639470767153876703324141211878621185200719382967536652931654270619349 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup_pulldown.57725363639470767153876703324141211878621185200719382967536652931654270619349
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.11488380112531809321430629442672222237899514526979364526164646453789489293852
Short name T599
Test name
Test status
Simulation time 572864232 ps
CPU time 5.27 seconds
Started Nov 22 12:23:00 PM PST 23
Finished Nov 22 12:23:05 PM PST 23
Peak memory 197676 kb
Host smart-682fc6fa-0243-4414-8203-709185f954b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11488380112531809321430629442672222237899514526979364526164646453789489293852 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_long_reg_writes_reg_reads.114883801125318093214306294426722222378995145269
79364526164646453789489293852
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.97175492085347572452206551381045931207919585784327889656948234627445625184699
Short name T782
Test name
Test status
Simulation time 112796484 ps
CPU time 1.3 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 194008 kb
Host smart-46b1f048-92b6-457c-8f31-d55869c450d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97175492085347572452206551381045931207919585784327889656948234627445625184699 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.gpio_smoke.97175492085347572452206551381045931207919585784327889656948234627445625184699
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.60068962190140110947514647975230269600041570973753059090913747582355862087864
Short name T756
Test name
Test status
Simulation time 112796484 ps
CPU time 1.35 seconds
Started Nov 22 12:26:31 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 193768 kb
Host smart-7386eabd-5d93-4baa-81ed-22e570983091
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60068962190140110947514647975230269600041570973753059090913747582355862087864 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.60068962190140110947514647975230269600041570973753059090913747582355862087864
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.69697429260739743529388163433999835259275931487990971041092646175392433709636
Short name T510
Test name
Test status
Simulation time 21104521406 ps
CPU time 155.81 seconds
Started Nov 22 12:26:32 PM PST 23
Finished Nov 22 12:29:09 PM PST 23
Peak memory 198028 kb
Host smart-83dd0c40-cbb0-45c3-8a7f-a1819db58ae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6969742926073974352938816343399983525927593148799097104109264617
5392433709636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all.696974292607397435293881634339998352592759314879909710410926461
75392433709636
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.37462020665065177101813922772347801801484310346498507172788001297627783234735
Short name T17
Test name
Test status
Simulation time 133069054254 ps
CPU time 1079.62 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:40:52 PM PST 23
Peak memory 198192 kb
Host smart-a676b356-c095-4a37-afd2-3630e03be8da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=37462020665065177101813922772347801801484310346498507172788001297627783234735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_wi
th_rand_reset.37462020665065177101813922772347801801484310346498507172788001297627783234735
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4841362604015595142051975840622890818777163480070686668078973065643800741255
Short name T798
Test name
Test status
Simulation time 22440064 ps
CPU time 0.54 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:03 PM PST 23
Peak memory 193448 kb
Host smart-427f35d0-be8c-47f6-b6fd-fc84c16d47fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4841362604015595142051975840622890818777163480070686668078973065643800741255 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.gpio_alert_test.4841362604015595142051975840622890818777163480070686668078973065643800741255
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.50755632316724992061681030531467942676616791886249720235838582081630549461152
Short name T691
Test name
Test status
Simulation time 57921923 ps
CPU time 1.05 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 193436 kb
Host smart-24099339-d45c-48f5-a79d-71e4c2644907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50755632316724992061681030531467942676616791886249720235838582081630549461152 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.50755632316724992061681030531467942676616791886249720235838582081630549461152
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.6707745837069120167598801394157764819601654879554141739147363865774235270914
Short name T577
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.67 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:42 PM PST 23
Peak memory 195044 kb
Host smart-9df8ecda-e875-4b93-a02b-246ff8a38b64
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6707745837069120167598801394157764819601654879554141739147363865774235270914 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stress.6707745837069120167598801394157764819601654879554141739147363865774235270914
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.109015681715115556605158158071261804359806706101759730084393939459957165855230
Short name T245
Test name
Test status
Simulation time 137439144 ps
CPU time 1.05 seconds
Started Nov 22 12:22:06 PM PST 23
Finished Nov 22 12:22:08 PM PST 23
Peak memory 196504 kb
Host smart-6eea568f-e466-4ec8-9b58-0547d99454d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109015681715115556605158158071261804359806706101759730084393939459957165855230 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.109015681715115556605158158071261804359806706101759730084393939459957165855230
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.75949436917025007037624223283475378153564049419880139270282691955315679119388
Short name T816
Test name
Test status
Simulation time 119314289 ps
CPU time 1.52 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 192920 kb
Host smart-07112d10-e507-45a8-92d8-846aba30b6c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75949436917025007037624223283475378153564049419880139270282691955315679119388 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.75949436917025007037624223283475378153564049419880139270282691955315679119388
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.27530947673014277031789312559644980412257918132521141752399819245082782443924
Short name T769
Test name
Test status
Simulation time 134635595 ps
CPU time 2.92 seconds
Started Nov 22 12:22:09 PM PST 23
Finished Nov 22 12:22:12 PM PST 23
Peak memory 196984 kb
Host smart-5f0d2588-5fad-4b0f-94fa-551d4fb938a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27530947673014277031789312559644980412257918132521141752399819245082
782443924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.27530947673014277031789
312559644980412257918132521141752399819245082782443924
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.37541436262181807651252811121172640223840768006905274172078255544327930014077
Short name T770
Test name
Test status
Simulation time 228920555 ps
CPU time 2.9 seconds
Started Nov 22 12:25:52 PM PST 23
Finished Nov 22 12:25:57 PM PST 23
Peak memory 194736 kb
Host smart-15a18559-6748-438c-9b60-322e0ce3b64c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541436262181807651252811121172640223840768006905274172078255544327930014077 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.37541436262181807651252811121172640223840768006905274172078255544327930014077
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.51768465739381609896764417798410679717108491782150268947066538664712440907808
Short name T355
Test name
Test status
Simulation time 81278879 ps
CPU time 1.16 seconds
Started Nov 22 12:24:27 PM PST 23
Finished Nov 22 12:24:29 PM PST 23
Peak memory 195652 kb
Host smart-705f433a-53ad-4617-877d-54efc2286f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51768465739381609896764417798410679717108491782150268947066538664712440907808 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.gpio_random_dout_din.51768465739381609896764417798410679717108491782150268947066538664712440907808
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.75258130643924759889484988720329904740886418664636727670247653436084940458793
Short name T708
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:27:49 PM PST 23
Finished Nov 22 12:27:54 PM PST 23
Peak memory 195412 kb
Host smart-b5eebcdc-8a68-4cd5-8bc0-792f14f6963b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75258130643924759889484988720329904740886418664636727670247653436084940458793 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup_pulldown.75258130643924759889484988720329904740886418664636727670247653436084940458793
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.46559754402899505607220980043434820861648841314418362774405988361955953938913
Short name T841
Test name
Test status
Simulation time 572864232 ps
CPU time 4.89 seconds
Started Nov 22 12:25:54 PM PST 23
Finished Nov 22 12:26:00 PM PST 23
Peak memory 197572 kb
Host smart-e4ccfa3f-abaf-4677-ab02-667318271fe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46559754402899505607220980043434820861648841314418362774405988361955953938913 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_long_reg_writes_reg_reads.465597544028995056072209800434348208616488413144
18362774405988361955953938913
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.96010199390729197950754470483394770470299620641144286156052921488821715149161
Short name T711
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:22:49 PM PST 23
Finished Nov 22 12:22:51 PM PST 23
Peak memory 195384 kb
Host smart-a207c54a-12cd-49b3-a090-601e8c92484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96010199390729197950754470483394770470299620641144286156052921488821715149161 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.gpio_smoke.96010199390729197950754470483394770470299620641144286156052921488821715149161
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.49162880294232467687991967791842079313103956628731669392465483958648312180226
Short name T636
Test name
Test status
Simulation time 112796484 ps
CPU time 1.62 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 192364 kb
Host smart-45d4db38-ffe9-48d9-a4b1-1a5f6efde81a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49162880294232467687991967791842079313103956628731669392465483958648312180226 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.49162880294232467687991967791842079313103956628731669392465483958648312180226
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.102814284136085132494661520830936687318420776467664585381787294238695417104534
Short name T326
Test name
Test status
Simulation time 21104521406 ps
CPU time 163.61 seconds
Started Nov 22 12:27:51 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 197872 kb
Host smart-b7fea52e-f5fc-4505-a8c0-edb44fb71f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028142841360851324946615208309366873184207764676645853817872942
38695417104534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all.10281428413608513249466152083093668731842077646766458538178729
4238695417104534
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.18331734039312076557772163332601604520570093962788153744401503381234639156892
Short name T623
Test name
Test status
Simulation time 133069054254 ps
CPU time 1124.78 seconds
Started Nov 22 12:22:56 PM PST 23
Finished Nov 22 12:41:41 PM PST 23
Peak memory 198384 kb
Host smart-ac7fbb4d-e11b-4fa2-b790-7b585f806134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=18331734039312076557772163332601604520570093962788153744401503381234639156892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_wi
th_rand_reset.18331734039312076557772163332601604520570093962788153744401503381234639156892
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.9703484526413987218678835177161872603582445588643986501067400758893575621688
Short name T867
Test name
Test status
Simulation time 22440064 ps
CPU time 0.76 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:26 PM PST 23
Peak memory 191524 kb
Host smart-c412c05e-8229-4342-8b5f-5a395a3b721c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9703484526413987218678835177161872603582445588643986501067400758893575621688 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.gpio_alert_test.9703484526413987218678835177161872603582445588643986501067400758893575621688
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.45090438079294175059169668306749294458716425886846260619571847216106089241038
Short name T811
Test name
Test status
Simulation time 57921923 ps
CPU time 0.85 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 196160 kb
Host smart-3eb4d301-bd12-4757-9b30-f74ab55850db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45090438079294175059169668306749294458716425886846260619571847216106089241038 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.45090438079294175059169668306749294458716425886846260619571847216106089241038
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.104555705432330115001760546595784147938808327985863350998542258325945822493242
Short name T447
Test name
Test status
Simulation time 1135699015 ps
CPU time 23.17 seconds
Started Nov 22 12:25:24 PM PST 23
Finished Nov 22 12:25:48 PM PST 23
Peak memory 195460 kb
Host smart-81bf6b1d-1828-488c-873b-d03bd1c216b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104555705432330115001760546595784147938808327985863350998542258325945822493242 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stress.104555705432330115001760546595784147938808327985863350998542258325945822493242
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.60877288005192017304944050545030030776328016906996500654917439555235302548933
Short name T653
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:10 PM PST 23
Peak memory 196168 kb
Host smart-0bc5daba-9329-4300-bb59-1a010d47970b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60877288005192017304944050545030030776328016906996500654917439555235302548933 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.60877288005192017304944050545030030776328016906996500654917439555235302548933
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.8922751039912075179402345300895614858988161812230131103405245984324076261522
Short name T402
Test name
Test status
Simulation time 119314289 ps
CPU time 1.33 seconds
Started Nov 22 12:24:59 PM PST 23
Finished Nov 22 12:25:01 PM PST 23
Peak memory 195712 kb
Host smart-49a54d74-da27-426a-a5d6-3d28f398dddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8922751039912075179402345300895614858988161812230131103405245984324076261522 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.8922751039912075179402345300895614858988161812230131103405245984324076261522
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.36783670612804880003367947458005548628478810168179562299876241918288421440441
Short name T860
Test name
Test status
Simulation time 134635595 ps
CPU time 3.05 seconds
Started Nov 22 12:24:11 PM PST 23
Finished Nov 22 12:24:15 PM PST 23
Peak memory 197116 kb
Host smart-39ce983b-4813-45c3-86ae-39f77bb8fad7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783670612804880003367947458005548628478810168179562299876241918288
421440441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.36783670612804880003367
947458005548628478810168179562299876241918288421440441
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.22459126527163929398797787306405880600469255751802405329632351465314698756990
Short name T215
Test name
Test status
Simulation time 228920555 ps
CPU time 3.05 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:07 PM PST 23
Peak memory 193080 kb
Host smart-2b42e54b-2359-4b83-9d00-cf2c2f469bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22459126527163929398797787306405880600469255751802405329632351465314698756990 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.22459126527163929398797787306405880600469255751802405329632351465314698756990
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1753974198542686495317387788519652927233939675572087130710329569454864458804
Short name T207
Test name
Test status
Simulation time 81278879 ps
CPU time 1.49 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 193572 kb
Host smart-5e27fda2-00c1-42be-950b-4b666fe8ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753974198542686495317387788519652927233939675572087130710329569454864458804 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.gpio_random_dout_din.1753974198542686495317387788519652927233939675572087130710329569454864458804
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.94732849089382691221025618032550310208951250261065473012918006176057021662371
Short name T575
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:25:11 PM PST 23
Finished Nov 22 12:25:12 PM PST 23
Peak memory 195688 kb
Host smart-e9d700bf-c4a6-4dd2-98c8-0da1bbd06a7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94732849089382691221025618032550310208951250261065473012918006176057021662371 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup_pulldown.94732849089382691221025618032550310208951250261065473012918006176057021662371
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4751076981882972039271711311712331881105907193246399198523255836185437761798
Short name T705
Test name
Test status
Simulation time 572864232 ps
CPU time 5.26 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:30 PM PST 23
Peak memory 194740 kb
Host smart-8e2b8302-4d6d-442d-b3c2-c72fa6d6fd65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4751076981882972039271711311712331881105907193246399198523255836185437761798 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_long_reg_writes_reg_reads.4751076981882972039271711311712331881105907193246
399198523255836185437761798
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.45540438892687296235317028314564407849752610783562248434813618499833848553088
Short name T341
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 195344 kb
Host smart-2be13f1e-840b-465e-b386-730cb22bec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45540438892687296235317028314564407849752610783562248434813618499833848553088 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.gpio_smoke.45540438892687296235317028314564407849752610783562248434813618499833848553088
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.62135175959457166311964495802509805473433916002062669932104706088331854728257
Short name T525
Test name
Test status
Simulation time 112796484 ps
CPU time 1.63 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 192624 kb
Host smart-7c9be0f6-f87a-405e-bf3f-e8f63ac63d73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62135175959457166311964495802509805473433916002062669932104706088331854728257 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.62135175959457166311964495802509805473433916002062669932104706088331854728257
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.66922540777053559905192663626118351721998818500756957248107236092097677700329
Short name T386
Test name
Test status
Simulation time 21104521406 ps
CPU time 150.53 seconds
Started Nov 22 12:27:01 PM PST 23
Finished Nov 22 12:29:38 PM PST 23
Peak memory 197732 kb
Host smart-72f3e328-9e8a-4460-bfad-a464751fd313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6692254077705355990519266362611835172199881850075695724810723609
2097677700329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all.669225407770535599051926636261183517219988185007569572481072360
92097677700329
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.25452693649647238453785419174304300863288753572838538890365231383576506029901
Short name T384
Test name
Test status
Simulation time 133069054254 ps
CPU time 1077.04 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:44:21 PM PST 23
Peak memory 198068 kb
Host smart-d5d7e6cc-afa8-48d9-bf6e-c9887a65eb33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=25452693649647238453785419174304300863288753572838538890365231383576506029901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_wi
th_rand_reset.25452693649647238453785419174304300863288753572838538890365231383576506029901
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.43413926316344215667174877686086138628424989349408546114098361030572124622479
Short name T700
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:07 PM PST 23
Peak memory 193540 kb
Host smart-a756edda-361b-4093-9760-ba9e5a1485f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43413926316344215667174877686086138628424989349408546114098361030572124622479 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.gpio_alert_test.43413926316344215667174877686086138628424989349408546114098361030572124622479
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.70369202504749110728139142497755838775385766073813072409316664249635142140513
Short name T427
Test name
Test status
Simulation time 57921923 ps
CPU time 1.02 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:26 PM PST 23
Peak memory 194100 kb
Host smart-86f8c0d6-04b6-42ae-9bb5-61315febdb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70369202504749110728139142497755838775385766073813072409316664249635142140513 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.70369202504749110728139142497755838775385766073813072409316664249635142140513
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1544309445078490569183156931697805574044821809591362218111508357859274595251
Short name T703
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.64 seconds
Started Nov 22 12:27:50 PM PST 23
Finished Nov 22 12:28:15 PM PST 23
Peak memory 195280 kb
Host smart-8993e077-70fa-4314-ba0a-c77ab5dd7507
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544309445078490569183156931697805574044821809591362218111508357859274595251 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress.1544309445078490569183156931697805574044821809591362218111508357859274595251
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.112973482617949508658723454447976122395907187506303849833647558057015596756255
Short name T453
Test name
Test status
Simulation time 137439144 ps
CPU time 1.16 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:26 PM PST 23
Peak memory 193928 kb
Host smart-213ad1a9-77b5-4c44-a12b-c1cabf9d9f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112973482617949508658723454447976122395907187506303849833647558057015596756255 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.112973482617949508658723454447976122395907187506303849833647558057015596756255
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.46795635245618683820023343540412650242817979095503864674264412675119717606985
Short name T507
Test name
Test status
Simulation time 119314289 ps
CPU time 1.49 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 193420 kb
Host smart-0f429420-169f-4010-b454-e6e94e4ab8a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46795635245618683820023343540412650242817979095503864674264412675119717606985 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.46795635245618683820023343540412650242817979095503864674264412675119717606985
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.114949929479213290726939657759769551583084305207632321971756829374447180615335
Short name T594
Test name
Test status
Simulation time 134635595 ps
CPU time 2.91 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 196784 kb
Host smart-adeaae2f-5fa5-48f5-a317-ea1c3d98800b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494992947921329072693965775976955158308430520763232197175682937444
7180615335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1149499294792132907269
39657759769551583084305207632321971756829374447180615335
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1277875843663296406189397579936972552761426332155524485190984217781523019225
Short name T352
Test name
Test status
Simulation time 228920555 ps
CPU time 2.78 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:55 PM PST 23
Peak memory 195732 kb
Host smart-42c0b882-05fe-438b-891c-035cd206eedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277875843663296406189397579936972552761426332155524485190984217781523019225 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.1277875843663296406189397579936972552761426332155524485190984217781523019225
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.99989702389674432121438059368949180510866740145306529218034171486552868610415
Short name T666
Test name
Test status
Simulation time 81278879 ps
CPU time 1.45 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 193228 kb
Host smart-773c5ad7-27ad-47cd-af4a-01bf39038b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99989702389674432121438059368949180510866740145306529218034171486552868610415 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.gpio_random_dout_din.99989702389674432121438059368949180510866740145306529218034171486552868610415
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.102017592617308942252660627460917610427768146788815340446041162723747115062720
Short name T776
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:25:53 PM PST 23
Finished Nov 22 12:25:55 PM PST 23
Peak memory 195324 kb
Host smart-e9657fa5-c3b4-4c9f-9bf9-15382b05bdcc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102017592617308942252660627460917610427768146788815340446041162723747115062720 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup_pulldown.102017592617308942252660627460917610427768146788815340446041162723747115062720
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.25329782088136400393001359848786906299209586510512346432348114239989909774519
Short name T213
Test name
Test status
Simulation time 572864232 ps
CPU time 5.03 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:12 PM PST 23
Peak memory 197460 kb
Host smart-5abd7415-9ddd-4926-aa6e-615239c5ae6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329782088136400393001359848786906299209586510512346432348114239989909774519 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_long_reg_writes_reg_reads.253297820881364003930013598487869062992095865105
12346432348114239989909774519
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.71362303676008952533832066215650816539581115521616828381181496418474670865684
Short name T481
Test name
Test status
Simulation time 112796484 ps
CPU time 1.58 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 193468 kb
Host smart-81064a01-9a7a-488c-911e-18be8f189900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71362303676008952533832066215650816539581115521616828381181496418474670865684 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.gpio_smoke.71362303676008952533832066215650816539581115521616828381181496418474670865684
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.61324153398249366188545012551174532882427839051364640799603013705928905310999
Short name T574
Test name
Test status
Simulation time 112796484 ps
CPU time 1.29 seconds
Started Nov 22 12:26:27 PM PST 23
Finished Nov 22 12:26:32 PM PST 23
Peak memory 195360 kb
Host smart-e962d9a8-142e-40d6-8f55-9eb7d3e02159
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61324153398249366188545012551174532882427839051364640799603013705928905310999 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.61324153398249366188545012551174532882427839051364640799603013705928905310999
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.52263785780426840344239071960216718875000829135845261573946769053111709389817
Short name T451
Test name
Test status
Simulation time 21104521406 ps
CPU time 157.99 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:29:03 PM PST 23
Peak memory 197860 kb
Host smart-cb7c5397-61b0-4246-a97a-be8664ad3bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5226378578042684034423907196021671887500082913584526157394676905
3111709389817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all.522637857804268403442390719602167188750008291358452615739467690
53111709389817
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.107868139917219345263582497792072914723038159900789504582813049200140161670621
Short name T562
Test name
Test status
Simulation time 133069054254 ps
CPU time 1050.72 seconds
Started Nov 22 12:25:53 PM PST 23
Finished Nov 22 12:43:25 PM PST 23
Peak memory 197756 kb
Host smart-fd11c96e-d5da-496d-8793-fc8452a545db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=107868139917219345263582497792072914723038159900789504582813049200140161670621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_w
ith_rand_reset.107868139917219345263582497792072914723038159900789504582813049200140161670621
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.49879888300896263383886525735019414815383524017762174371938505171456076309161
Short name T646
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:25:02 PM PST 23
Finished Nov 22 12:25:03 PM PST 23
Peak memory 193636 kb
Host smart-4f94ef78-0499-47b1-87fa-81db4e7b5962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49879888300896263383886525735019414815383524017762174371938505171456076309161 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.gpio_alert_test.49879888300896263383886525735019414815383524017762174371938505171456076309161
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.97380697873947487462058664500688511469121156684511114767137813723241436412881
Short name T449
Test name
Test status
Simulation time 57921923 ps
CPU time 0.81 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 196016 kb
Host smart-e8b6ff10-7470-4b41-b619-4b3e9b586184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97380697873947487462058664500688511469121156684511114767137813723241436412881 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.97380697873947487462058664500688511469121156684511114767137813723241436412881
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.101463147763289759471607681152985353880683151184799845829238378378050547260617
Short name T729
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.63 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 195136 kb
Host smart-50666b34-da89-4479-8614-aa9e7b5a49d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101463147763289759471607681152985353880683151184799845829238378378050547260617 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stress.101463147763289759471607681152985353880683151184799845829238378378050547260617
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.19273399501736458247975438669318450082731324516802318710837700243225452755945
Short name T311
Test name
Test status
Simulation time 137439144 ps
CPU time 0.94 seconds
Started Nov 22 12:25:00 PM PST 23
Finished Nov 22 12:25:02 PM PST 23
Peak memory 194992 kb
Host smart-c7471c2b-a2d8-4e91-acf5-0d0213609aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19273399501736458247975438669318450082731324516802318710837700243225452755945 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.19273399501736458247975438669318450082731324516802318710837700243225452755945
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.112619059116352763410664855551339699977242261643392097141848629679005931045896
Short name T598
Test name
Test status
Simulation time 119314289 ps
CPU time 1.24 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:07 PM PST 23
Peak memory 194244 kb
Host smart-ae51167f-daef-4682-9e1a-c4f565257bd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112619059116352763410664855551339699977242261643392097141848629679005931045896 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.112619059116352763410664855551339699977242261643392097141848629679005931045896
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.21889844032806622414269047025751575031029458938608691266517190936229110192891
Short name T808
Test name
Test status
Simulation time 134635595 ps
CPU time 2.99 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 195504 kb
Host smart-f912271e-8356-4cb4-b6fa-2e57e18b4164
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889844032806622414269047025751575031029458938608691266517190936229
110192891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.21889844032806622414269
047025751575031029458938608691266517190936229110192891
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.53407998155030832132943124715386353509309160459342903963812404039532597780506
Short name T471
Test name
Test status
Simulation time 228920555 ps
CPU time 3.03 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 192992 kb
Host smart-e611378b-35a3-45be-9d6e-902113ea4b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53407998155030832132943124715386353509309160459342903963812404039532597780506 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.53407998155030832132943124715386353509309160459342903963812404039532597780506
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.55310544307808557018052716714130463485793943359036589063951127602150459054560
Short name T582
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:25:01 PM PST 23
Finished Nov 22 12:25:03 PM PST 23
Peak memory 195364 kb
Host smart-d5cb31b6-f588-449e-96c6-af4fc7b32fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55310544307808557018052716714130463485793943359036589063951127602150459054560 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.gpio_random_dout_din.55310544307808557018052716714130463485793943359036589063951127602150459054560
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.61824070089429233551239169150194443993196973408875100358419621814292826581274
Short name T628
Test name
Test status
Simulation time 81278879 ps
CPU time 1.36 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:26 PM PST 23
Peak memory 193212 kb
Host smart-8b1ade0c-7d21-4bd5-9163-d5da7b898b43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61824070089429233551239169150194443993196973408875100358419621814292826581274 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup_pulldown.61824070089429233551239169150194443993196973408875100358419621814292826581274
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.74109235188441006737276032013417707073620875525259538767111635648273492032665
Short name T336
Test name
Test status
Simulation time 572864232 ps
CPU time 5.39 seconds
Started Nov 22 12:22:55 PM PST 23
Finished Nov 22 12:23:01 PM PST 23
Peak memory 197728 kb
Host smart-84e36465-35f0-481d-9b57-27910ea5cc69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74109235188441006737276032013417707073620875525259538767111635648273492032665 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_long_reg_writes_reg_reads.741092351884410067372760320134177070736208755252
59538767111635648273492032665
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.46838582338640449609598186671032457583307503934483249111286762131014958012750
Short name T485
Test name
Test status
Simulation time 112796484 ps
CPU time 1.33 seconds
Started Nov 22 12:23:04 PM PST 23
Finished Nov 22 12:23:06 PM PST 23
Peak memory 195412 kb
Host smart-bae76682-2695-4958-ab2c-3837f46fefaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46838582338640449609598186671032457583307503934483249111286762131014958012750 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.gpio_smoke.46838582338640449609598186671032457583307503934483249111286762131014958012750
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.10803584118335909867423771424107535440062800503070440203592648525433132118710
Short name T586
Test name
Test status
Simulation time 112796484 ps
CPU time 1.52 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:27 PM PST 23
Peak memory 192880 kb
Host smart-bba28338-0086-4e0b-87cc-ccdfa5730944
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803584118335909867423771424107535440062800503070440203592648525433132118710 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.10803584118335909867423771424107535440062800503070440203592648525433132118710
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.38602457942625164883993279347531644914773930675979689118789494137343635197138
Short name T831
Test name
Test status
Simulation time 21104521406 ps
CPU time 167.91 seconds
Started Nov 22 12:27:13 PM PST 23
Finished Nov 22 12:30:08 PM PST 23
Peak memory 197716 kb
Host smart-f0013d09-037d-426d-8c97-4e061a41e1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860245794262516488399327934753164491477393067597968911878949413
7343635197138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all.386024579426251648839932793475316449147739306759796891187894941
37343635197138
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1122769481111691211322574759106784084441298970221319894942670479438217200130
Short name T830
Test name
Test status
Simulation time 133069054254 ps
CPU time 1094.6 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:45:21 PM PST 23
Peak memory 196904 kb
Host smart-d0234439-6efb-45d5-a0c4-d081a73e18ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1122769481111691211322574759106784084441298970221319894942670479438217200130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_wit
h_rand_reset.1122769481111691211322574759106784084441298970221319894942670479438217200130
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.71705252147726966822321066692961428719517793053032645257305132323576134607940
Short name T753
Test name
Test status
Simulation time 22440064 ps
CPU time 0.69 seconds
Started Nov 22 12:26:26 PM PST 23
Finished Nov 22 12:26:31 PM PST 23
Peak memory 191900 kb
Host smart-05d493b0-7f2b-425c-b68a-5b9f45ad6424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71705252147726966822321066692961428719517793053032645257305132323576134607940 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.gpio_alert_test.71705252147726966822321066692961428719517793053032645257305132323576134607940
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.47910483140890778675734090992665351755308603665604387862165977920832070591770
Short name T642
Test name
Test status
Simulation time 57921923 ps
CPU time 0.83 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 195044 kb
Host smart-c6e943d2-c462-492b-86ff-a815f278b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47910483140890778675734090992665351755308603665604387862165977920832070591770 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.47910483140890778675734090992665351755308603665604387862165977920832070591770
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.99168724794953565802233917111278093042794876860590219384952831316920323372485
Short name T490
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.33 seconds
Started Nov 22 12:27:40 PM PST 23
Finished Nov 22 12:28:11 PM PST 23
Peak memory 193860 kb
Host smart-c7522e59-7152-4ac4-9cab-66b47a493999
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99168724794953565802233917111278093042794876860590219384952831316920323372485 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress.99168724794953565802233917111278093042794876860590219384952831316920323372485
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.25397412766848349204533052997732677965993279799736115035645679019875558715412
Short name T549
Test name
Test status
Simulation time 137439144 ps
CPU time 0.91 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:23 PM PST 23
Peak memory 196240 kb
Host smart-25b6f3e8-0f4d-42ef-aa5f-81a406ec2ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25397412766848349204533052997732677965993279799736115035645679019875558715412 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.25397412766848349204533052997732677965993279799736115035645679019875558715412
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.52069013408812673311424932852892389484746123344459927228198615430587376816119
Short name T78
Test name
Test status
Simulation time 119314289 ps
CPU time 1.15 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 195220 kb
Host smart-a0c28c7a-ea5d-468e-bfce-0ee64fd91162
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52069013408812673311424932852892389484746123344459927228198615430587376816119 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.52069013408812673311424932852892389484746123344459927228198615430587376816119
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.93452397203997649903501034059156423466352721308797646218133063371029045786043
Short name T649
Test name
Test status
Simulation time 134635595 ps
CPU time 2.9 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 196908 kb
Host smart-d62f69a5-4e11-4fda-b321-827a2700a4e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93452397203997649903501034059156423466352721308797646218133063371029
045786043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.93452397203997649903501
034059156423466352721308797646218133063371029045786043
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.52662068393217883159519774169473538069651565211141720349088790759811926011747
Short name T515
Test name
Test status
Simulation time 228920555 ps
CPU time 2.76 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 195416 kb
Host smart-95e681a5-fb54-4b98-a45b-6d15b74272ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52662068393217883159519774169473538069651565211141720349088790759811926011747 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.52662068393217883159519774169473538069651565211141720349088790759811926011747
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.13714566149248653767901734131146519549211902792722571454635217107766189061732
Short name T560
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:24:41 PM PST 23
Finished Nov 22 12:24:43 PM PST 23
Peak memory 195716 kb
Host smart-6fb985dd-0f52-4a7b-9871-23b1ca569e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13714566149248653767901734131146519549211902792722571454635217107766189061732 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.gpio_random_dout_din.13714566149248653767901734131146519549211902792722571454635217107766189061732
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.104198789916145356988147821641186981484305434899391362360880172313898115551001
Short name T626
Test name
Test status
Simulation time 81278879 ps
CPU time 1.18 seconds
Started Nov 22 12:22:23 PM PST 23
Finished Nov 22 12:22:25 PM PST 23
Peak memory 195676 kb
Host smart-d75fc0e7-27fe-4ddd-b5f3-f9e700bc1d96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104198789916145356988147821641186981484305434899391362360880172313898115551001 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup_pulldown.104198789916145356988147821641186981484305434899391362360880172313898115551001
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.66786388394795864210151950118014121098483185238518622992851041076101861213813
Short name T833
Test name
Test status
Simulation time 572864232 ps
CPU time 5.12 seconds
Started Nov 22 12:26:14 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 197452 kb
Host smart-024653c8-7235-452a-aa2f-86ddebaf65cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66786388394795864210151950118014121098483185238518622992851041076101861213813 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_long_reg_writes_reg_reads.667863883947958642101519501180141210984831852385
18622992851041076101861213813
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.63632306851553030138814822574170741832084478410040476939401671697794952011943
Short name T791
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:27:51 PM PST 23
Finished Nov 22 12:27:55 PM PST 23
Peak memory 195308 kb
Host smart-da96bfeb-73e7-4e59-b672-cc1fc17970ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63632306851553030138814822574170741832084478410040476939401671697794952011943 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.gpio_smoke.63632306851553030138814822574170741832084478410040476939401671697794952011943
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.29709028454265131370383664984390000391218201458010832115678719279802009504509
Short name T696
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 194384 kb
Host smart-3df62efb-7fa6-41e7-a5df-65fb09d7a6e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29709028454265131370383664984390000391218201458010832115678719279802009504509 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.29709028454265131370383664984390000391218201458010832115678719279802009504509
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.64228208048135156423612132795901286474739691822130149272307708122147806086424
Short name T763
Test name
Test status
Simulation time 21104521406 ps
CPU time 170.97 seconds
Started Nov 22 12:22:23 PM PST 23
Finished Nov 22 12:25:15 PM PST 23
Peak memory 197984 kb
Host smart-9df5d278-5b6c-433d-8334-18f02df285d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6422820804813515642361213279590128647473969182213014927230770812
2147806086424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all.642282080481351564236121327959012864747396918221301492723077081
22147806086424
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.75919208927281852253212712553644427048937986522034109973693377713508614847277
Short name T826
Test name
Test status
Simulation time 133069054254 ps
CPU time 1074.55 seconds
Started Nov 22 12:25:01 PM PST 23
Finished Nov 22 12:42:57 PM PST 23
Peak memory 197964 kb
Host smart-1647f8c7-94cb-4948-aee3-e6d9544fc453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=75919208927281852253212712553644427048937986522034109973693377713508614847277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_wi
th_rand_reset.75919208927281852253212712553644427048937986522034109973693377713508614847277
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.99044385156402531936560410580119026459520509025938517544202032798828643095249
Short name T645
Test name
Test status
Simulation time 22440064 ps
CPU time 0.54 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 193452 kb
Host smart-8b91386f-433b-497b-a162-a5101bc89c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99044385156402531936560410580119026459520509025938517544202032798828643095249 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.gpio_alert_test.99044385156402531936560410580119026459520509025938517544202032798828643095249
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.85231165871210827603868809572060470841447081901377155532037992368184717661972
Short name T268
Test name
Test status
Simulation time 57921923 ps
CPU time 0.86 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:23 PM PST 23
Peak memory 196232 kb
Host smart-636d333b-6895-4ef7-a65a-10cd19b2b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85231165871210827603868809572060470841447081901377155532037992368184717661972 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.85231165871210827603868809572060470841447081901377155532037992368184717661972
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.75100001033908251198465701712257924964582667218290547078435914503742922436497
Short name T627
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.8 seconds
Started Nov 22 12:21:43 PM PST 23
Finished Nov 22 12:22:06 PM PST 23
Peak memory 195424 kb
Host smart-59bf7895-aeee-4ac8-812c-eedc8d343b48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75100001033908251198465701712257924964582667218290547078435914503742922436497 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress.75100001033908251198465701712257924964582667218290547078435914503742922436497
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.43428230741531969297372179655677232116442944381829233353363345391601024434240
Short name T680
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 195928 kb
Host smart-a8fae12c-62c7-46a1-90af-c49ba0d51de2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43428230741531969297372179655677232116442944381829233353363345391601024434240 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.43428230741531969297372179655677232116442944381829233353363345391601024434240
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.9931030829427053886954843810628335274890186627883374410743385246001392927661
Short name T339
Test name
Test status
Simulation time 119314289 ps
CPU time 1.25 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:53 PM PST 23
Peak memory 195664 kb
Host smart-48b8a0c9-1b50-4dca-9d2b-bb364b56c1ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9931030829427053886954843810628335274890186627883374410743385246001392927661 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.9931030829427053886954843810628335274890186627883374410743385246001392927661
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.63560884370598948437776729886546795156821927196254235385007861107333193362147
Short name T631
Test name
Test status
Simulation time 134635595 ps
CPU time 3.05 seconds
Started Nov 22 12:22:04 PM PST 23
Finished Nov 22 12:22:10 PM PST 23
Peak memory 197000 kb
Host smart-9d60fab9-758e-431c-8af4-2fa2db5132cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63560884370598948437776729886546795156821927196254235385007861107333
193362147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.635608843705989484377767
29886546795156821927196254235385007861107333193362147
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.27630917687525253001274542245938872028080940331898138157785642994388390176456
Short name T793
Test name
Test status
Simulation time 228920555 ps
CPU time 2.91 seconds
Started Nov 22 12:22:09 PM PST 23
Finished Nov 22 12:22:13 PM PST 23
Peak memory 195624 kb
Host smart-62a7b156-a980-4c36-8e8a-30f5812d01d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27630917687525253001274542245938872028080940331898138157785642994388390176456 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.27630917687525253001274542245938872028080940331898138157785642994388390176456
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.91418591729776839642118603101706427503351922191693219125961859584203625344003
Short name T728
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:23:03 PM PST 23
Finished Nov 22 12:23:04 PM PST 23
Peak memory 195568 kb
Host smart-811b6be7-f731-492f-81e2-04c97141bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91418591729776839642118603101706427503351922191693219125961859584203625344003 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.gpio_random_dout_din.91418591729776839642118603101706427503351922191693219125961859584203625344003
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.77803824613588562984414380315717495819110732346385196922283324429083500284419
Short name T247
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:53 PM PST 23
Peak memory 195684 kb
Host smart-90f91109-8dbd-4d78-93d1-935c84775f18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77803824613588562984414380315717495819110732346385196922283324429083500284419 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_pulldown.77803824613588562984414380315717495819110732346385196922283324429083500284419
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.66005736856850227563211034157212543841875806217059013910985002485740355605928
Short name T821
Test name
Test status
Simulation time 572864232 ps
CPU time 5.33 seconds
Started Nov 22 12:21:06 PM PST 23
Finished Nov 22 12:21:12 PM PST 23
Peak memory 197356 kb
Host smart-ffe53c58-ab05-420b-9944-91d388fb1fba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66005736856850227563211034157212543841875806217059013910985002485740355605928 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_long_reg_writes_reg_reads.6600573685685022756321103415721254384187580621705
9013910985002485740355605928
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.24366652124246967292532307116519927609575034749254327509730493352356297656092
Short name T54
Test name
Test status
Simulation time 134885593 ps
CPU time 0.91 seconds
Started Nov 22 12:26:49 PM PST 23
Finished Nov 22 12:26:51 PM PST 23
Peak memory 214640 kb
Host smart-89c4aee2-d44e-45aa-b5fd-4d5c82e85bc4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24366652124246967292532307116519927609575034749254327509730493352356297656092 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.gpio_sec_cm.24366652124246967292532307116519927609575034749254327509730493352356297656092
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.14187251167182381643732096137568534713322051150225729420014762404598674656366
Short name T710
Test name
Test status
Simulation time 112796484 ps
CPU time 1.31 seconds
Started Nov 22 12:22:58 PM PST 23
Finished Nov 22 12:23:00 PM PST 23
Peak memory 195384 kb
Host smart-0bd19146-fc59-456b-8157-b36035179e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14187251167182381643732096137568534713322051150225729420014762404598674656366 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.gpio_smoke.14187251167182381643732096137568534713322051150225729420014762404598674656366
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.23133622608545051558729335023831036587116754784957265013915361438999133367051
Short name T202
Test name
Test status
Simulation time 112796484 ps
CPU time 1.27 seconds
Started Nov 22 12:22:32 PM PST 23
Finished Nov 22 12:22:33 PM PST 23
Peak memory 195656 kb
Host smart-75f31371-9b3f-481c-9c5d-d4a9e4333946
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133622608545051558729335023831036587116754784957265013915361438999133367051 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.23133622608545051558729335023831036587116754784957265013915361438999133367051
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.78567829141984837314334064013132928469099146806068225222946676894935988119846
Short name T762
Test name
Test status
Simulation time 21104521406 ps
CPU time 164.61 seconds
Started Nov 22 12:27:42 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 197324 kb
Host smart-75830752-b3b5-4c87-980e-1c80eb524a9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7856782914198483731433406401313292846909914680606822522294667689
4935988119846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all.7856782914198483731433406401313292846909914680606822522294667689
4935988119846
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.68672905984059472595069850096293081609402791205667240209815898458133807745264
Short name T457
Test name
Test status
Simulation time 133069054254 ps
CPU time 1113.71 seconds
Started Nov 22 12:21:38 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 197972 kb
Host smart-45bdef68-fe2b-4e64-8116-3486d5cf62e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=68672905984059472595069850096293081609402791205667240209815898458133807745264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_wit
h_rand_reset.68672905984059472595069850096293081609402791205667240209815898458133807745264
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.108065878803419731549202649613104842120052978170161232626222897872110551437028
Short name T369
Test name
Test status
Simulation time 22440064 ps
CPU time 0.61 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:07 PM PST 23
Peak memory 193428 kb
Host smart-4e25fbe9-47a1-4ee2-b637-2cb500314b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108065878803419731549202649613104842120052978170161232626222897872110551437028 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.108065878803419731549202649613104842120052978170161232626222897872110551437028
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.31495760209271363116627409118711986237481428891408079875277647717154553005660
Short name T461
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:22:29 PM PST 23
Finished Nov 22 12:22:30 PM PST 23
Peak memory 196292 kb
Host smart-19b29471-eb3d-4319-be7d-afe63e89137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31495760209271363116627409118711986237481428891408079875277647717154553005660 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.31495760209271363116627409118711986237481428891408079875277647717154553005660
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.104803610702183361057600685723595891003127461532601336582662894163832299699367
Short name T536
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.1 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:31 PM PST 23
Peak memory 193276 kb
Host smart-f2704210-7e86-4689-b491-3a8538f5f2cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104803610702183361057600685723595891003127461532601336582662894163832299699367 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stress.104803610702183361057600685723595891003127461532601336582662894163832299699367
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.88612696591982294794827201716803676914766066750062876618508689968591317743766
Short name T345
Test name
Test status
Simulation time 137439144 ps
CPU time 1.19 seconds
Started Nov 22 12:25:52 PM PST 23
Finished Nov 22 12:25:54 PM PST 23
Peak memory 196400 kb
Host smart-7dd870d7-ecd7-48da-9fe6-0ff9ce493bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88612696591982294794827201716803676914766066750062876618508689968591317743766 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.88612696591982294794827201716803676914766066750062876618508689968591317743766
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.46084184575738446508513412366153484275356326669742225322935556100180216967634
Short name T253
Test name
Test status
Simulation time 119314289 ps
CPU time 1.2 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 195532 kb
Host smart-588a8da7-9c3a-4a23-99f3-3ee848449011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46084184575738446508513412366153484275356326669742225322935556100180216967634 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.46084184575738446508513412366153484275356326669742225322935556100180216967634
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.112832296350726464763762599351731591562399305617262793618525941739253724815098
Short name T83
Test name
Test status
Simulation time 134635595 ps
CPU time 2.87 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:26:04 PM PST 23
Peak memory 195668 kb
Host smart-fcc3ac20-880c-4ebd-a211-529082efa735
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11283229635072646476376259935173159156239930561726279361852594173925
3724815098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1128322963507264647637
62599351731591562399305617262793618525941739253724815098
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.61748939738225096948420580115719765431122734167373999763597147077874689917960
Short name T767
Test name
Test status
Simulation time 228920555 ps
CPU time 2.83 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:10 PM PST 23
Peak memory 195400 kb
Host smart-c6ec0652-60dd-42dd-9f9f-eb25a20d4963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61748939738225096948420580115719765431122734167373999763597147077874689917960 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.61748939738225096948420580115719765431122734167373999763597147077874689917960
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.13660641024670762296958834190896035741800984464770804823000786328738640202216
Short name T329
Test name
Test status
Simulation time 81278879 ps
CPU time 1.06 seconds
Started Nov 22 12:25:12 PM PST 23
Finished Nov 22 12:25:14 PM PST 23
Peak memory 195644 kb
Host smart-2b1a99fa-4dcc-476c-a363-ad144aa73f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13660641024670762296958834190896035741800984464770804823000786328738640202216 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.gpio_random_dout_din.13660641024670762296958834190896035741800984464770804823000786328738640202216
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.68890390620602655696811992422276309766283128271277344520084859421746975755575
Short name T503
Test name
Test status
Simulation time 81278879 ps
CPU time 1.23 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 193348 kb
Host smart-777a423c-04f9-45a9-ae48-be2e1a4a4b6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68890390620602655696811992422276309766283128271277344520084859421746975755575 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup_pulldown.68890390620602655696811992422276309766283128271277344520084859421746975755575
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.53609884817330693554792185436205709320161415538878513680445775517402692053825
Short name T738
Test name
Test status
Simulation time 572864232 ps
CPU time 5.02 seconds
Started Nov 22 12:26:10 PM PST 23
Finished Nov 22 12:26:16 PM PST 23
Peak memory 197696 kb
Host smart-c9b88c09-7c44-441a-bba0-2febcab81f34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53609884817330693554792185436205709320161415538878513680445775517402692053825 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_long_reg_writes_reg_reads.536098848173306935547921854362057093201614155388
78513680445775517402692053825
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.39975718822797499088929809191410791922492155792155782641190469332095399531351
Short name T532
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 195256 kb
Host smart-6f6c18d8-857c-473c-9d99-87ec9bf6e514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39975718822797499088929809191410791922492155792155782641190469332095399531351 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.gpio_smoke.39975718822797499088929809191410791922492155792155782641190469332095399531351
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.51055441024137651565723324777357142754048052548968510481475896562658362281873
Short name T396
Test name
Test status
Simulation time 112796484 ps
CPU time 1.31 seconds
Started Nov 22 12:25:35 PM PST 23
Finished Nov 22 12:25:43 PM PST 23
Peak memory 195524 kb
Host smart-76633756-92da-4621-99b5-fe999fdd7477
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51055441024137651565723324777357142754048052548968510481475896562658362281873 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.51055441024137651565723324777357142754048052548968510481475896562658362281873
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.28177543688243158986911025846491012905774848459019123084132815218702702161360
Short name T323
Test name
Test status
Simulation time 21104521406 ps
CPU time 162.93 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:28:45 PM PST 23
Peak memory 196536 kb
Host smart-f9d9c2d5-9979-420f-a823-bee723cfabbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817754368824315898691102584649101290577484845901912308413281521
8702702161360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all.281775436882431589869110258464910129057748484590191230841328152
18702702161360
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.61020975703785032954216721511916854958688226134592707147812707669667513166955
Short name T720
Test name
Test status
Simulation time 133069054254 ps
CPU time 1167.28 seconds
Started Nov 22 12:24:02 PM PST 23
Finished Nov 22 12:43:30 PM PST 23
Peak memory 198384 kb
Host smart-4809070d-6d83-470b-b56e-a3511fefef89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=61020975703785032954216721511916854958688226134592707147812707669667513166955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_wi
th_rand_reset.61020975703785032954216721511916854958688226134592707147812707669667513166955
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.62035377641800292860066865440552237210078560416800470482836664091805979392208
Short name T62
Test name
Test status
Simulation time 22440064 ps
CPU time 0.57 seconds
Started Nov 22 12:22:19 PM PST 23
Finished Nov 22 12:22:20 PM PST 23
Peak memory 193760 kb
Host smart-62b6519c-69ca-474a-9579-af8348730c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62035377641800292860066865440552237210078560416800470482836664091805979392208 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.gpio_alert_test.62035377641800292860066865440552237210078560416800470482836664091805979392208
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.98746263232086841250567248076306408285325225139603253019394038178381982845093
Short name T736
Test name
Test status
Simulation time 57921923 ps
CPU time 0.89 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:07 PM PST 23
Peak memory 195372 kb
Host smart-3d37a98e-109a-4db9-aa6c-3e8a4005ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98746263232086841250567248076306408285325225139603253019394038178381982845093 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.98746263232086841250567248076306408285325225139603253019394038178381982845093
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.102055582657569043718515105631027592285271077075677478024873888035452624933770
Short name T472
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.51 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:23:15 PM PST 23
Peak memory 195468 kb
Host smart-76f67483-2bee-427c-9e5a-79262354746e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102055582657569043718515105631027592285271077075677478024873888035452624933770 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stress.102055582657569043718515105631027592285271077075677478024873888035452624933770
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.53061895565438714660947861268565895524228369435954744378689185498362292160793
Short name T777
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:23:40 PM PST 23
Finished Nov 22 12:23:42 PM PST 23
Peak memory 196284 kb
Host smart-3daa92a2-23ca-46c8-a10b-f2ad0feb4586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53061895565438714660947861268565895524228369435954744378689185498362292160793 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.53061895565438714660947861268565895524228369435954744378689185498362292160793
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.104344237018788490866515875396873948389569507790132720301580385819652701721832
Short name T689
Test name
Test status
Simulation time 119314289 ps
CPU time 1.16 seconds
Started Nov 22 12:25:13 PM PST 23
Finished Nov 22 12:25:15 PM PST 23
Peak memory 195648 kb
Host smart-0105f367-fe60-4de8-b180-c5b7cc6ff7cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104344237018788490866515875396873948389569507790132720301580385819652701721832 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.104344237018788490866515875396873948389569507790132720301580385819652701721832
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.50883973662137398126393228716324889927019364847525944373619847760198631394193
Short name T697
Test name
Test status
Simulation time 134635595 ps
CPU time 2.82 seconds
Started Nov 22 12:25:49 PM PST 23
Finished Nov 22 12:25:53 PM PST 23
Peak memory 197040 kb
Host smart-e947cdef-a6c7-43b7-a073-eaed76008e12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50883973662137398126393228716324889927019364847525944373619847760198
631394193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.50883973662137398126393
228716324889927019364847525944373619847760198631394193
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.65681537096932697830918672539656298486716812796154100263959761512449611456238
Short name T401
Test name
Test status
Simulation time 228920555 ps
CPU time 2.79 seconds
Started Nov 22 12:24:41 PM PST 23
Finished Nov 22 12:24:44 PM PST 23
Peak memory 195732 kb
Host smart-04ff2193-2a20-4dd4-a1fd-b701fd7748da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65681537096932697830918672539656298486716812796154100263959761512449611456238 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.65681537096932697830918672539656298486716812796154100263959761512449611456238
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.109426766423513782069684968406805543291532150066845788022007750513872405067231
Short name T612
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:25:30 PM PST 23
Finished Nov 22 12:25:32 PM PST 23
Peak memory 195708 kb
Host smart-4ce233a4-9d50-44bd-86ac-025bd9f13464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109426766423513782069684968406805543291532150066845788022007750513872405067231 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_random_dout_din.109426766423513782069684968406805543291532150066845788022007750513872405067231
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.106519255736388821468713748439941889296154481811923870176009556058893247157166
Short name T455
Test name
Test status
Simulation time 81278879 ps
CPU time 1.07 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:26:57 PM PST 23
Peak memory 195676 kb
Host smart-2715ec4a-4844-4cf7-b80b-12f8b03301c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106519255736388821468713748439941889296154481811923870176009556058893247157166 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup_pulldown.106519255736388821468713748439941889296154481811923870176009556058893247157166
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.102737113927317673733676239729412365676731826137440437827595981993176998652109
Short name T77
Test name
Test status
Simulation time 572864232 ps
CPU time 4.95 seconds
Started Nov 22 12:26:23 PM PST 23
Finished Nov 22 12:26:33 PM PST 23
Peak memory 197584 kb
Host smart-52d09554-0544-4597-9cd1-e3f856b1b996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102737113927317673733676239729412365676731826137440437827595981993176998652109 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_long_reg_writes_reg_reads.10273711392731767373367623972941236567673182613
7440437827595981993176998652109
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.62565234866628510701444273716187145581769706111143532283203793211932429053755
Short name T463
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:25:00 PM PST 23
Finished Nov 22 12:25:02 PM PST 23
Peak memory 194020 kb
Host smart-7d7d14c8-1e80-40b3-ba34-d9a38eee66e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62565234866628510701444273716187145581769706111143532283203793211932429053755 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.gpio_smoke.62565234866628510701444273716187145581769706111143532283203793211932429053755
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.99381204708506682286368091635124170339652821432680766028398081126221238787429
Short name T270
Test name
Test status
Simulation time 112796484 ps
CPU time 1.37 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:07 PM PST 23
Peak memory 193752 kb
Host smart-2257611f-5055-427e-b616-3c0b1562868f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99381204708506682286368091635124170339652821432680766028398081126221238787429 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.99381204708506682286368091635124170339652821432680766028398081126221238787429
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.64486758509132205767472485514224445839358560195177227950025962985602001092089
Short name T242
Test name
Test status
Simulation time 21104521406 ps
CPU time 174.4 seconds
Started Nov 22 12:25:35 PM PST 23
Finished Nov 22 12:28:36 PM PST 23
Peak memory 198224 kb
Host smart-46e0cb6a-2f52-403e-9f99-f498c8ca2726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6448675850913220576747248551422444583935856019517722795002596298
5602001092089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all.644867585091322057674724855142244458393585601951772279500259629
85602001092089
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.18944241138419765916773669274106386133123362105444156438688702060023775316450
Short name T542
Test name
Test status
Simulation time 133069054254 ps
CPU time 1113.37 seconds
Started Nov 22 12:23:02 PM PST 23
Finished Nov 22 12:41:36 PM PST 23
Peak memory 198120 kb
Host smart-f6ec8d8a-1607-4663-b125-d9775d2670b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=18944241138419765916773669274106386133123362105444156438688702060023775316450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_wi
th_rand_reset.18944241138419765916773669274106386133123362105444156438688702060023775316450
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.108120062489534939983544516563956642405102126380827078250568658986121969691350
Short name T468
Test name
Test status
Simulation time 22440064 ps
CPU time 0.62 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:13 PM PST 23
Peak memory 192964 kb
Host smart-5f32fa15-7549-4075-84a3-0e4d0f23b3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108120062489534939983544516563956642405102126380827078250568658986121969691350 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.108120062489534939983544516563956642405102126380827078250568658986121969691350
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.19754653336548310053128710054177543785852372478353261214396874474659097332480
Short name T287
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:22:48 PM PST 23
Finished Nov 22 12:22:49 PM PST 23
Peak memory 196156 kb
Host smart-76622c9f-075a-495e-b6db-64e2b6ffb03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19754653336548310053128710054177543785852372478353261214396874474659097332480 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.19754653336548310053128710054177543785852372478353261214396874474659097332480
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.38458317928866174606281798051596805465106021575568420535394569872473946308243
Short name T267
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.22 seconds
Started Nov 22 12:27:48 PM PST 23
Finished Nov 22 12:28:16 PM PST 23
Peak memory 193340 kb
Host smart-47fd4b3b-3d1f-411f-8391-d30f7ee598ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458317928866174606281798051596805465106021575568420535394569872473946308243 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stress.38458317928866174606281798051596805465106021575568420535394569872473946308243
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.38959587341052646853626961565578640145127033779363762866639278330123225978401
Short name T716
Test name
Test status
Simulation time 137439144 ps
CPU time 0.94 seconds
Started Nov 22 12:27:22 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 196300 kb
Host smart-66aa1e27-645c-4893-8b35-1d790b8aaadc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38959587341052646853626961565578640145127033779363762866639278330123225978401 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.38959587341052646853626961565578640145127033779363762866639278330123225978401
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.71126148035677194807765474409252560634081321981210920734585150570466984343554
Short name T781
Test name
Test status
Simulation time 119314289 ps
CPU time 1.22 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:04 PM PST 23
Peak memory 195384 kb
Host smart-bfd77db0-4b95-4ed7-bfe0-388eabf381b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71126148035677194807765474409252560634081321981210920734585150570466984343554 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.71126148035677194807765474409252560634081321981210920734585150570466984343554
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.81468458552526113000383922178661336922265143204499036072379246407111410031318
Short name T248
Test name
Test status
Simulation time 134635595 ps
CPU time 2.8 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:27 PM PST 23
Peak memory 197084 kb
Host smart-ec84889e-9477-4051-b265-ac48a1a45a2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81468458552526113000383922178661336922265143204499036072379246407111
410031318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.81468458552526113000383
922178661336922265143204499036072379246407111410031318
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.33694801637664162911058372302931872498680663743280080131134614693916649877446
Short name T662
Test name
Test status
Simulation time 228920555 ps
CPU time 2.87 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:26:04 PM PST 23
Peak memory 194136 kb
Host smart-0bd5974e-f5fb-4f48-b216-e499824520e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694801637664162911058372302931872498680663743280080131134614693916649877446 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.33694801637664162911058372302931872498680663743280080131134614693916649877446
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.14288927806967569841948528089315263766638570761325196071036363114737417363296
Short name T684
Test name
Test status
Simulation time 81278879 ps
CPU time 1.05 seconds
Started Nov 22 12:25:49 PM PST 23
Finished Nov 22 12:25:51 PM PST 23
Peak memory 195644 kb
Host smart-ea031e58-c166-4243-9480-94aecf3b582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14288927806967569841948528089315263766638570761325196071036363114737417363296 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.gpio_random_dout_din.14288927806967569841948528089315263766638570761325196071036363114737417363296
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.6671478795892000692009081861691600495870528481198525125324099910832362675215
Short name T704
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 195564 kb
Host smart-c74a1259-8b26-455a-ad49-61af69086796
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6671478795892000692009081861691600495870528481198525125324099910832362675215 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup_pulldown.6671478795892000692009081861691600495870528481198525125324099910832362675215
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.101247142158057558037488313280695420378203500454329189866395251550954714588273
Short name T291
Test name
Test status
Simulation time 572864232 ps
CPU time 5.15 seconds
Started Nov 22 12:27:48 PM PST 23
Finished Nov 22 12:27:59 PM PST 23
Peak memory 195940 kb
Host smart-1e110fa0-c1e4-4c25-ac63-827604d6410d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101247142158057558037488313280695420378203500454329189866395251550954714588273 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_long_reg_writes_reg_reads.10124714215805755803748831328069542037820350045
4329189866395251550954714588273
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.65593519791084157232529350049237421894817799022507850828740997135645046715871
Short name T399
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:26:11 PM PST 23
Finished Nov 22 12:26:14 PM PST 23
Peak memory 195396 kb
Host smart-68a64e75-62fb-4838-b557-8d7bc127b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65593519791084157232529350049237421894817799022507850828740997135645046715871 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.gpio_smoke.65593519791084157232529350049237421894817799022507850828740997135645046715871
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.92778971094959248387895798372893243587238567660141489904181213475728568527172
Short name T634
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:16 PM PST 23
Peak memory 194540 kb
Host smart-e003fd7c-8761-480f-9672-82c6a5f0d82a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92778971094959248387895798372893243587238567660141489904181213475728568527172 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.92778971094959248387895798372893243587238567660141489904181213475728568527172
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.41460888776295459908525956140880360423935996250810784899005156038696447290990
Short name T518
Test name
Test status
Simulation time 21104521406 ps
CPU time 169.92 seconds
Started Nov 22 12:24:25 PM PST 23
Finished Nov 22 12:27:16 PM PST 23
Peak memory 198024 kb
Host smart-af489200-b9bf-4e97-9a8f-8d41fd4d6986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146088877629545990852595614088036042393599625081078489900515603
8696447290990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all.414608887762954599085259561408803604239359962508107848990051560
38696447290990
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.75487636028226287661252453197491595138157464454704361748040432842030101583871
Short name T768
Test name
Test status
Simulation time 133069054254 ps
CPU time 1097.82 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:44:00 PM PST 23
Peak memory 198168 kb
Host smart-28226016-67eb-42d3-939e-245037a26f43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=75487636028226287661252453197491595138157464454704361748040432842030101583871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_wi
th_rand_reset.75487636028226287661252453197491595138157464454704361748040432842030101583871
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.10341606183645119741798904727997523553493471165228953061242845695653864056171
Short name T794
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:23:45 PM PST 23
Finished Nov 22 12:23:47 PM PST 23
Peak memory 193864 kb
Host smart-5029d5c7-0a38-4977-8cd0-8845fac058ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10341606183645119741798904727997523553493471165228953061242845695653864056171 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.gpio_alert_test.10341606183645119741798904727997523553493471165228953061242845695653864056171
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.112024020897992098097561074566009932477041237163559338932291999985922758922406
Short name T779
Test name
Test status
Simulation time 57921923 ps
CPU time 0.78 seconds
Started Nov 22 12:27:17 PM PST 23
Finished Nov 22 12:27:24 PM PST 23
Peak memory 196136 kb
Host smart-8822af2a-0120-4ae5-863e-8b411aa613a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112024020897992098097561074566009932477041237163559338932291999985922758922406 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.112024020897992098097561074566009932477041237163559338932291999985922758922406
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.112617611652425476252391717949853538523351713352973012291813503033689181677329
Short name T391
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.07 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:40 PM PST 23
Peak memory 195136 kb
Host smart-5b143eae-b97f-41cc-914e-15c47bd9c547
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112617611652425476252391717949853538523351713352973012291813503033689181677329 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stress.112617611652425476252391717949853538523351713352973012291813503033689181677329
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.105489012004285467700458130528957691979346551017657381343932393667420950362088
Short name T595
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 195924 kb
Host smart-f413a9cd-385d-4a04-92ba-b4884e89f144
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105489012004285467700458130528957691979346551017657381343932393667420950362088 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.105489012004285467700458130528957691979346551017657381343932393667420950362088
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.41946805118827276953458357505795498336433789859303078941102596424939632850045
Short name T420
Test name
Test status
Simulation time 119314289 ps
CPU time 1.22 seconds
Started Nov 22 12:23:03 PM PST 23
Finished Nov 22 12:23:05 PM PST 23
Peak memory 195532 kb
Host smart-f2890c79-7181-45fd-be5c-957fd3701dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41946805118827276953458357505795498336433789859303078941102596424939632850045 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.41946805118827276953458357505795498336433789859303078941102596424939632850045
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.77475011751943811484549574278637017978768792434517955069137507047192864534617
Short name T613
Test name
Test status
Simulation time 134635595 ps
CPU time 3.2 seconds
Started Nov 22 12:26:26 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 195360 kb
Host smart-9384d52e-077c-422b-98f0-d3475694302f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77475011751943811484549574278637017978768792434517955069137507047192
864534617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.77475011751943811484549
574278637017978768792434517955069137507047192864534617
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.44358827418720503096798021724174543458411342522226165876951591855838256609258
Short name T690
Test name
Test status
Simulation time 228920555 ps
CPU time 3.1 seconds
Started Nov 22 12:26:26 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 193616 kb
Host smart-27cfa4ef-b283-430a-809f-7079e340987f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44358827418720503096798021724174543458411342522226165876951591855838256609258 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.44358827418720503096798021724174543458411342522226165876951591855838256609258
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.40349039015062568380735109295160107638785734217619937474703673993293840354845
Short name T381
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:25:13 PM PST 23
Finished Nov 22 12:25:15 PM PST 23
Peak memory 195644 kb
Host smart-0a31faae-bf9a-4fa4-b52d-30d2cfd01a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40349039015062568380735109295160107638785734217619937474703673993293840354845 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.gpio_random_dout_din.40349039015062568380735109295160107638785734217619937474703673993293840354845
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.85132005529583804421603726194702419407921075427341544108681230579807129942340
Short name T278
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:25:20 PM PST 23
Finished Nov 22 12:25:22 PM PST 23
Peak memory 194812 kb
Host smart-2febb0b8-8205-4df5-9698-8335673fa69d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85132005529583804421603726194702419407921075427341544108681230579807129942340 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup_pulldown.85132005529583804421603726194702419407921075427341544108681230579807129942340
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.34159881755141231676048530851569320471423818996728491530353638636772847018186
Short name T394
Test name
Test status
Simulation time 572864232 ps
CPU time 4.94 seconds
Started Nov 22 12:27:17 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 197744 kb
Host smart-e4ceaa85-b74e-4fb2-a256-95d72e3a91ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159881755141231676048530851569320471423818996728491530353638636772847018186 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_long_reg_writes_reg_reads.341598817551412316760485308515693204714238189967
28491530353638636772847018186
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.52279527980594638366226409819277353653329059716469080204352531216896844328364
Short name T475
Test name
Test status
Simulation time 112796484 ps
CPU time 1.48 seconds
Started Nov 22 12:26:26 PM PST 23
Finished Nov 22 12:26:32 PM PST 23
Peak memory 193484 kb
Host smart-554cca21-66e2-4dd7-8322-2c3a4cf75380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52279527980594638366226409819277353653329059716469080204352531216896844328364 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.gpio_smoke.52279527980594638366226409819277353653329059716469080204352531216896844328364
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.75104941414381978611815459507052493861007042543433239070298520494469635454900
Short name T222
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:26:24 PM PST 23
Finished Nov 22 12:26:30 PM PST 23
Peak memory 195428 kb
Host smart-deddc8a1-377d-41b4-a985-c67ad2ad07fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75104941414381978611815459507052493861007042543433239070298520494469635454900 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.75104941414381978611815459507052493861007042543433239070298520494469635454900
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.10575417767797080195523386943994568231129941882786101512739812966242995009294
Short name T266
Test name
Test status
Simulation time 21104521406 ps
CPU time 162.18 seconds
Started Nov 22 12:25:22 PM PST 23
Finished Nov 22 12:28:05 PM PST 23
Peak memory 198016 kb
Host smart-3430161f-616a-4d1f-a64a-684adf4389f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057541776779708019552338694399456823112994188278610151273981296
6242995009294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all.105754177677970801955233869439945682311299418827861015127398129
66242995009294
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.18032207300965259494176822057037063618094802458905484631733079120637462097307
Short name T610
Test name
Test status
Simulation time 133069054254 ps
CPU time 1087.82 seconds
Started Nov 22 12:26:26 PM PST 23
Finished Nov 22 12:44:39 PM PST 23
Peak memory 196408 kb
Host smart-299a1f1d-cbf4-4b01-946d-e72454e06eda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=18032207300965259494176822057037063618094802458905484631733079120637462097307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_wi
th_rand_reset.18032207300965259494176822057037063618094802458905484631733079120637462097307
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.60245028943469793259351674839699094011544830448428933959286548224653550193496
Short name T872
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 193444 kb
Host smart-2c2e66fd-64a1-4f68-8701-90b231307b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60245028943469793259351674839699094011544830448428933959286548224653550193496 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.gpio_alert_test.60245028943469793259351674839699094011544830448428933959286548224653550193496
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.99630020818298273899428346200373527555740774301897554733596248559325260979463
Short name T774
Test name
Test status
Simulation time 57921923 ps
CPU time 1.01 seconds
Started Nov 22 12:26:26 PM PST 23
Finished Nov 22 12:26:32 PM PST 23
Peak memory 194384 kb
Host smart-5be153aa-6271-4654-adee-edd89689719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99630020818298273899428346200373527555740774301897554733596248559325260979463 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.99630020818298273899428346200373527555740774301897554733596248559325260979463
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.24296093108710179588987438329422830398509271856141771268954087345580613051227
Short name T737
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.53 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:48 PM PST 23
Peak memory 195148 kb
Host smart-be5a90bf-b547-4626-bcd0-1d478bd507ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296093108710179588987438329422830398509271856141771268954087345580613051227 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stress.24296093108710179588987438329422830398509271856141771268954087345580613051227
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.89856300588177934627602324959799276805807494861638782636263138556348335591770
Short name T412
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:22:34 PM PST 23
Finished Nov 22 12:22:36 PM PST 23
Peak memory 196244 kb
Host smart-daa4fdab-5b19-4a4a-afc6-6d5fda95e19b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89856300588177934627602324959799276805807494861638782636263138556348335591770 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.89856300588177934627602324959799276805807494861638782636263138556348335591770
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.84845425277556125137707055741078590908074415937057129307074479898000884498504
Short name T495
Test name
Test status
Simulation time 119314289 ps
CPU time 1.28 seconds
Started Nov 22 12:24:32 PM PST 23
Finished Nov 22 12:24:34 PM PST 23
Peak memory 195272 kb
Host smart-a10a4b93-456f-4746-b547-95ed914cca65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84845425277556125137707055741078590908074415937057129307074479898000884498504 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.84845425277556125137707055741078590908074415937057129307074479898000884498504
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.16442041999951176018625577815173909366154183054087655749620870094822518327226
Short name T390
Test name
Test status
Simulation time 134635595 ps
CPU time 2.87 seconds
Started Nov 22 12:26:05 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 196908 kb
Host smart-859c0519-2f6d-4592-bc87-1af2043b2e97
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16442041999951176018625577815173909366154183054087655749620870094822
518327226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.16442041999951176018625
577815173909366154183054087655749620870094822518327226
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.75772493961495558724297771948587465768784146899305885792302828616887120675745
Short name T750
Test name
Test status
Simulation time 228920555 ps
CPU time 2.65 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:06 PM PST 23
Peak memory 195268 kb
Host smart-40c4a665-5aa8-4440-8fd8-90bc79e93547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75772493961495558724297771948587465768784146899305885792302828616887120675745 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.75772493961495558724297771948587465768784146899305885792302828616887120675745
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.60904793144918201076008372174143360630690182732991136815045651787581808286217
Short name T398
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:27:02 PM PST 23
Finished Nov 22 12:27:10 PM PST 23
Peak memory 195828 kb
Host smart-0953b1da-da5f-4ae3-bebe-cd5a5bbdda55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60904793144918201076008372174143360630690182732991136815045651787581808286217 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.gpio_random_dout_din.60904793144918201076008372174143360630690182732991136815045651787581808286217
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.78892947252029939494913068619735571608257303055870767175598500124689788065552
Short name T533
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:26:46 PM PST 23
Finished Nov 22 12:26:49 PM PST 23
Peak memory 194604 kb
Host smart-feebe265-cf8b-45e4-bc5f-de6acca96e37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78892947252029939494913068619735571608257303055870767175598500124689788065552 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup_pulldown.78892947252029939494913068619735571608257303055870767175598500124689788065552
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.91317470222364821973211127934882705550277491216273352003657936376069895447809
Short name T663
Test name
Test status
Simulation time 572864232 ps
CPU time 5.4 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:25:47 PM PST 23
Peak memory 197744 kb
Host smart-8ce302f0-3129-4c41-b537-2da4d64bb3ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91317470222364821973211127934882705550277491216273352003657936376069895447809 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_long_reg_writes_reg_reads.913174702223648219732111279348827055502774912162
73352003657936376069895447809
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.28705008682494891188183641270612297293060742718757173414522297884575464085862
Short name T297
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:25:43 PM PST 23
Peak memory 195420 kb
Host smart-1331c9fa-c1ce-4b6f-9907-62f133bed3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28705008682494891188183641270612297293060742718757173414522297884575464085862 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.gpio_smoke.28705008682494891188183641270612297293060742718757173414522297884575464085862
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.52066321721571743221484514522220271708651839240113739286469259487244308639535
Short name T505
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:26:06 PM PST 23
Finished Nov 22 12:26:08 PM PST 23
Peak memory 195280 kb
Host smart-6a2bb854-898f-48ca-abd7-1fc8439496d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52066321721571743221484514522220271708651839240113739286469259487244308639535 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.52066321721571743221484514522220271708651839240113739286469259487244308639535
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.7184496901373437019647732202795490145139421269417580307968491958041827200798
Short name T603
Test name
Test status
Simulation time 21104521406 ps
CPU time 148.77 seconds
Started Nov 22 12:26:50 PM PST 23
Finished Nov 22 12:29:20 PM PST 23
Peak memory 198116 kb
Host smart-e5f10b82-bffa-4be8-b2c2-b8563ba9be7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7184496901373437019647732202795490145139421269417580307968491958
041827200798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all.7184496901373437019647732202795490145139421269417580307968491958041827200798
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2084871604002132655184605075922867339255225054908608971425676537182076038457
Short name T29
Test name
Test status
Simulation time 133069054254 ps
CPU time 1072.93 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:43:35 PM PST 23
Peak memory 198148 kb
Host smart-2b941f60-3bf9-4f29-9773-d06cfe278e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2084871604002132655184605075922867339255225054908608971425676537182076038457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_wit
h_rand_reset.2084871604002132655184605075922867339255225054908608971425676537182076038457
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.56134885417576498558171155182014798054340406918797906864406924350981201601933
Short name T552
Test name
Test status
Simulation time 22440064 ps
CPU time 0.62 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:52 PM PST 23
Peak memory 193864 kb
Host smart-b53805b0-d08e-4c24-b388-b3cbbab88635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56134885417576498558171155182014798054340406918797906864406924350981201601933 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.gpio_alert_test.56134885417576498558171155182014798054340406918797906864406924350981201601933
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.113121388270099433830554120078366415048888226496853146578061014173034436997901
Short name T225
Test name
Test status
Simulation time 57921923 ps
CPU time 0.81 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:01 PM PST 23
Peak memory 196284 kb
Host smart-920d4e5f-f46d-4ced-938c-a4a6095f1cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113121388270099433830554120078366415048888226496853146578061014173034436997901 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.113121388270099433830554120078366415048888226496853146578061014173034436997901
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.66803723504437804636619373217376854670465156343496494995835306508903043233261
Short name T350
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.54 seconds
Started Nov 22 12:26:56 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 195336 kb
Host smart-9ab5e9d8-4484-43bd-a744-ea438070ed22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66803723504437804636619373217376854670465156343496494995835306508903043233261 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress.66803723504437804636619373217376854670465156343496494995835306508903043233261
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.46832229928300502862129946150740017386314044964748907624553765042489818514175
Short name T240
Test name
Test status
Simulation time 137439144 ps
CPU time 1 seconds
Started Nov 22 12:22:42 PM PST 23
Finished Nov 22 12:22:44 PM PST 23
Peak memory 196172 kb
Host smart-3033b266-7a40-43bb-8535-5f526dd4671a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46832229928300502862129946150740017386314044964748907624553765042489818514175 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.46832229928300502862129946150740017386314044964748907624553765042489818514175
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.97342836336948201909313885214893787937399095003792538613279663623046858731539
Short name T561
Test name
Test status
Simulation time 119314289 ps
CPU time 1.2 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:06 PM PST 23
Peak memory 195384 kb
Host smart-36ae50c9-de5d-4e7c-ac15-befb848ad86c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97342836336948201909313885214893787937399095003792538613279663623046858731539 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.97342836336948201909313885214893787937399095003792538613279663623046858731539
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.28705288921210423666621756358856262263732014010401646276547922800709080461724
Short name T788
Test name
Test status
Simulation time 134635595 ps
CPU time 2.91 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:25:45 PM PST 23
Peak memory 197064 kb
Host smart-41bf0838-b256-49f1-86b4-ab4d9005ae2c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705288921210423666621756358856262263732014010401646276547922800709
080461724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.28705288921210423666621
756358856262263732014010401646276547922800709080461724
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.95138858146643585785309668877959726167893844967443473909719686610259575006669
Short name T450
Test name
Test status
Simulation time 228920555 ps
CPU time 2.75 seconds
Started Nov 22 12:26:49 PM PST 23
Finished Nov 22 12:26:54 PM PST 23
Peak memory 195788 kb
Host smart-d3c87732-8bca-4b9a-93a4-173602ae3705
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95138858146643585785309668877959726167893844967443473909719686610259575006669 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.95138858146643585785309668877959726167893844967443473909719686610259575006669
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.72430338521586496875052621086059980533645360193334526367155804625395377249547
Short name T417
Test name
Test status
Simulation time 81278879 ps
CPU time 1.07 seconds
Started Nov 22 12:25:20 PM PST 23
Finished Nov 22 12:25:22 PM PST 23
Peak memory 195308 kb
Host smart-8647b04c-e92d-48d3-952e-b462278a39a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72430338521586496875052621086059980533645360193334526367155804625395377249547 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.gpio_random_dout_din.72430338521586496875052621086059980533645360193334526367155804625395377249547
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.19537924139128466079600388210732354978830952787700467163202982940379957411379
Short name T754
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:26:49 PM PST 23
Finished Nov 22 12:26:52 PM PST 23
Peak memory 195592 kb
Host smart-afca69ea-b904-4ff8-8a7f-7e7aecd82cbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19537924139128466079600388210732354978830952787700467163202982940379957411379 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup_pulldown.19537924139128466079600388210732354978830952787700467163202982940379957411379
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.76337436839611812308909151548908442180996588207304956332813351651478962896074
Short name T265
Test name
Test status
Simulation time 572864232 ps
CPU time 4.97 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 197728 kb
Host smart-0221e6ab-12e5-4352-818d-a5f2f0669d7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76337436839611812308909151548908442180996588207304956332813351651478962896074 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_long_reg_writes_reg_reads.763374368396118123089091515489084421809965882073
04956332813351651478962896074
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.85653733213593165890318777751952207091944225029816229090238520862524377992469
Short name T842
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:05 PM PST 23
Finished Nov 22 12:26:08 PM PST 23
Peak memory 195300 kb
Host smart-716f5d8d-edf4-48d9-9274-f3db17957720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85653733213593165890318777751952207091944225029816229090238520862524377992469 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.gpio_smoke.85653733213593165890318777751952207091944225029816229090238520862524377992469
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4706126850914130268525411077606851226981971605768359149840062052454846900128
Short name T876
Test name
Test status
Simulation time 112796484 ps
CPU time 1.23 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 195104 kb
Host smart-dedfc46b-9b24-47f1-873e-63bbca7e10ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4706126850914130268525411077606851226981971605768359149840062052454846900128 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4706126850914130268525411077606851226981971605768359149840062052454846900128
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.106872314335829064849204321610500460471709549321397411642256995482533740339750
Short name T511
Test name
Test status
Simulation time 21104521406 ps
CPU time 153.67 seconds
Started Nov 22 12:26:46 PM PST 23
Finished Nov 22 12:29:22 PM PST 23
Peak memory 197064 kb
Host smart-071b0879-1996-45bf-8d7e-c29f708cc055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068723143358290648492043216105004604717095493213974116422569954
82533740339750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all.10687231433582906484920432161050046047170954932139741164225699
5482533740339750
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.88564342567569242392783437025897607574678634577927164521779454375194858418334
Short name T334
Test name
Test status
Simulation time 133069054254 ps
CPU time 1137.01 seconds
Started Nov 22 12:22:42 PM PST 23
Finished Nov 22 12:41:39 PM PST 23
Peak memory 198104 kb
Host smart-d5b38a8a-f268-4e71-8a7c-63c5bbb71699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=88564342567569242392783437025897607574678634577927164521779454375194858418334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_wi
th_rand_reset.88564342567569242392783437025897607574678634577927164521779454375194858418334
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.109223050798121220672774329529122922526717121010383048515134182960381357828633
Short name T315
Test name
Test status
Simulation time 22440064 ps
CPU time 0.76 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:40 PM PST 23
Peak memory 190296 kb
Host smart-4db20b6a-779f-4b19-b4b1-6b18582e8143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109223050798121220672774329529122922526717121010383048515134182960381357828633 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.109223050798121220672774329529122922526717121010383048515134182960381357828633
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.11749058357758823216710919961995990282199576460340709956861082802692529134834
Short name T861
Test name
Test status
Simulation time 57921923 ps
CPU time 0.9 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 195736 kb
Host smart-5a34712a-64ec-4c6d-82fe-f711d0a8677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11749058357758823216710919961995990282199576460340709956861082802692529134834 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.11749058357758823216710919961995990282199576460340709956861082802692529134834
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.28306642664943938156262975926991623003994345275143354249363121609621468676896
Short name T256
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.65 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:27:45 PM PST 23
Peak memory 195432 kb
Host smart-eae87be4-c116-42ee-9b92-0b9c903c0f3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306642664943938156262975926991623003994345275143354249363121609621468676896 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stress.28306642664943938156262975926991623003994345275143354249363121609621468676896
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.48291019143354188848990746889684338479159038793932961825683766879559473009857
Short name T621
Test name
Test status
Simulation time 137439144 ps
CPU time 1.17 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:41 PM PST 23
Peak memory 192836 kb
Host smart-30632443-6d89-4f43-9df3-02a994dc2de6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48291019143354188848990746889684338479159038793932961825683766879559473009857 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.48291019143354188848990746889684338479159038793932961825683766879559473009857
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.48165170054179007493615188595266370971093241296496346537182596572973133351193
Short name T491
Test name
Test status
Simulation time 119314289 ps
CPU time 1.27 seconds
Started Nov 22 12:22:24 PM PST 23
Finished Nov 22 12:22:26 PM PST 23
Peak memory 195644 kb
Host smart-0ed11713-f11b-4225-86b1-906a12b4e82f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48165170054179007493615188595266370971093241296496346537182596572973133351193 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.48165170054179007493615188595266370971093241296496346537182596572973133351193
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.72855035633116043052208884998781774161512122378036493077954724887009335392541
Short name T389
Test name
Test status
Simulation time 134635595 ps
CPU time 2.83 seconds
Started Nov 22 12:26:14 PM PST 23
Finished Nov 22 12:26:20 PM PST 23
Peak memory 196772 kb
Host smart-4af6bf4b-e533-4bc0-8f4c-5ceed27e2ccd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72855035633116043052208884998781774161512122378036493077954724887009
335392541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.72855035633116043052208
884998781774161512122378036493077954724887009335392541
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.102878955155788372455760952976466930984759546013213899904367647471156175511586
Short name T289
Test name
Test status
Simulation time 228920555 ps
CPU time 2.69 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:29 PM PST 23
Peak memory 195424 kb
Host smart-5a2dd0d8-7f49-40e7-8337-d286517806c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102878955155788372455760952976466930984759546013213899904367647471156175511586 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.102878955155788372455760952976466930984759546013213899904367647471156175511586
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.97679915011517443944048497730961219225966780947150376919607791774866070776188
Short name T832
Test name
Test status
Simulation time 81278879 ps
CPU time 1.22 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 194828 kb
Host smart-7437fb51-6e33-43a6-bc71-884feba47955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97679915011517443944048497730961219225966780947150376919607791774866070776188 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.gpio_random_dout_din.97679915011517443944048497730961219225966780947150376919607791774866070776188
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2810819446212246065648957424045994403685520577034960391803140917313705367682
Short name T859
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 195420 kb
Host smart-bb262476-f440-4f9a-9474-86044f64e595
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810819446212246065648957424045994403685520577034960391803140917313705367682 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_pulldown.2810819446212246065648957424045994403685520577034960391803140917313705367682
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.43135499221984301587267746570132921993298433039270750542389333934177803924435
Short name T699
Test name
Test status
Simulation time 572864232 ps
CPU time 5.49 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:45 PM PST 23
Peak memory 194864 kb
Host smart-6a998cd6-e8c8-4a43-9678-e234eecaf96c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43135499221984301587267746570132921993298433039270750542389333934177803924435 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_long_reg_writes_reg_reads.431354992219843015872677465701329219932984330392
70750542389333934177803924435
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.87221871308057986893314677722382303302875370331199183947742979179469933833881
Short name T783
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:49 PM PST 23
Finished Nov 22 12:26:52 PM PST 23
Peak memory 195108 kb
Host smart-075fb018-435f-42ed-8c67-4fdb4e11e1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87221871308057986893314677722382303302875370331199183947742979179469933833881 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.gpio_smoke.87221871308057986893314677722382303302875370331199183947742979179469933833881
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.16124996165601493609747574970339446385008516561617383662788960953403114510528
Short name T523
Test name
Test status
Simulation time 112796484 ps
CPU time 1.48 seconds
Started Nov 22 12:27:08 PM PST 23
Finished Nov 22 12:27:16 PM PST 23
Peak memory 195428 kb
Host smart-53446958-86ba-47dc-ad98-28944456fa4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124996165601493609747574970339446385008516561617383662788960953403114510528 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.16124996165601493609747574970339446385008516561617383662788960953403114510528
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.59501382792674970521764373379880996011099152794030521545651456442754702779685
Short name T625
Test name
Test status
Simulation time 21104521406 ps
CPU time 170.21 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:30:30 PM PST 23
Peak memory 194404 kb
Host smart-b47a3b01-801b-4c4a-b029-3e6445b1c6e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5950138279267497052176437337988099601109915279403052154565145644
2754702779685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all.595013827926749705217643733798809960110991527940305215456514564
42754702779685
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.16655708844685683287093165361711376741259701628757137510237841017031579110118
Short name T799
Test name
Test status
Simulation time 133069054254 ps
CPU time 1090.59 seconds
Started Nov 22 12:23:07 PM PST 23
Finished Nov 22 12:41:19 PM PST 23
Peak memory 198204 kb
Host smart-1558650b-f805-4ada-88b5-107a5df9cc5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=16655708844685683287093165361711376741259701628757137510237841017031579110118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_wi
th_rand_reset.16655708844685683287093165361711376741259701628757137510237841017031579110118
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.71856248658225555306992820129064138721130308333960087280261490019738412618849
Short name T695
Test name
Test status
Simulation time 22440064 ps
CPU time 0.61 seconds
Started Nov 22 12:25:56 PM PST 23
Finished Nov 22 12:25:58 PM PST 23
Peak memory 192956 kb
Host smart-cd8466cc-1cf2-4112-8e88-d4f7187176bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71856248658225555306992820129064138721130308333960087280261490019738412618849 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.gpio_alert_test.71856248658225555306992820129064138721130308333960087280261490019738412618849
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.47835691176320512474961306690563864514767912277716451790804830587738571752626
Short name T692
Test name
Test status
Simulation time 57921923 ps
CPU time 0.96 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:15 PM PST 23
Peak memory 196188 kb
Host smart-82d19294-ccbe-44f0-8722-611c9f52c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47835691176320512474961306690563864514767912277716451790804830587738571752626 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.47835691176320512474961306690563864514767912277716451790804830587738571752626
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.90783439996585317473310846178152929911653008919519496605679296700992941167327
Short name T349
Test name
Test status
Simulation time 1135699015 ps
CPU time 23.16 seconds
Started Nov 22 12:23:07 PM PST 23
Finished Nov 22 12:23:30 PM PST 23
Peak memory 195432 kb
Host smart-6b95d35f-95ba-43db-926e-e7553a7b360e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90783439996585317473310846178152929911653008919519496605679296700992941167327 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress.90783439996585317473310846178152929911653008919519496605679296700992941167327
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3255643829250048611689581709953717198367707357510310413713170521759599533019
Short name T58
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:26:00 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 195100 kb
Host smart-d4bb9990-7439-4408-a9de-84f552816133
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255643829250048611689581709953717198367707357510310413713170521759599533019 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3255643829250048611689581709953717198367707357510310413713170521759599533019
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.71814421119661075517714898238379016996896845723231888393202865878045612068351
Short name T309
Test name
Test status
Simulation time 119314289 ps
CPU time 1.17 seconds
Started Nov 22 12:26:02 PM PST 23
Finished Nov 22 12:26:04 PM PST 23
Peak memory 195412 kb
Host smart-ffb2cbfb-de95-445e-8ae0-c3ed5d130d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71814421119661075517714898238379016996896845723231888393202865878045612068351 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.71814421119661075517714898238379016996896845723231888393202865878045612068351
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.5791429681955219252362441669533313558990016631927586286921187837120068072111
Short name T827
Test name
Test status
Simulation time 134635595 ps
CPU time 2.98 seconds
Started Nov 22 12:26:04 PM PST 23
Finished Nov 22 12:26:09 PM PST 23
Peak memory 196648 kb
Host smart-2272fd1f-02b5-405e-8f35-50e3b17e14e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57914296819552192523624416695333135589900166319275862869211878371200
68072111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.579142968195521925236244
1669533313558990016631927586286921187837120068072111
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.89028760906042438321899459233597767761941081265952303961002453387869312472929
Short name T499
Test name
Test status
Simulation time 228920555 ps
CPU time 2.76 seconds
Started Nov 22 12:27:41 PM PST 23
Finished Nov 22 12:27:52 PM PST 23
Peak memory 193976 kb
Host smart-270c4ea8-7279-49ec-8301-341f64ad9d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89028760906042438321899459233597767761941081265952303961002453387869312472929 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.89028760906042438321899459233597767761941081265952303961002453387869312472929
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.41522341022992416115386078536064855248681651147504957996064438151036558481878
Short name T548
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:26:00 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 194576 kb
Host smart-e87392bb-ff4d-48b7-8d60-b39f0cc27d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41522341022992416115386078536064855248681651147504957996064438151036558481878 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.gpio_random_dout_din.41522341022992416115386078536064855248681651147504957996064438151036558481878
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.38699301231641280234286237510981226869036144006025448116287925057958402374819
Short name T385
Test name
Test status
Simulation time 81278879 ps
CPU time 1.1 seconds
Started Nov 22 12:22:55 PM PST 23
Finished Nov 22 12:22:56 PM PST 23
Peak memory 195704 kb
Host smart-b3cb27f6-ac5d-4635-b80d-1fb01aeaa58a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699301231641280234286237510981226869036144006025448116287925057958402374819 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup_pulldown.38699301231641280234286237510981226869036144006025448116287925057958402374819
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.6046493391056592526338518688004077314598677869665830153941464373827899199606
Short name T469
Test name
Test status
Simulation time 572864232 ps
CPU time 5.14 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:45 PM PST 23
Peak memory 195248 kb
Host smart-2ba29c72-344f-4cb7-8a87-c8a06ee48240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6046493391056592526338518688004077314598677869665830153941464373827899199606 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_long_reg_writes_reg_reads.6046493391056592526338518688004077314598677869665
830153941464373827899199606
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.4563867059880728934723505756448543963107987145233702078973976169740785913750
Short name T415
Test name
Test status
Simulation time 112796484 ps
CPU time 1.23 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:17 PM PST 23
Peak memory 195432 kb
Host smart-e1b4f8ab-dc82-42df-adf0-a7db797fd0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4563867059880728934723505756448543963107987145233702078973976169740785913750 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.gpio_smoke.4563867059880728934723505756448543963107987145233702078973976169740785913750
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.39368596344013440730711670223913090810788831423806937751883744398956308608615
Short name T609
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 195460 kb
Host smart-55bfe839-757a-4254-bf3f-2e8555809f10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39368596344013440730711670223913090810788831423806937751883744398956308608615 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.39368596344013440730711670223913090810788831423806937751883744398956308608615
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.29933103223813148822665778745314895916283125411472577473131474522530986134141
Short name T819
Test name
Test status
Simulation time 21104521406 ps
CPU time 168.62 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 195000 kb
Host smart-29058e96-9742-43c0-b4da-1f661bc8f12a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993310322381314882266577874531489591628312541147257747313147452
2530986134141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all.299331032238131488226657787453148959162831254114725774731314745
22530986134141
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.18835166981775134859911211567088540057377239960293290845658007419796240127597
Short name T383
Test name
Test status
Simulation time 133069054254 ps
CPU time 1142.26 seconds
Started Nov 22 12:27:41 PM PST 23
Finished Nov 22 12:46:51 PM PST 23
Peak memory 196560 kb
Host smart-6c86ac9f-08f6-4e74-8162-f94f27385f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=18835166981775134859911211567088540057377239960293290845658007419796240127597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_wi
th_rand_reset.18835166981775134859911211567088540057377239960293290845658007419796240127597
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.28932972508770026852526251292891201005800711068413615868941992171472459182273
Short name T261
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:25:42 PM PST 23
Peak memory 193824 kb
Host smart-1543cb5f-8e3f-45ac-ae79-798d382d7109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28932972508770026852526251292891201005800711068413615868941992171472459182273 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.gpio_alert_test.28932972508770026852526251292891201005800711068413615868941992171472459182273
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.50954502413580337031090380064349835559341011230420733470710425010653796309332
Short name T404
Test name
Test status
Simulation time 57921923 ps
CPU time 0.8 seconds
Started Nov 22 12:26:11 PM PST 23
Finished Nov 22 12:26:13 PM PST 23
Peak memory 196168 kb
Host smart-07dbc451-ea14-47d1-9283-036d66b6e5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50954502413580337031090380064349835559341011230420733470710425010653796309332 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.50954502413580337031090380064349835559341011230420733470710425010653796309332
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.56763299828781258654686225772133079184624756369351806298047589240442942677744
Short name T255
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.38 seconds
Started Nov 22 12:26:22 PM PST 23
Finished Nov 22 12:26:49 PM PST 23
Peak memory 195432 kb
Host smart-1e6d9381-a703-4a33-8bd4-6408f60f83a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56763299828781258654686225772133079184624756369351806298047589240442942677744 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stress.56763299828781258654686225772133079184624756369351806298047589240442942677744
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.15011182197603829712843443881549546974407646761068410208561976301425770734033
Short name T223
Test name
Test status
Simulation time 137439144 ps
CPU time 1.03 seconds
Started Nov 22 12:23:31 PM PST 23
Finished Nov 22 12:23:33 PM PST 23
Peak memory 196240 kb
Host smart-865c86f8-7610-4f16-a8ba-6ebd9ad78b5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15011182197603829712843443881549546974407646761068410208561976301425770734033 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.15011182197603829712843443881549546974407646761068410208561976301425770734033
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.33071555668219957069841935362377370737910446112356566613643917800933858393331
Short name T433
Test name
Test status
Simulation time 119314289 ps
CPU time 1.23 seconds
Started Nov 22 12:25:58 PM PST 23
Finished Nov 22 12:26:01 PM PST 23
Peak memory 195516 kb
Host smart-8eef4312-e31e-489c-81eb-797a4095af8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071555668219957069841935362377370737910446112356566613643917800933858393331 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.33071555668219957069841935362377370737910446112356566613643917800933858393331
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.58134040277070907105816981477663994161114144359529131598953820542100200982989
Short name T428
Test name
Test status
Simulation time 134635595 ps
CPU time 2.86 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 196924 kb
Host smart-67da2c77-e220-4acd-83ab-7ccdc6b3d0f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58134040277070907105816981477663994161114144359529131598953820542100
200982989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.58134040277070907105816
981477663994161114144359529131598953820542100200982989
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.64579638148282929031742102929904081895767405808709909065203568797118964031796
Short name T206
Test name
Test status
Simulation time 228920555 ps
CPU time 2.89 seconds
Started Nov 22 12:26:06 PM PST 23
Finished Nov 22 12:26:10 PM PST 23
Peak memory 195472 kb
Host smart-dd9c2271-b8d5-4234-9260-a0f543709e49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64579638148282929031742102929904081895767405808709909065203568797118964031796 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.64579638148282929031742102929904081895767405808709909065203568797118964031796
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.85586853359937560187426990917317523640695251091429114797385609659085705979567
Short name T400
Test name
Test status
Simulation time 81278879 ps
CPU time 1.16 seconds
Started Nov 22 12:23:57 PM PST 23
Finished Nov 22 12:24:02 PM PST 23
Peak memory 195700 kb
Host smart-400c69d3-be00-4859-978b-e02a67fc9c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85586853359937560187426990917317523640695251091429114797385609659085705979567 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.gpio_random_dout_din.85586853359937560187426990917317523640695251091429114797385609659085705979567
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.41969324261525815034150865177279987097962973293100908305533365463120411377461
Short name T578
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:09 PM PST 23
Peak memory 195580 kb
Host smart-846f1ddb-4eaa-4a9e-a8c8-9c1aa8ff7591
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41969324261525815034150865177279987097962973293100908305533365463120411377461 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_pulldown.41969324261525815034150865177279987097962973293100908305533365463120411377461
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.86891892617076598778979386725857682212623118790610149851813767121884022178175
Short name T567
Test name
Test status
Simulation time 572864232 ps
CPU time 5.01 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:19 PM PST 23
Peak memory 197724 kb
Host smart-4f55b655-d78f-4b4f-a593-74c961bd8315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86891892617076598778979386725857682212623118790610149851813767121884022178175 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_long_reg_writes_reg_reads.868918926170765987789793867258576822126231187906
10149851813767121884022178175
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.55319054420234269043710786903460734244190663406393212578542015836312399630687
Short name T581
Test name
Test status
Simulation time 112796484 ps
CPU time 1.41 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:41 PM PST 23
Peak memory 193108 kb
Host smart-3c900b71-b37e-45aa-9289-cfb3796a6030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55319054420234269043710786903460734244190663406393212578542015836312399630687 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.gpio_smoke.55319054420234269043710786903460734244190663406393212578542015836312399630687
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.27853839404303587949703086950025143593030258077749009708113786110751775003675
Short name T585
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:24:01 PM PST 23
Finished Nov 22 12:24:03 PM PST 23
Peak memory 195484 kb
Host smart-41d7ff49-a07b-4d22-b495-e302381d5ef2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27853839404303587949703086950025143593030258077749009708113786110751775003675 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.27853839404303587949703086950025143593030258077749009708113786110751775003675
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.55798978918906872637162859741429610624297371392291138675414129513989386831485
Short name T301
Test name
Test status
Simulation time 21104521406 ps
CPU time 163.16 seconds
Started Nov 22 12:27:45 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 198020 kb
Host smart-9ee7e79d-993f-4b0b-be7d-5e25e33cb402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5579897891890687263716285974142961062429737139229113867541412951
3989386831485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all.557989789189068726371628597414296106242973713922911386754141295
13989386831485
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.48998028397271930991339306278178054992799212739563701779828682878392406199407
Short name T869
Test name
Test status
Simulation time 133069054254 ps
CPU time 1144.71 seconds
Started Nov 22 12:26:27 PM PST 23
Finished Nov 22 12:45:36 PM PST 23
Peak memory 198260 kb
Host smart-96e65046-e6d5-47c3-af65-de13139a0033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=48998028397271930991339306278178054992799212739563701779828682878392406199407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_wi
th_rand_reset.48998028397271930991339306278178054992799212739563701779828682878392406199407
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.60293792728401862980634478942429797899933621612972202175072998932114530986585
Short name T835
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:25:53 PM PST 23
Finished Nov 22 12:25:55 PM PST 23
Peak memory 193932 kb
Host smart-1dd027bc-10fb-4cb5-beea-01823437d55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60293792728401862980634478942429797899933621612972202175072998932114530986585 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.gpio_alert_test.60293792728401862980634478942429797899933621612972202175072998932114530986585
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.31437252528618320861733555454552022553756662510723178701955168707378336986064
Short name T228
Test name
Test status
Simulation time 57921923 ps
CPU time 0.89 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 196136 kb
Host smart-da8da235-6f91-4ec7-ab4f-b5f1326c4b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31437252528618320861733555454552022553756662510723178701955168707378336986064 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.31437252528618320861733555454552022553756662510723178701955168707378336986064
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.30676484401190075686306385393073746203333119499146140225072117804728065480761
Short name T849
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.96 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:28 PM PST 23
Peak memory 195140 kb
Host smart-8c388030-ab8e-4920-ad3f-029f9573a328
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30676484401190075686306385393073746203333119499146140225072117804728065480761 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stress.30676484401190075686306385393073746203333119499146140225072117804728065480761
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.115275820762711946932428995822741287888927195124582602664784686981144335116855
Short name T679
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:25:24 PM PST 23
Finished Nov 22 12:25:25 PM PST 23
Peak memory 196324 kb
Host smart-27d83c55-be0e-459c-a292-afac2a329549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115275820762711946932428995822741287888927195124582602664784686981144335116855 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.115275820762711946932428995822741287888927195124582602664784686981144335116855
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.103127622207641034005041905744156402443971258775012321909430400631762583001476
Short name T658
Test name
Test status
Simulation time 119314289 ps
CPU time 1.18 seconds
Started Nov 22 12:25:38 PM PST 23
Finished Nov 22 12:25:43 PM PST 23
Peak memory 195672 kb
Host smart-0d82b477-dc8b-480c-a2a0-c9cd19b7e2fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103127622207641034005041905744156402443971258775012321909430400631762583001476 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.103127622207641034005041905744156402443971258775012321909430400631762583001476
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.6487448779827223260515010062404652593420335459252747768873634926128739879654
Short name T243
Test name
Test status
Simulation time 134635595 ps
CPU time 2.94 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 196808 kb
Host smart-84a936d6-bf2f-415b-af49-b0b88789ee55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64874487798272232605150100624046525934203354592527477688736349261287
39879654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.648744877982722326051501
0062404652593420335459252747768873634926128739879654
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.89138270061775202651049705414487496002217049315764464179576637364454310281141
Short name T657
Test name
Test status
Simulation time 228920555 ps
CPU time 2.94 seconds
Started Nov 22 12:23:11 PM PST 23
Finished Nov 22 12:23:14 PM PST 23
Peak memory 195732 kb
Host smart-b6e2a025-d349-469b-9786-a15c81f49011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89138270061775202651049705414487496002217049315764464179576637364454310281141 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.89138270061775202651049705414487496002217049315764464179576637364454310281141
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.21713472470759664422042484085398553127644386801725215261857664216858874589671
Short name T218
Test name
Test status
Simulation time 81278879 ps
CPU time 1.07 seconds
Started Nov 22 12:27:37 PM PST 23
Finished Nov 22 12:27:48 PM PST 23
Peak memory 195704 kb
Host smart-e8b83755-8125-4881-8424-15874774fe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21713472470759664422042484085398553127644386801725215261857664216858874589671 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.gpio_random_dout_din.21713472470759664422042484085398553127644386801725215261857664216858874589671
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.59593215504049358427055113703445790912276071269925878579420669651896499506913
Short name T850
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:09 PM PST 23
Peak memory 195580 kb
Host smart-5f01736f-a7f4-4a62-a96f-a924d5bc0344
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59593215504049358427055113703445790912276071269925878579420669651896499506913 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_pulldown.59593215504049358427055113703445790912276071269925878579420669651896499506913
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.25997123388792810511308745934267300606244071840924948296738706041981442478127
Short name T368
Test name
Test status
Simulation time 572864232 ps
CPU time 5.25 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 197736 kb
Host smart-5caa3fa9-c82b-4a3a-be45-e416f70ae136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25997123388792810511308745934267300606244071840924948296738706041981442478127 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_long_reg_writes_reg_reads.259971233887928105113087459342673006062440718409
24948296738706041981442478127
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.61519205977448272191294075117643959437356226563302890684448478156623431725298
Short name T535
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 194324 kb
Host smart-75b3be16-2ea6-4d8d-b894-98a3b834eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61519205977448272191294075117643959437356226563302890684448478156623431725298 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.gpio_smoke.61519205977448272191294075117643959437356226563302890684448478156623431725298
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.12120195594666973870252848399625168637040546691423751816658047225816244335599
Short name T506
Test name
Test status
Simulation time 112796484 ps
CPU time 1.31 seconds
Started Nov 22 12:22:52 PM PST 23
Finished Nov 22 12:22:54 PM PST 23
Peak memory 195456 kb
Host smart-9e927359-9e84-465a-980c-9e191470118a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120195594666973870252848399625168637040546691423751816658047225816244335599 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.12120195594666973870252848399625168637040546691423751816658047225816244335599
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.12492132066802186899492435964173771230369089018476908796597632755950466223570
Short name T439
Test name
Test status
Simulation time 21104521406 ps
CPU time 170.5 seconds
Started Nov 22 12:25:22 PM PST 23
Finished Nov 22 12:28:13 PM PST 23
Peak memory 197988 kb
Host smart-451ae85b-76b2-460c-9f6f-e6eadd93a254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249213206680218689949243596417377123036908901847690879659763275
5950466223570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all.124921320668021868994924359641737712303690890184769087965976327
55950466223570
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.50564549789763034437471523700604289128711795013943768053247705802350704074470
Short name T392
Test name
Test status
Simulation time 133069054254 ps
CPU time 1072.7 seconds
Started Nov 22 12:27:45 PM PST 23
Finished Nov 22 12:45:44 PM PST 23
Peak memory 198180 kb
Host smart-fd1447a7-8d58-4de3-a78c-7ed4f04b738a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=50564549789763034437471523700604289128711795013943768053247705802350704074470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_wi
th_rand_reset.50564549789763034437471523700604289128711795013943768053247705802350704074470
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.26781060409525949548893571617944230032709906390583706528970433682348055310503
Short name T693
Test name
Test status
Simulation time 22440064 ps
CPU time 0.58 seconds
Started Nov 22 12:27:49 PM PST 23
Finished Nov 22 12:27:54 PM PST 23
Peak memory 193668 kb
Host smart-97fc933c-81d2-4b98-9383-5c1e7a63208a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781060409525949548893571617944230032709906390583706528970433682348055310503 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.gpio_alert_test.26781060409525949548893571617944230032709906390583706528970433682348055310503
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.27785416592441548424069273044170626497783377544573708548681435974444172262465
Short name T351
Test name
Test status
Simulation time 57921923 ps
CPU time 0.92 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:11 PM PST 23
Peak memory 195768 kb
Host smart-6bb0abad-9951-4516-8bc3-8b39165b3669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27785416592441548424069273044170626497783377544573708548681435974444172262465 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.27785416592441548424069273044170626497783377544573708548681435974444172262465
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.45305489890955960440391809495417392639133025226615498818139807890187371004930
Short name T614
Test name
Test status
Simulation time 1135699015 ps
CPU time 23.42 seconds
Started Nov 22 12:21:52 PM PST 23
Finished Nov 22 12:22:16 PM PST 23
Peak memory 195400 kb
Host smart-91e63938-7f01-4a16-a0b3-f5c4652b439e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45305489890955960440391809495417392639133025226615498818139807890187371004930 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress.45305489890955960440391809495417392639133025226615498818139807890187371004930
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.82554245653820496809311206638433934346849966310027040709786136381840709966983
Short name T822
Test name
Test status
Simulation time 137439144 ps
CPU time 1.01 seconds
Started Nov 22 12:23:40 PM PST 23
Finished Nov 22 12:23:42 PM PST 23
Peak memory 196312 kb
Host smart-406287aa-a49b-4f0f-b4db-46e66658a12a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82554245653820496809311206638433934346849966310027040709786136381840709966983 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.82554245653820496809311206638433934346849966310027040709786136381840709966983
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.52007767162919050895319029763424913209554791944936755146682638638121953413921
Short name T789
Test name
Test status
Simulation time 119314289 ps
CPU time 1.18 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 195700 kb
Host smart-12640242-07b1-47e1-8e71-61d3298e8f70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52007767162919050895319029763424913209554791944936755146682638638121953413921 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.52007767162919050895319029763424913209554791944936755146682638638121953413921
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.20343698243267128755001513308346398548860265374609718201193613292264911673912
Short name T81
Test name
Test status
Simulation time 134635595 ps
CPU time 3.18 seconds
Started Nov 22 12:25:42 PM PST 23
Finished Nov 22 12:25:49 PM PST 23
Peak memory 197116 kb
Host smart-4384daef-3927-4876-a978-a8e4f5e8d3c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20343698243267128755001513308346398548860265374609718201193613292264
911673912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.203436982432671287550015
13308346398548860265374609718201193613292264911673912
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.21236329953565052535111474230644844559701331376313038824888936500922636210397
Short name T210
Test name
Test status
Simulation time 228920555 ps
CPU time 3 seconds
Started Nov 22 12:26:36 PM PST 23
Finished Nov 22 12:26:40 PM PST 23
Peak memory 195724 kb
Host smart-a05ad287-07c8-4281-99f2-f95326e32694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236329953565052535111474230644844559701331376313038824888936500922636210397 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.21236329953565052535111474230644844559701331376313038824888936500922636210397
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.88562082334207683210508031622995530703178784647892225883321369951455175960354
Short name T288
Test name
Test status
Simulation time 81278879 ps
CPU time 1.07 seconds
Started Nov 22 12:21:44 PM PST 23
Finished Nov 22 12:21:47 PM PST 23
Peak memory 195668 kb
Host smart-a1e1093e-71fa-4342-9917-e5a8c3f23639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88562082334207683210508031622995530703178784647892225883321369951455175960354 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.gpio_random_dout_din.88562082334207683210508031622995530703178784647892225883321369951455175960354
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.93765660995201941476557441620386290585045779773976436595290542260021474398254
Short name T286
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 195276 kb
Host smart-da1615c0-d647-4de5-980b-e1da3b26111f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93765660995201941476557441620386290585045779773976436595290542260021474398254 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_pulldown.93765660995201941476557441620386290585045779773976436595290542260021474398254
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.99316075234383730859333681173712749149269072993111172522475005956408282472242
Short name T760
Test name
Test status
Simulation time 572864232 ps
CPU time 5.32 seconds
Started Nov 22 12:23:11 PM PST 23
Finished Nov 22 12:23:17 PM PST 23
Peak memory 197736 kb
Host smart-70cab681-7858-41ca-a6e0-93291be94039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99316075234383730859333681173712749149269072993111172522475005956408282472242 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_long_reg_writes_reg_reads.9931607523438373085933368117371274914926907299311
1172522475005956408282472242
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.54619791556748974523808851673669144620720896927010424992625936827076918588823
Short name T73
Test name
Test status
Simulation time 134885593 ps
CPU time 0.95 seconds
Started Nov 22 12:21:44 PM PST 23
Finished Nov 22 12:21:46 PM PST 23
Peak memory 214588 kb
Host smart-b3fceb40-7c2d-4ff5-95f8-e6d6f1dbcd2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54619791556748974523808851673669144620720896927010424992625936827076918588823 -assert nopostpro
c +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.gpio_sec_cm.54619791556748974523808851673669144620720896927010424992625936827076918588823
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.23022725546785669188449794121577096902989786253119553277539319115895227890987
Short name T292
Test name
Test status
Simulation time 112796484 ps
CPU time 1.35 seconds
Started Nov 22 12:25:06 PM PST 23
Finished Nov 22 12:25:08 PM PST 23
Peak memory 195400 kb
Host smart-0ee54326-d096-4189-9e0b-614dd7753a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23022725546785669188449794121577096902989786253119553277539319115895227890987 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.gpio_smoke.23022725546785669188449794121577096902989786253119553277539319115895227890987
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.45457822077739659173847432600551367468677211447883110613715513784508525888151
Short name T476
Test name
Test status
Simulation time 112796484 ps
CPU time 1.2 seconds
Started Nov 22 12:27:13 PM PST 23
Finished Nov 22 12:27:21 PM PST 23
Peak memory 195136 kb
Host smart-b72ddfeb-56d9-4ca8-a42f-32e9aa7f320a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45457822077739659173847432600551367468677211447883110613715513784508525888151 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.45457822077739659173847432600551367468677211447883110613715513784508525888151
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.79579045927742555020559379508932184460198063168240480529193542855854990892175
Short name T605
Test name
Test status
Simulation time 21104521406 ps
CPU time 150.56 seconds
Started Nov 22 12:27:08 PM PST 23
Finished Nov 22 12:29:46 PM PST 23
Peak memory 197012 kb
Host smart-3b1a9809-9a13-4821-9e97-26ecd4ab63b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7957904592774255502055937950893218446019806316824048052919354285
5854990892175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all.7957904592774255502055937950893218446019806316824048052919354285
5854990892175
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.12534527300041808908049305271177294680169589425487516621655924008931274615571
Short name T314
Test name
Test status
Simulation time 133069054254 ps
CPU time 1052.73 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:44:54 PM PST 23
Peak memory 197876 kb
Host smart-289a97e9-5107-47bd-aa61-a9e2dd6bbf23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=12534527300041808908049305271177294680169589425487516621655924008931274615571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_wit
h_rand_reset.12534527300041808908049305271177294680169589425487516621655924008931274615571
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.91562347434135521565091824536854111314337063518535592310253871805558289990270
Short name T571
Test name
Test status
Simulation time 22440064 ps
CPU time 0.57 seconds
Started Nov 22 12:26:33 PM PST 23
Finished Nov 22 12:26:35 PM PST 23
Peak memory 193812 kb
Host smart-8c33ed79-d3d6-4eec-aafe-1fcef5e25ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91562347434135521565091824536854111314337063518535592310253871805558289990270 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.gpio_alert_test.91562347434135521565091824536854111314337063518535592310253871805558289990270
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.11440451766521705338046194115381049771504910698816808241874916926006223913967
Short name T687
Test name
Test status
Simulation time 57921923 ps
CPU time 0.84 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:16 PM PST 23
Peak memory 196148 kb
Host smart-38da055e-5a5d-44f5-9a78-f4abb7a88645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11440451766521705338046194115381049771504910698816808241874916926006223913967 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.11440451766521705338046194115381049771504910698816808241874916926006223913967
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.68048818609016056731055562086756463213295349447210159290312668642294563224687
Short name T388
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.11 seconds
Started Nov 22 12:26:37 PM PST 23
Finished Nov 22 12:26:59 PM PST 23
Peak memory 195432 kb
Host smart-ef434051-a04f-4b6b-b6be-ee61c14565fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68048818609016056731055562086756463213295349447210159290312668642294563224687 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stress.68048818609016056731055562086756463213295349447210159290312668642294563224687
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1135849650207869108023596207085494688712946558131781442045495428411642355996
Short name T530
Test name
Test status
Simulation time 137439144 ps
CPU time 1.01 seconds
Started Nov 22 12:26:45 PM PST 23
Finished Nov 22 12:26:47 PM PST 23
Peak memory 196300 kb
Host smart-488b3e2e-8fbc-4cf2-8b92-3f73e708e2d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135849650207869108023596207085494688712946558131781442045495428411642355996 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1135849650207869108023596207085494688712946558131781442045495428411642355996
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.38301133327757597751136014785581596056126270770232814211385747806354520843477
Short name T237
Test name
Test status
Simulation time 119314289 ps
CPU time 1.23 seconds
Started Nov 22 12:24:48 PM PST 23
Finished Nov 22 12:24:50 PM PST 23
Peak memory 195680 kb
Host smart-e2e3e42a-880d-4f36-8522-5562b8d7f9aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38301133327757597751136014785581596056126270770232814211385747806354520843477 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.38301133327757597751136014785581596056126270770232814211385747806354520843477
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.74552775667883621839262549281115411036436336301160937348330128255913702715344
Short name T492
Test name
Test status
Simulation time 134635595 ps
CPU time 2.95 seconds
Started Nov 22 12:26:38 PM PST 23
Finished Nov 22 12:26:42 PM PST 23
Peak memory 197088 kb
Host smart-d275562a-dbad-4a77-8664-2da4ce08d6ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74552775667883621839262549281115411036436336301160937348330128255913
702715344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.74552775667883621839262
549281115411036436336301160937348330128255913702715344
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3167404144045643275266537947963312770899541921113399598355848888435431389419
Short name T431
Test name
Test status
Simulation time 228920555 ps
CPU time 2.75 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:27 PM PST 23
Peak memory 195416 kb
Host smart-3d827d34-8bfb-41f3-8e39-fdf647a4baa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167404144045643275266537947963312770899541921113399598355848888435431389419 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.3167404144045643275266537947963312770899541921113399598355848888435431389419
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.8498872935063752719641111584603938072607417817517323761563276756755935407679
Short name T376
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:17 PM PST 23
Peak memory 195692 kb
Host smart-5f2301a3-3b44-46b7-9081-32f62c9af2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8498872935063752719641111584603938072607417817517323761563276756755935407679 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.gpio_random_dout_din.8498872935063752719641111584603938072607417817517323761563276756755935407679
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.69424997087951302905331582868452589590151231327350677584481272646860161733864
Short name T443
Test name
Test status
Simulation time 81278879 ps
CPU time 1.09 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:27:26 PM PST 23
Peak memory 195412 kb
Host smart-1305963f-18ee-4e82-aa7b-ec1576299dbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69424997087951302905331582868452589590151231327350677584481272646860161733864 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup_pulldown.69424997087951302905331582868452589590151231327350677584481272646860161733864
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2429407535854509272280798980219809170554529619539880850565885676479272353047
Short name T484
Test name
Test status
Simulation time 572864232 ps
CPU time 5.3 seconds
Started Nov 22 12:26:43 PM PST 23
Finished Nov 22 12:26:50 PM PST 23
Peak memory 197808 kb
Host smart-5779bd0a-d251-4dd7-8bba-b27e3a22d1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429407535854509272280798980219809170554529619539880850565885676479272353047 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_long_reg_writes_reg_reads.2429407535854509272280798980219809170554529619539
880850565885676479272353047
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.102169370031040272460154403213609300879767184547520282098325583554706002844470
Short name T678
Test name
Test status
Simulation time 112796484 ps
CPU time 1.25 seconds
Started Nov 22 12:27:45 PM PST 23
Finished Nov 22 12:27:52 PM PST 23
Peak memory 195456 kb
Host smart-31c8bb83-c81b-4bdb-b3c8-3fbbb2abd6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102169370031040272460154403213609300879767184547520282098325583554706002844470 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.gpio_smoke.102169370031040272460154403213609300879767184547520282098325583554706002844470
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.54993479365427873597690292704381638121102076080558032321092889510927040472308
Short name T300
Test name
Test status
Simulation time 112796484 ps
CPU time 1.3 seconds
Started Nov 22 12:23:40 PM PST 23
Finished Nov 22 12:23:42 PM PST 23
Peak memory 195408 kb
Host smart-d2880a94-58bd-4c13-9e5f-a24e11abb2a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54993479365427873597690292704381638121102076080558032321092889510927040472308 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.54993479365427873597690292704381638121102076080558032321092889510927040472308
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.95379540251179849487156440005619454061508701563476924616451799296639471339322
Short name T709
Test name
Test status
Simulation time 21104521406 ps
CPU time 166.95 seconds
Started Nov 22 12:23:09 PM PST 23
Finished Nov 22 12:25:57 PM PST 23
Peak memory 198148 kb
Host smart-14004f52-451e-41fd-a3d9-a8c8dd5ef908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9537954025117984948715644000561945406150870156347692461645179929
6639471339322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all.953795402511798494871564400056194540615087015634769246164517992
96639471339322
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.8058569545648153953274833133617301322430967109079601664741315176297376371895
Short name T555
Test name
Test status
Simulation time 133069054254 ps
CPU time 1072.16 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:44:15 PM PST 23
Peak memory 197292 kb
Host smart-39ea4c73-7166-4395-8b07-04d700470f4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=8058569545648153953274833133617301322430967109079601664741315176297376371895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_wit
h_rand_reset.8058569545648153953274833133617301322430967109079601664741315176297376371895
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.115434804526775790247955677337451786602872125867154793010498951545709187786804
Short name T602
Test name
Test status
Simulation time 22440064 ps
CPU time 0.77 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:40 PM PST 23
Peak memory 190792 kb
Host smart-ece6e662-24fe-47ac-af58-3ac9114a7618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115434804526775790247955677337451786602872125867154793010498951545709187786804 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.115434804526775790247955677337451786602872125867154793010498951545709187786804
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.101997287654762593787942599287568964316703486600111563248403203243915655739064
Short name T460
Test name
Test status
Simulation time 57921923 ps
CPU time 0.85 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:04 PM PST 23
Peak memory 194828 kb
Host smart-e63a5088-4a28-4ff1-bad1-7054314a663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101997287654762593787942599287568964316703486600111563248403203243915655739064 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.101997287654762593787942599287568964316703486600111563248403203243915655739064
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.39218280487807696019672654357131918611793309541560055913109864708506935584406
Short name T305
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.62 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:44 PM PST 23
Peak memory 195436 kb
Host smart-0386e65d-a9ed-43fc-af67-2484e4c3480e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218280487807696019672654357131918611793309541560055913109864708506935584406 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stress.39218280487807696019672654357131918611793309541560055913109864708506935584406
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.79118357409119534799600673467549753581729298174493030142105888018535039390486
Short name T313
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 196304 kb
Host smart-5e6b6cb0-1abe-427b-a9bc-b55d2d1b02b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79118357409119534799600673467549753581729298174493030142105888018535039390486 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.79118357409119534799600673467549753581729298174493030142105888018535039390486
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.111226868612169275063491160021715981285314939094173816863482514032100285396265
Short name T786
Test name
Test status
Simulation time 119314289 ps
CPU time 1.18 seconds
Started Nov 22 12:28:17 PM PST 23
Finished Nov 22 12:28:20 PM PST 23
Peak memory 194796 kb
Host smart-01cb11d5-acb2-40bf-98e4-d30fed19babe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111226868612169275063491160021715981285314939094173816863482514032100285396265 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.111226868612169275063491160021715981285314939094173816863482514032100285396265
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.8850592645503984031823495405321341772718017648345097820655687011987928574742
Short name T456
Test name
Test status
Simulation time 134635595 ps
CPU time 2.88 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:11 PM PST 23
Peak memory 196728 kb
Host smart-1a01e1c8-7b5e-4fbb-ba1a-ae38b6de63d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88505926455039840318234954053213417727180176483450978206556870119879
28574742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.885059264550398403182349
5405321341772718017648345097820655687011987928574742
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2754823982614646439116469544877587055718845146604446551921980935844102404359
Short name T310
Test name
Test status
Simulation time 228920555 ps
CPU time 2.75 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 195704 kb
Host smart-a11ffbea-b444-4ceb-94a5-4651e103c5e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754823982614646439116469544877587055718845146604446551921980935844102404359 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.2754823982614646439116469544877587055718845146604446551921980935844102404359
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.21877615187873654995215541452246900165001101112766594054685736032330680775997
Short name T418
Test name
Test status
Simulation time 81278879 ps
CPU time 1.1 seconds
Started Nov 22 12:27:19 PM PST 23
Finished Nov 22 12:27:27 PM PST 23
Peak memory 195556 kb
Host smart-63b4ffc1-6ef3-42f6-ae63-f129d8492765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21877615187873654995215541452246900165001101112766594054685736032330680775997 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.gpio_random_dout_din.21877615187873654995215541452246900165001101112766594054685736032330680775997
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.75182601869255891882688818838043692139190510250917160767974749580370507388549
Short name T217
Test name
Test status
Simulation time 81278879 ps
CPU time 1.08 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:27:22 PM PST 23
Peak memory 195412 kb
Host smart-c121e4b1-c430-48c9-b331-27e9772656f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75182601869255891882688818838043692139190510250917160767974749580370507388549 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup_pulldown.75182601869255891882688818838043692139190510250917160767974749580370507388549
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.18428568881781584069956759825724146621652112172695117712295920112431091811007
Short name T800
Test name
Test status
Simulation time 572864232 ps
CPU time 5.23 seconds
Started Nov 22 12:26:58 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 196916 kb
Host smart-002d7e5f-f3e7-4ae8-b6bb-43c3acba01d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428568881781584069956759825724146621652112172695117712295920112431091811007 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_long_reg_writes_reg_reads.184285688817815840699567598257241466216521121726
95117712295920112431091811007
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.106537748116962428725909639151858133375125612381252758442896110527656393974889
Short name T436
Test name
Test status
Simulation time 112796484 ps
CPU time 1.22 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:17 PM PST 23
Peak memory 195432 kb
Host smart-104f517f-e7b0-4a7a-a9d4-fc1e5040b1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106537748116962428725909639151858133375125612381252758442896110527656393974889 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.gpio_smoke.106537748116962428725909639151858133375125612381252758442896110527656393974889
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.109734535453279015084277452269848436184105392359829781627214882496776507014250
Short name T466
Test name
Test status
Simulation time 112796484 ps
CPU time 1.21 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 195376 kb
Host smart-e1ef387d-a4b4-49d8-9007-e0b935dd41ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109734535453279015084277452269848436184105392359829781627214882496776507014250 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.109734535453279015084277452269848436184105392359829781627214882496776507014250
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.85864546999889511070251709633746737367829856781419284012368114635118210779419
Short name T870
Test name
Test status
Simulation time 21104521406 ps
CPU time 156.04 seconds
Started Nov 22 12:27:18 PM PST 23
Finished Nov 22 12:30:01 PM PST 23
Peak memory 196124 kb
Host smart-659e0939-c9a7-4ebc-81fe-45e7587e3b10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8586454699988951107025170963374673736782985678141928401236811463
5118210779419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all.858645469998895110702517096337467373678298567814192840123681146
35118210779419
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.97084629831285507095180794663024313108571653644490113415686556302830250199756
Short name T668
Test name
Test status
Simulation time 133069054254 ps
CPU time 1071.96 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:44:16 PM PST 23
Peak memory 197732 kb
Host smart-1ed7ad48-a824-45e6-ad74-297a185d5a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=97084629831285507095180794663024313108571653644490113415686556302830250199756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_wi
th_rand_reset.97084629831285507095180794663024313108571653644490113415686556302830250199756
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.57178387189664303023584839556169014514935348032325372060246264793423791713298
Short name T277
Test name
Test status
Simulation time 22440064 ps
CPU time 0.77 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:40 PM PST 23
Peak memory 190660 kb
Host smart-98c0807c-e0c3-4afc-bc11-b295b92510f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57178387189664303023584839556169014514935348032325372060246264793423791713298 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.gpio_alert_test.57178387189664303023584839556169014514935348032325372060246264793423791713298
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.86797607781791106234660600234655031869216496730229772619089457280110709815133
Short name T249
Test name
Test status
Simulation time 57921923 ps
CPU time 0.82 seconds
Started Nov 22 12:26:51 PM PST 23
Finished Nov 22 12:26:54 PM PST 23
Peak memory 196148 kb
Host smart-eed149f0-4d80-41db-83dd-13d55c7d2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86797607781791106234660600234655031869216496730229772619089457280110709815133 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.86797607781791106234660600234655031869216496730229772619089457280110709815133
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.51312195532281898265402159303912523653603730815925168606421719794196941087709
Short name T727
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.09 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:46 PM PST 23
Peak memory 195048 kb
Host smart-fc91b3fd-f356-4f86-975d-e36a17303950
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51312195532281898265402159303912523653603730815925168606421719794196941087709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stress.51312195532281898265402159303912523653603730815925168606421719794196941087709
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.18115842256105050815941965768157302434928619170896751025518218622581573909461
Short name T593
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 195880 kb
Host smart-69a79f7a-13f6-48b1-a0ca-d3f653ddb7b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18115842256105050815941965768157302434928619170896751025518218622581573909461 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.18115842256105050815941965768157302434928619170896751025518218622581573909461
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.75480380801084363507658237213671269535105320697164296211260290353605818628423
Short name T843
Test name
Test status
Simulation time 119314289 ps
CPU time 1.19 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 195636 kb
Host smart-ac053e27-8474-4f55-9b31-bf6230dde779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75480380801084363507658237213671269535105320697164296211260290353605818628423 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.75480380801084363507658237213671269535105320697164296211260290353605818628423
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.75052344386550971354374525827230856133320866819418471164799566668196828135661
Short name T254
Test name
Test status
Simulation time 134635595 ps
CPU time 2.77 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:21 PM PST 23
Peak memory 197028 kb
Host smart-1afdf362-026c-4441-9d79-ab73282b3dec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75052344386550971354374525827230856133320866819418471164799566668196
828135661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.75052344386550971354374
525827230856133320866819418471164799566668196828135661
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.107663170080535865244207536524292750872769660343770595547372310004310602475062
Short name T230
Test name
Test status
Simulation time 228920555 ps
CPU time 2.78 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 195284 kb
Host smart-40f81f3e-91b5-4628-b92a-72420f390083
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107663170080535865244207536524292750872769660343770595547372310004310602475062 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.107663170080535865244207536524292750872769660343770595547372310004310602475062
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.74297088452298468878115069814211608319130260979964324875828326916277620743187
Short name T232
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:27:01 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 193820 kb
Host smart-4fa887ee-f431-4c43-b130-79ac908a521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74297088452298468878115069814211608319130260979964324875828326916277620743187 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.gpio_random_dout_din.74297088452298468878115069814211608319130260979964324875828326916277620743187
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.96190356594038868825075333187734242396421738097507983137927152905059243828515
Short name T205
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:26:58 PM PST 23
Finished Nov 22 12:27:06 PM PST 23
Peak memory 195628 kb
Host smart-634dc94d-1c66-4f7f-98b0-db9649ac7ea2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96190356594038868825075333187734242396421738097507983137927152905059243828515 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_pulldown.96190356594038868825075333187734242396421738097507983137927152905059243828515
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.28219058507800336747204045690932340019936473424105191892620538387195982368105
Short name T290
Test name
Test status
Simulation time 572864232 ps
CPU time 5.13 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:11 PM PST 23
Peak memory 197672 kb
Host smart-dacfa019-9562-4fd7-9ae4-b1a2d2bd26e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219058507800336747204045690932340019936473424105191892620538387195982368105 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_long_reg_writes_reg_reads.282190585078003367472040456909323400199364734241
05191892620538387195982368105
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.115574927666051728730301825472417685331439484176680966811466499033682126374855
Short name T473
Test name
Test status
Simulation time 112796484 ps
CPU time 1.23 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:08 PM PST 23
Peak memory 195364 kb
Host smart-b9ae8504-f5c5-4ec5-81ab-2754e1188d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115574927666051728730301825472417685331439484176680966811466499033682126374855 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.gpio_smoke.115574927666051728730301825472417685331439484176680966811466499033682126374855
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.21040725553328052962543530819214738917626554891905086673973002307896922263689
Short name T482
Test name
Test status
Simulation time 112796484 ps
CPU time 1.19 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:04 PM PST 23
Peak memory 195340 kb
Host smart-c55482a1-b8e7-4f18-ba0a-d616435d6023
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21040725553328052962543530819214738917626554891905086673973002307896922263689 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.21040725553328052962543530819214738917626554891905086673973002307896922263689
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.113112978887554764035980649412543470266961689374449923864943984885737478612299
Short name T670
Test name
Test status
Simulation time 21104521406 ps
CPU time 166.81 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:30:04 PM PST 23
Peak memory 197980 kb
Host smart-1105cea4-41fd-48d4-b3da-f77c32cd4dae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131129788875547640359806494125434702669616893744499238649439848
85737478612299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all.11311297888755476403598064941254347026696168937444992386494398
4885737478612299
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.69164368164353538320447208216171736221031607513714760701066915346312236685477
Short name T675
Test name
Test status
Simulation time 133069054254 ps
CPU time 1102.86 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:45:41 PM PST 23
Peak memory 198132 kb
Host smart-cdd6d7b8-55ab-4a82-976f-dc7ce3f76429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=69164368164353538320447208216171736221031607513714760701066915346312236685477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_wi
th_rand_reset.69164368164353538320447208216171736221031607513714760701066915346312236685477
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.75084397299795562559854499310832909203668586996000372405745448775964879778568
Short name T342
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:03 PM PST 23
Peak memory 193828 kb
Host smart-77adcf55-a0ad-4819-950e-9cc6d7dcdd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75084397299795562559854499310832909203668586996000372405745448775964879778568 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.gpio_alert_test.75084397299795562559854499310832909203668586996000372405745448775964879778568
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.106670447284021055976876346066407440801105770967614599233827453633700434615230
Short name T216
Test name
Test status
Simulation time 57921923 ps
CPU time 0.85 seconds
Started Nov 22 12:27:01 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 195776 kb
Host smart-6a0933fc-e5bc-43e8-8c9d-30cbeb267e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106670447284021055976876346066407440801105770967614599233827453633700434615230 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.106670447284021055976876346066407440801105770967614599233827453633700434615230
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.97922540998510413376404841292134921711587033728734757081803510087626472672719
Short name T410
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.45 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:45 PM PST 23
Peak memory 194596 kb
Host smart-6c933eeb-dc30-4240-bace-f50eb3d1c688
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97922540998510413376404841292134921711587033728734757081803510087626472672719 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stress.97922540998510413376404841292134921711587033728734757081803510087626472672719
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.11930061543627337148821151343201277106085753602958141590882683072875023621009
Short name T568
Test name
Test status
Simulation time 137439144 ps
CPU time 0.95 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 196272 kb
Host smart-5a17a182-01f1-457f-b4a4-6f4ec8a4c300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11930061543627337148821151343201277106085753602958141590882683072875023621009 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.11930061543627337148821151343201277106085753602958141590882683072875023621009
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.74257888233503150505195616415412264716931818641548837631098719972484657846299
Short name T573
Test name
Test status
Simulation time 119314289 ps
CPU time 1.27 seconds
Started Nov 22 12:26:41 PM PST 23
Finished Nov 22 12:26:44 PM PST 23
Peak memory 195604 kb
Host smart-c9e6bbf1-0e04-4b06-bfea-b0ab02327b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74257888233503150505195616415412264716931818641548837631098719972484657846299 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.74257888233503150505195616415412264716931818641548837631098719972484657846299
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.51473392028873530506804799954129191382422486287299693958871973464567810062042
Short name T465
Test name
Test status
Simulation time 134635595 ps
CPU time 2.76 seconds
Started Nov 22 12:27:04 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 197028 kb
Host smart-c18ef428-8771-4928-88d0-8c087a19afba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51473392028873530506804799954129191382422486287299693958871973464567
810062042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.51473392028873530506804
799954129191382422486287299693958871973464567810062042
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.88088455349519727954748565188517794662960223060963677972256483824767533651191
Short name T840
Test name
Test status
Simulation time 228920555 ps
CPU time 2.96 seconds
Started Nov 22 12:24:15 PM PST 23
Finished Nov 22 12:24:19 PM PST 23
Peak memory 195740 kb
Host smart-eb872b25-020a-46f7-98ec-d1c2ebdf76d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88088455349519727954748565188517794662960223060963677972256483824767533651191 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.88088455349519727954748565188517794662960223060963677972256483824767533651191
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.63449547883939280162716433453938097804878029286432994742011064121947231122698
Short name T496
Test name
Test status
Simulation time 81278879 ps
CPU time 1.13 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 194932 kb
Host smart-7e13560f-1d8c-4a9e-b666-4f862d37753d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63449547883939280162716433453938097804878029286432994742011064121947231122698 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.gpio_random_dout_din.63449547883939280162716433453938097804878029286432994742011064121947231122698
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.80592758703493039368228950459187790715212437565187572370710071113052459312533
Short name T522
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:24:32 PM PST 23
Finished Nov 22 12:24:34 PM PST 23
Peak memory 195312 kb
Host smart-3265f5f7-2927-4b3e-88bc-7a9f5a668ca2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80592758703493039368228950459187790715212437565187572370710071113052459312533 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup_pulldown.80592758703493039368228950459187790715212437565187572370710071113052459312533
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.31807677294385862733869393110397544688472387600184715656300896079997390199132
Short name T306
Test name
Test status
Simulation time 572864232 ps
CPU time 4.87 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:29 PM PST 23
Peak memory 197336 kb
Host smart-254ff45b-d50e-4378-be88-eaa90d4cd9c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31807677294385862733869393110397544688472387600184715656300896079997390199132 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_long_reg_writes_reg_reads.318076772943858627338693931103975446884723876001
84715656300896079997390199132
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.48384306901983091062784230565492136680517332437414659918339947965348792661326
Short name T806
Test name
Test status
Simulation time 112796484 ps
CPU time 1.23 seconds
Started Nov 22 12:27:00 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 194520 kb
Host smart-b8ce99ca-f0c2-4946-aeba-b495f5f0da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48384306901983091062784230565492136680517332437414659918339947965348792661326 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.gpio_smoke.48384306901983091062784230565492136680517332437414659918339947965348792661326
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.80513533945598481557013820680049569920092427603764332029177260747791261713542
Short name T547
Test name
Test status
Simulation time 112796484 ps
CPU time 1.35 seconds
Started Nov 22 12:24:45 PM PST 23
Finished Nov 22 12:24:47 PM PST 23
Peak memory 195392 kb
Host smart-c19921e3-3de4-4e7a-b3e0-62ec14268ecc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80513533945598481557013820680049569920092427603764332029177260747791261713542 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.80513533945598481557013820680049569920092427603764332029177260747791261713542
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.70931059080214712572279834989186373360370443570302604537400633441228674818230
Short name T517
Test name
Test status
Simulation time 21104521406 ps
CPU time 158.58 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:29:03 PM PST 23
Peak memory 196968 kb
Host smart-e4ea8625-4cb5-4ad4-8bff-eb27909db210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7093105908021471257227983498918637336037044357030260453740063344
1228674818230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all.709310590802147125722798349891863733603704435703026045374006334
41228674818230
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.44393893400703744595814736109516041409029788972992331264399727333924310136369
Short name T478
Test name
Test status
Simulation time 133069054254 ps
CPU time 1134.51 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:46:12 PM PST 23
Peak memory 198204 kb
Host smart-cfe8eefc-6c62-4e6f-8fde-f59831e6dd5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=44393893400703744595814736109516041409029788972992331264399727333924310136369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_wi
th_rand_reset.44393893400703744595814736109516041409029788972992331264399727333924310136369
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.68712251021715506580356553981371637579534889222088064155986063461600099916310
Short name T239
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 193548 kb
Host smart-78049ede-beb3-4b9e-936e-4fe91dff3e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68712251021715506580356553981371637579534889222088064155986063461600099916310 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.gpio_alert_test.68712251021715506580356553981371637579534889222088064155986063461600099916310
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.31278636926245849240414784260946534824479923846816830590039560115845933290147
Short name T477
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.42 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 195424 kb
Host smart-4b1ff7d7-fe40-4d88-8785-4a04ac4a3615
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278636926245849240414784260946534824479923846816830590039560115845933290147 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress.31278636926245849240414784260946534824479923846816830590039560115845933290147
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.5280557881476868915107029105938577225027842113709127796392905141796425987026
Short name T858
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 196000 kb
Host smart-939713f2-8792-4dd9-ba74-a8cbc56dd9d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5280557881476868915107029105938577225027842113709127796392905141796425987026 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.5280557881476868915107029105938577225027842113709127796392905141796425987026
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.10608137878948843951296038791478167984180750443629299835885835017489674132487
Short name T282
Test name
Test status
Simulation time 119314289 ps
CPU time 1.38 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 193020 kb
Host smart-8450aad5-49f3-4a45-9964-8fa57445880e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10608137878948843951296038791478167984180750443629299835885835017489674132487 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.10608137878948843951296038791478167984180750443629299835885835017489674132487
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2437978617460135744063689125649054736101050338274774478337730230247808552457
Short name T685
Test name
Test status
Simulation time 134635595 ps
CPU time 2.87 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 196928 kb
Host smart-be834a58-66c4-45a3-878b-d1c2f78a156d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24379786174601357440636891256490547361010503382747744783377302302478
08552457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.243797861746013574406368
9125649054736101050338274774478337730230247808552457
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.21351268773598605032907956541127327830076774875780875934450521875083590440763
Short name T747
Test name
Test status
Simulation time 228920555 ps
CPU time 2.93 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:16 PM PST 23
Peak memory 195752 kb
Host smart-0e5a61d3-ca73-4ebb-892c-94ef9d7d6cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21351268773598605032907956541127327830076774875780875934450521875083590440763 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.21351268773598605032907956541127327830076774875780875934450521875083590440763
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.80351936830459679393625656118616722357458526243673219476687021280016184476843
Short name T260
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:27:01 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 194000 kb
Host smart-23162b6e-0963-40a2-b05f-d8492fd8bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80351936830459679393625656118616722357458526243673219476687021280016184476843 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.gpio_random_dout_din.80351936830459679393625656118616722357458526243673219476687021280016184476843
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.17169397166781683387307017393874282264041206498903970479164289000939349756703
Short name T596
Test name
Test status
Simulation time 81278879 ps
CPU time 1.29 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 193148 kb
Host smart-b3ee9282-10b5-438d-871e-667957dce6f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169397166781683387307017393874282264041206498903970479164289000939349756703 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup_pulldown.17169397166781683387307017393874282264041206498903970479164289000939349756703
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.55997993291914328831949478774961003988693956312761304265195311095946126680849
Short name T601
Test name
Test status
Simulation time 572864232 ps
CPU time 5.02 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:23 PM PST 23
Peak memory 197744 kb
Host smart-33fe403b-f25f-4816-b3d3-1713d74bab5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55997993291914328831949478774961003988693956312761304265195311095946126680849 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_long_reg_writes_reg_reads.559979932919143288319494787749610039886939563127
61304265195311095946126680849
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.31159791227106008734774603147008222789290308626790416058838863382242559390063
Short name T296
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 194424 kb
Host smart-c511d5da-0992-43e5-ba4c-8bfe79a03f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31159791227106008734774603147008222789290308626790416058838863382242559390063 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.gpio_smoke.31159791227106008734774603147008222789290308626790416058838863382242559390063
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.69431173868120296306671243450543408231216661700583913761041065343987582600461
Short name T618
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:26:19 PM PST 23
Finished Nov 22 12:26:25 PM PST 23
Peak memory 195016 kb
Host smart-bbe5a4b3-c12e-4075-9769-3f335a41b08c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69431173868120296306671243450543408231216661700583913761041065343987582600461 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.69431173868120296306671243450543408231216661700583913761041065343987582600461
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.95737824196679880482548445719308927037444889551079980461828656475579302306151
Short name T667
Test name
Test status
Simulation time 21104521406 ps
CPU time 169.7 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:30:07 PM PST 23
Peak memory 198012 kb
Host smart-edbc39c9-1913-4e60-8bc6-d9c1564ab42b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9573782419667988048254844571930892703744488955107998046182865647
5579302306151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all.957378241966798804825484457193089270374448895510799804618286564
75579302306151
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.47226756289985252772199854356448955915847701964256038142767790687424476485359
Short name T608
Test name
Test status
Simulation time 133069054254 ps
CPU time 1088.88 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:44:29 PM PST 23
Peak memory 195356 kb
Host smart-7bdb8e7c-142f-4612-9629-16853b293835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=47226756289985252772199854356448955915847701964256038142767790687424476485359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_wi
th_rand_reset.47226756289985252772199854356448955915847701964256038142767790687424476485359
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.18746220945873018617044328414856286437047634095866599282610214488613904567037
Short name T792
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:27:19 PM PST 23
Finished Nov 22 12:27:26 PM PST 23
Peak memory 193832 kb
Host smart-79b0baa8-906b-4cd0-a46c-8199b23486ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18746220945873018617044328414856286437047634095866599282610214488613904567037 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.gpio_alert_test.18746220945873018617044328414856286437047634095866599282610214488613904567037
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.5712667026245975515078064118918355745623078307840346576514001898105255245754
Short name T828
Test name
Test status
Simulation time 57921923 ps
CPU time 0.99 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 193532 kb
Host smart-4b7fa8fa-4f9c-49d8-b2b6-67bcd2b1f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5712667026245975515078064118918355745623078307840346576514001898105255245754 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.gpio_dout_din_regs_random_rw.5712667026245975515078064118918355745623078307840346576514001898105255245754
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.20799927651676779892545635401820759473141223236756105873871541013062327976585
Short name T413
Test name
Test status
Simulation time 1135699015 ps
CPU time 23.21 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:27:45 PM PST 23
Peak memory 195428 kb
Host smart-23a88102-0139-4710-8008-7922101116b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20799927651676779892545635401820759473141223236756105873871541013062327976585 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stress.20799927651676779892545635401820759473141223236756105873871541013062327976585
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.37332224596569614361750269812078823646222287607207415919094795760314902282417
Short name T591
Test name
Test status
Simulation time 137439144 ps
CPU time 0.97 seconds
Started Nov 22 12:26:15 PM PST 23
Finished Nov 22 12:26:19 PM PST 23
Peak memory 196308 kb
Host smart-f5138611-1211-487e-a0f3-fe972509cf5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332224596569614361750269812078823646222287607207415919094795760314902282417 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.37332224596569614361750269812078823646222287607207415919094795760314902282417
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.49969714232443002874077018090818839025786413650717179403882896903823284875710
Short name T430
Test name
Test status
Simulation time 119314289 ps
CPU time 1.43 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 193484 kb
Host smart-be4ec03e-59f9-466f-a561-5bfccd802758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49969714232443002874077018090818839025786413650717179403882896903823284875710 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.49969714232443002874077018090818839025786413650717179403882896903823284875710
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.75036540835602179028034628740118167646941457217666337139517885525324991106815
Short name T820
Test name
Test status
Simulation time 134635595 ps
CPU time 3.06 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:23 PM PST 23
Peak memory 195536 kb
Host smart-b2391b04-6e9c-4f57-b5a1-1b5c64cf5e1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75036540835602179028034628740118167646941457217666337139517885525324
991106815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.75036540835602179028034
628740118167646941457217666337139517885525324991106815
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.53712146754806819175127248969669411698088068075492152062345170582162957195768
Short name T541
Test name
Test status
Simulation time 228920555 ps
CPU time 2.72 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:09 PM PST 23
Peak memory 195628 kb
Host smart-2709603c-5948-4e49-80fa-4f209d6eb559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53712146754806819175127248969669411698088068075492152062345170582162957195768 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.53712146754806819175127248969669411698088068075492152062345170582162957195768
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.7653096409177165361224479122601334841017335964231208032968682039050536288409
Short name T742
Test name
Test status
Simulation time 81278879 ps
CPU time 1.3 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 193604 kb
Host smart-19ba45c3-c303-4587-8b52-aefd4a614dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7653096409177165361224479122601334841017335964231208032968682039050536288409 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.gpio_random_dout_din.7653096409177165361224479122601334841017335964231208032968682039050536288409
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.112763272609476869312130352165755238492979593859697551940119249596823415692967
Short name T558
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:24:52 PM PST 23
Finished Nov 22 12:24:54 PM PST 23
Peak memory 195936 kb
Host smart-3f07167c-39b4-43f2-8347-86e9202079a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112763272609476869312130352165755238492979593859697551940119249596823415692967 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup_pulldown.112763272609476869312130352165755238492979593859697551940119249596823415692967
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.15915300998962403171117537555464233715291012969395319239486477032495001096680
Short name T862
Test name
Test status
Simulation time 572864232 ps
CPU time 5.27 seconds
Started Nov 22 12:26:50 PM PST 23
Finished Nov 22 12:26:57 PM PST 23
Peak memory 197788 kb
Host smart-fa3ea87c-0362-4ef0-81a9-b8299581e0d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915300998962403171117537555464233715291012969395319239486477032495001096680 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_long_reg_writes_reg_reads.159153009989624031711175375554642337152910129693
95319239486477032495001096680
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.36487704531765816055685455983598361616302220542171639697645620755027692086883
Short name T584
Test name
Test status
Simulation time 112796484 ps
CPU time 1.45 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 192804 kb
Host smart-2e045b7c-ff95-4636-a154-cdfb53b7fa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36487704531765816055685455983598361616302220542171639697645620755027692086883 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.gpio_smoke.36487704531765816055685455983598361616302220542171639697645620755027692086883
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.80315476083727492425349896821495716638991769825527843640869963039563961988844
Short name T723
Test name
Test status
Simulation time 112796484 ps
CPU time 1.3 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 195028 kb
Host smart-148951ea-eb3e-4a48-8b5b-c4844879e8ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80315476083727492425349896821495716638991769825527843640869963039563961988844 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.80315476083727492425349896821495716638991769825527843640869963039563961988844
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.556476532237597377060567253816250525336414109977236241640294121629595848626
Short name T732
Test name
Test status
Simulation time 21104521406 ps
CPU time 153.62 seconds
Started Nov 22 12:27:01 PM PST 23
Finished Nov 22 12:29:42 PM PST 23
Peak memory 196264 kb
Host smart-187d219c-3619-444e-817f-841082e91652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5564765322375973770605672538162505253364141099772362416402941216
29595848626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all.556476532237597377060567253816250525336414109977236241640294121629595848626
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.37296307805665090488355465970253389138096801120347479651895317715397583206500
Short name T838
Test name
Test status
Simulation time 133069054254 ps
CPU time 1073.07 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:44:13 PM PST 23
Peak memory 195804 kb
Host smart-c3fa1a68-22fe-465a-b6b6-ffbab225e666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=37296307805665090488355465970253389138096801120347479651895317715397583206500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_wi
th_rand_reset.37296307805665090488355465970253389138096801120347479651895317715397583206500
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.30607134625642041705853864198998902514683155533863145453986158879713420874677
Short name T486
Test name
Test status
Simulation time 22440064 ps
CPU time 0.54 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:00 PM PST 23
Peak memory 193780 kb
Host smart-b13ad687-72c2-4a84-86f9-85e89436ca0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30607134625642041705853864198998902514683155533863145453986158879713420874677 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.gpio_alert_test.30607134625642041705853864198998902514683155533863145453986158879713420874677
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.81145993382670821504533891110002928468565021538127372495668903867282638803424
Short name T493
Test name
Test status
Simulation time 57921923 ps
CPU time 0.93 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 193204 kb
Host smart-289e8956-86e3-429a-9f62-92794dc30d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81145993382670821504533891110002928468565021538127372495668903867282638803424 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.81145993382670821504533891110002928468565021538127372495668903867282638803424
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.20103252727357336186319777939989594749706723388400175271868660244324802677509
Short name T648
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.74 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:54 PM PST 23
Peak memory 194248 kb
Host smart-a6004648-77b5-4856-a0fa-b3565326da6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20103252727357336186319777939989594749706723388400175271868660244324802677509 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stress.20103252727357336186319777939989594749706723388400175271868660244324802677509
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.73798789789249162405463489419818941962569364114261571658020761020210880272044
Short name T444
Test name
Test status
Simulation time 137439144 ps
CPU time 0.99 seconds
Started Nov 22 12:25:05 PM PST 23
Finished Nov 22 12:25:06 PM PST 23
Peak memory 196284 kb
Host smart-3438531f-c841-4318-95fd-9d5f8512ddb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73798789789249162405463489419818941962569364114261571658020761020210880272044 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.73798789789249162405463489419818941962569364114261571658020761020210880272044
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.33360874036581933149358842299187943368365481243544003692954057794093494502152
Short name T724
Test name
Test status
Simulation time 119314289 ps
CPU time 1.19 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 194424 kb
Host smart-523e9d1c-d1d6-4b62-a586-8b3a2a4cb09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360874036581933149358842299187943368365481243544003692954057794093494502152 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.33360874036581933149358842299187943368365481243544003692954057794093494502152
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.39706865116809397547284723162907058469699821462678150552860458648960520264226
Short name T283
Test name
Test status
Simulation time 134635595 ps
CPU time 2.96 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:35 PM PST 23
Peak memory 195688 kb
Host smart-904076e1-dd6a-4bff-b886-aab75d0b5708
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39706865116809397547284723162907058469699821462678150552860458648960
520264226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.39706865116809397547284
723162907058469699821462678150552860458648960520264226
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.63460119131370239133585855049901750911281902245881334426424013719955759462146
Short name T421
Test name
Test status
Simulation time 228920555 ps
CPU time 2.69 seconds
Started Nov 22 12:27:03 PM PST 23
Finished Nov 22 12:27:13 PM PST 23
Peak memory 195768 kb
Host smart-063b068f-0a79-4341-9957-1b66f4e05cdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63460119131370239133585855049901750911281902245881334426424013719955759462146 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.63460119131370239133585855049901750911281902245881334426424013719955759462146
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.41282637524225886506016840660417344013936374317265740093541810512214257686399
Short name T865
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 194468 kb
Host smart-01edf6a6-8e2b-483b-86c6-072bb6f9e61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41282637524225886506016840660417344013936374317265740093541810512214257686399 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.gpio_random_dout_din.41282637524225886506016840660417344013936374317265740093541810512214257686399
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.93467835692220135821654104437941488492135233785489180417196034103941989512563
Short name T64
Test name
Test status
Simulation time 81278879 ps
CPU time 1.22 seconds
Started Nov 22 12:26:20 PM PST 23
Finished Nov 22 12:26:26 PM PST 23
Peak memory 193020 kb
Host smart-787e2da5-4fd4-468f-9a43-bab0ff0aa985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93467835692220135821654104437941488492135233785489180417196034103941989512563 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup_pulldown.93467835692220135821654104437941488492135233785489180417196034103941989512563
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.37251310676329636194752649226913696329837412545131373779704573572957754800427
Short name T637
Test name
Test status
Simulation time 572864232 ps
CPU time 5.16 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:37 PM PST 23
Peak memory 196468 kb
Host smart-3d601e93-1bea-4762-aacd-190b26ab568f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37251310676329636194752649226913696329837412545131373779704573572957754800427 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_long_reg_writes_reg_reads.372513106763296361947526492269136963298374125451
31373779704573572957754800427
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.57710590931133220646042662247672136232140132762641782392112093419715751780411
Short name T677
Test name
Test status
Simulation time 112796484 ps
CPU time 1.27 seconds
Started Nov 22 12:26:14 PM PST 23
Finished Nov 22 12:26:19 PM PST 23
Peak memory 195452 kb
Host smart-6a467b99-7ae8-4c6a-8566-232c4ba766f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57710590931133220646042662247672136232140132762641782392112093419715751780411 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.gpio_smoke.57710590931133220646042662247672136232140132762641782392112093419715751780411
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.100292811982112754906926870899800752318281253158621144132707138460611553199134
Short name T814
Test name
Test status
Simulation time 112796484 ps
CPU time 1.43 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 192976 kb
Host smart-27d9a9a4-d265-484f-a15d-4924a12525aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100292811982112754906926870899800752318281253158621144132707138460611553199134 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.100292811982112754906926870899800752318281253158621144132707138460611553199134
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.76525517931108775307723449615802207976607536212625892180087965612397907060179
Short name T701
Test name
Test status
Simulation time 21104521406 ps
CPU time 162.18 seconds
Started Nov 22 12:26:35 PM PST 23
Finished Nov 22 12:29:18 PM PST 23
Peak memory 198004 kb
Host smart-ff9b488e-d57a-4655-a81a-f46852989adf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7652551793110877530772344961580220797660753621262589218008796561
2397907060179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all.765255179311087753077234496158022079766075362126258921800879656
12397907060179
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.99789014483325489181878775721640208853911022133035375059884606203354191141094
Short name T414
Test name
Test status
Simulation time 133069054254 ps
CPU time 1089.77 seconds
Started Nov 22 12:27:04 PM PST 23
Finished Nov 22 12:45:21 PM PST 23
Peak memory 198172 kb
Host smart-ad48a908-d16c-4dd4-8a7a-97aa8c495d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=99789014483325489181878775721640208853911022133035375059884606203354191141094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_wi
th_rand_reset.99789014483325489181878775721640208853911022133035375059884606203354191141094
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.52517579873273273379139406785470751998711584612658165112312205766720429069425
Short name T316
Test name
Test status
Simulation time 22440064 ps
CPU time 0.57 seconds
Started Nov 22 12:24:42 PM PST 23
Finished Nov 22 12:24:44 PM PST 23
Peak memory 193864 kb
Host smart-6eb20d55-13d2-41c5-9e1c-de48ab9b26ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52517579873273273379139406785470751998711584612658165112312205766720429069425 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.gpio_alert_test.52517579873273273379139406785470751998711584612658165112312205766720429069425
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.18959253422664739191188468116744775371791857064695141947390925584435048408701
Short name T504
Test name
Test status
Simulation time 57921923 ps
CPU time 0.86 seconds
Started Nov 22 12:24:42 PM PST 23
Finished Nov 22 12:24:44 PM PST 23
Peak memory 196160 kb
Host smart-15da4736-b1c3-47b2-a78c-c2e527705123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18959253422664739191188468116744775371791857064695141947390925584435048408701 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.18959253422664739191188468116744775371791857064695141947390925584435048408701
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.89655573120198103681926029297596265750515410515252796868897625002625532674097
Short name T59
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.54 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:31 PM PST 23
Peak memory 193224 kb
Host smart-ded1c3e3-d14a-4cd7-91e8-053d39e97b6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89655573120198103681926029297596265750515410515252796868897625002625532674097 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress.89655573120198103681926029297596265750515410515252796868897625002625532674097
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.12983356476897976023895476520166295545818870083758114288291873785446689287128
Short name T343
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:24:39 PM PST 23
Finished Nov 22 12:24:41 PM PST 23
Peak memory 196284 kb
Host smart-74698bac-6d7c-4594-b568-54f1f5e0bdd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12983356476897976023895476520166295545818870083758114288291873785446689287128 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.12983356476897976023895476520166295545818870083758114288291873785446689287128
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.99691859937842871901070724654096398483772139023732612152579784263012323697116
Short name T497
Test name
Test status
Simulation time 119314289 ps
CPU time 1.23 seconds
Started Nov 22 12:25:15 PM PST 23
Finished Nov 22 12:25:17 PM PST 23
Peak memory 195604 kb
Host smart-27b0544e-ee63-4b23-a6af-ab46f5ab6885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99691859937842871901070724654096398483772139023732612152579784263012323697116 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.99691859937842871901070724654096398483772139023732612152579784263012323697116
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.72178706606144249861995857252431056690649625160894793391308276845957555740518
Short name T551
Test name
Test status
Simulation time 134635595 ps
CPU time 2.84 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 196764 kb
Host smart-6d5d8592-4325-4cbe-a4e1-eebbf11fdb87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72178706606144249861995857252431056690649625160894793391308276845957
555740518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.72178706606144249861995
857252431056690649625160894793391308276845957555740518
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.63296142253996766567799977095492693705119571036024249048859658582487900875407
Short name T807
Test name
Test status
Simulation time 228920555 ps
CPU time 2.78 seconds
Started Nov 22 12:24:39 PM PST 23
Finished Nov 22 12:24:43 PM PST 23
Peak memory 195740 kb
Host smart-c3eb1e63-1bb8-46d9-aeca-7f0ad2c3cb06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63296142253996766567799977095492693705119571036024249048859658582487900875407 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.63296142253996766567799977095492693705119571036024249048859658582487900875407
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.78000412743191004323783775134960493807105433610966633437665955328084049291873
Short name T423
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:26:25 PM PST 23
Finished Nov 22 12:26:31 PM PST 23
Peak memory 195656 kb
Host smart-a8b4b08c-435e-442e-962d-9d105356b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78000412743191004323783775134960493807105433610966633437665955328084049291873 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.gpio_random_dout_din.78000412743191004323783775134960493807105433610966633437665955328084049291873
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.58362199428691865538261601111702254545926610405964883138905732134000957091752
Short name T570
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:26:54 PM PST 23
Finished Nov 22 12:26:59 PM PST 23
Peak memory 195692 kb
Host smart-2f9355c5-dfff-436b-8cef-3d0a36f6e9c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58362199428691865538261601111702254545926610405964883138905732134000957091752 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup_pulldown.58362199428691865538261601111702254545926610405964883138905732134000957091752
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.23979169721381296527035915060114742423966602962478992441550889219745161666229
Short name T214
Test name
Test status
Simulation time 572864232 ps
CPU time 5.06 seconds
Started Nov 22 12:26:08 PM PST 23
Finished Nov 22 12:26:15 PM PST 23
Peak memory 197724 kb
Host smart-cd966545-24d6-48c7-bf04-f1e37aa4a513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979169721381296527035915060114742423966602962478992441550889219745161666229 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_long_reg_writes_reg_reads.239791697213812965270359150601147424239666029624
78992441550889219745161666229
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.8669791592386828785762859057482504518369982115112291398984051336820105690441
Short name T722
Test name
Test status
Simulation time 112796484 ps
CPU time 1.37 seconds
Started Nov 22 12:25:42 PM PST 23
Finished Nov 22 12:25:48 PM PST 23
Peak memory 195456 kb
Host smart-8cf5420f-11de-4090-8b5a-5f21dcf55c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8669791592386828785762859057482504518369982115112291398984051336820105690441 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.gpio_smoke.8669791592386828785762859057482504518369982115112291398984051336820105690441
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.27642360254511343221338316743189328285638764863656937336180523197453727779582
Short name T580
Test name
Test status
Simulation time 112796484 ps
CPU time 1.37 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:33 PM PST 23
Peak memory 194588 kb
Host smart-9119f6ac-0756-4a38-87db-979f7180363d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27642360254511343221338316743189328285638764863656937336180523197453727779582 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.27642360254511343221338316743189328285638764863656937336180523197453727779582
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.88678753340290206054825155553029036360759028127099899540728233794520222403784
Short name T227
Test name
Test status
Simulation time 21104521406 ps
CPU time 168.48 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:28:46 PM PST 23
Peak memory 196248 kb
Host smart-730cbd1b-88bb-48ba-be60-491722ddc4e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8867875334029020605482515555302903636075902812709989954072823379
4520222403784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all.886787533402902060548251555530290363607590281270998995407282337
94520222403784
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.103583900944911667832585680644174941339312506814991201642093585297630015553458
Short name T761
Test name
Test status
Simulation time 133069054254 ps
CPU time 1115.92 seconds
Started Nov 22 12:24:46 PM PST 23
Finished Nov 22 12:43:22 PM PST 23
Peak memory 198120 kb
Host smart-bb53342f-4cbe-4aa9-a8e5-1da1a00cda01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=103583900944911667832585680644174941339312506814991201642093585297630015553458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_w
ith_rand_reset.103583900944911667832585680644174941339312506814991201642093585297630015553458
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.44524526201580545156454195726789349290643900036544043262387670168185295788849
Short name T837
Test name
Test status
Simulation time 22440064 ps
CPU time 0.55 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:12 PM PST 23
Peak memory 193824 kb
Host smart-a4dedfc4-3945-426d-8844-a129e01a5d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44524526201580545156454195726789349290643900036544043262387670168185295788849 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.gpio_alert_test.44524526201580545156454195726789349290643900036544043262387670168185295788849
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.92968934063541335190982572857491056787878630591432409067285768088693085519032
Short name T556
Test name
Test status
Simulation time 57921923 ps
CPU time 0.87 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:13 PM PST 23
Peak memory 196128 kb
Host smart-a5dfda41-62bf-4dff-ab9b-d9f3be18e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92968934063541335190982572857491056787878630591432409067285768088693085519032 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.92968934063541335190982572857491056787878630591432409067285768088693085519032
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.115457173807654672950288678720562805920551722175343524778984666461135296162486
Short name T755
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.93 seconds
Started Nov 22 12:26:12 PM PST 23
Finished Nov 22 12:26:36 PM PST 23
Peak memory 195400 kb
Host smart-766fc445-2a60-4b90-aa32-5897c51d8074
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115457173807654672950288678720562805920551722175343524778984666461135296162486 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress.115457173807654672950288678720562805920551722175343524778984666461135296162486
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.7911658310830073321668221718967759214906588799237477870044449812000203181586
Short name T620
Test name
Test status
Simulation time 137439144 ps
CPU time 0.95 seconds
Started Nov 22 12:25:59 PM PST 23
Finished Nov 22 12:26:01 PM PST 23
Peak memory 196136 kb
Host smart-1e8ca7de-3d28-42a6-a7c6-819cee0ed495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7911658310830073321668221718967759214906588799237477870044449812000203181586 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.7911658310830073321668221718967759214906588799237477870044449812000203181586
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.96864812155925705648994151599660965970040912440240855732266927806119179772164
Short name T509
Test name
Test status
Simulation time 119314289 ps
CPU time 1.24 seconds
Started Nov 22 12:25:54 PM PST 23
Finished Nov 22 12:25:56 PM PST 23
Peak memory 195700 kb
Host smart-fd31c7b3-fdb2-41e5-9394-3cac7ef12250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96864812155925705648994151599660965970040912440240855732266927806119179772164 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.96864812155925705648994151599660965970040912440240855732266927806119179772164
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.98083526256873665128047767147456944109586839334384390789064188831901320963257
Short name T844
Test name
Test status
Simulation time 134635595 ps
CPU time 2.79 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 196528 kb
Host smart-c43d9775-4942-478e-b898-39f8a4a83c0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98083526256873665128047767147456944109586839334384390789064188831901
320963257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.98083526256873665128047
767147456944109586839334384390789064188831901320963257
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.17366582896773710957912573227443522340993627973056772029846698384030690922297
Short name T866
Test name
Test status
Simulation time 228920555 ps
CPU time 2.76 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:26:01 PM PST 23
Peak memory 193984 kb
Host smart-34c6ada5-c56e-4bce-96a7-aceb13ab522d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17366582896773710957912573227443522340993627973056772029846698384030690922297 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.17366582896773710957912573227443522340993627973056772029846698384030690922297
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.97770868325395814971688747808014236415316404621717332403818198027576112762484
Short name T583
Test name
Test status
Simulation time 81278879 ps
CPU time 1.11 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 195676 kb
Host smart-a89f3f7f-2565-4890-9d83-4693b810bb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97770868325395814971688747808014236415316404621717332403818198027576112762484 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.gpio_random_dout_din.97770868325395814971688747808014236415316404621717332403818198027576112762484
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.25711127964325379167230396036628323483974544474641434400758409392451612969379
Short name T397
Test name
Test status
Simulation time 81278879 ps
CPU time 1.15 seconds
Started Nov 22 12:24:44 PM PST 23
Finished Nov 22 12:24:46 PM PST 23
Peak memory 195708 kb
Host smart-e774a94a-8ede-48cd-8dbd-1ef6ee5475bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711127964325379167230396036628323483974544474641434400758409392451612969379 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup_pulldown.25711127964325379167230396036628323483974544474641434400758409392451612969379
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1139220708611653227907566581043428906316831250438806577537200188267187682636
Short name T318
Test name
Test status
Simulation time 572864232 ps
CPU time 4.98 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:26:14 PM PST 23
Peak memory 195748 kb
Host smart-59e065cf-7cc4-4b39-8ddf-82e623aa6538
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139220708611653227907566581043428906316831250438806577537200188267187682636 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_long_reg_writes_reg_reads.1139220708611653227907566581043428906316831250438
806577537200188267187682636
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.92360560824714952508519991302168945357133785571005791662244590382850980090662
Short name T650
Test name
Test status
Simulation time 112796484 ps
CPU time 1.24 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:26:00 PM PST 23
Peak memory 194972 kb
Host smart-4834674e-ecc5-4053-9af7-eb7f72103a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92360560824714952508519991302168945357133785571005791662244590382850980090662 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.gpio_smoke.92360560824714952508519991302168945357133785571005791662244590382850980090662
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.96945858227711981490196118606458071537171682308911931672475509980315247849224
Short name T559
Test name
Test status
Simulation time 112796484 ps
CPU time 1.21 seconds
Started Nov 22 12:27:06 PM PST 23
Finished Nov 22 12:27:14 PM PST 23
Peak memory 195424 kb
Host smart-3e0fc5ce-d8c6-4e8e-a88c-b7d09b41c378
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96945858227711981490196118606458071537171682308911931672475509980315247849224 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.96945858227711981490196118606458071537171682308911931672475509980315247849224
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.55271438759455452271631707597459548196997407465555356893687825337070915049067
Short name T682
Test name
Test status
Simulation time 21104521406 ps
CPU time 165.6 seconds
Started Nov 22 12:26:07 PM PST 23
Finished Nov 22 12:28:54 PM PST 23
Peak memory 195908 kb
Host smart-5281b1ca-c1de-4e43-9009-2e90f280d313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5527143875945545227163170759745954819699740746555535689368782533
7070915049067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all.552714387594554522716317075974595481969974074655553568936878253
37070915049067
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.59988482687817151809622753897469753283361015893489259485061733100716161772980
Short name T785
Test name
Test status
Simulation time 133069054254 ps
CPU time 1061.2 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:43:39 PM PST 23
Peak memory 196348 kb
Host smart-924bdcb2-a982-4c2a-b10b-38c8179126e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=59988482687817151809622753897469753283361015893489259485061733100716161772980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_wi
th_rand_reset.59988482687817151809622753897469753283361015893489259485061733100716161772980
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.34278519332536980954608388450258886176743857491467868128257251025919398957917
Short name T641
Test name
Test status
Simulation time 22440064 ps
CPU time 0.58 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:17 PM PST 23
Peak memory 193300 kb
Host smart-35964e95-1de8-4a52-992f-dea1c9863d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278519332536980954608388450258886176743857491467868128257251025919398957917 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.gpio_alert_test.34278519332536980954608388450258886176743857491467868128257251025919398957917
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.81926959692389069700178584267935452160407438770363776761280688632415964851034
Short name T659
Test name
Test status
Simulation time 57921923 ps
CPU time 0.81 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:17 PM PST 23
Peak memory 195948 kb
Host smart-c0a79d52-25c5-4bc3-86d0-2c804547c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81926959692389069700178584267935452160407438770363776761280688632415964851034 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.81926959692389069700178584267935452160407438770363776761280688632415964851034
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.32848622701875800877553649957573635461678404126519430355114777747924461364527
Short name T804
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.22 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:38 PM PST 23
Peak memory 194120 kb
Host smart-64556e5c-dcb2-4742-b03e-0088d6691806
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848622701875800877553649957573635461678404126519430355114777747924461364527 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stress.32848622701875800877553649957573635461678404126519430355114777747924461364527
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.78323324135393094375174641589122237738297750757218198094272818578101846723811
Short name T480
Test name
Test status
Simulation time 137439144 ps
CPU time 1.06 seconds
Started Nov 22 12:27:04 PM PST 23
Finished Nov 22 12:27:12 PM PST 23
Peak memory 195024 kb
Host smart-f5d4a85f-4559-472c-8c1a-537d9d7f8ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78323324135393094375174641589122237738297750757218198094272818578101846723811 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.78323324135393094375174641589122237738297750757218198094272818578101846723811
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.6328408482119347684712237218146930494159472357001249688750053377546944020141
Short name T824
Test name
Test status
Simulation time 119314289 ps
CPU time 1.11 seconds
Started Nov 22 12:26:29 PM PST 23
Finished Nov 22 12:26:32 PM PST 23
Peak memory 195620 kb
Host smart-44834b2d-63b2-4f61-830f-49a484496bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6328408482119347684712237218146930494159472357001249688750053377546944020141 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.6328408482119347684712237218146930494159472357001249688750053377546944020141
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.104431630911730765532876188526289621571165293769011730199663320795764369646653
Short name T624
Test name
Test status
Simulation time 134635595 ps
CPU time 2.67 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 196772 kb
Host smart-1025c3a3-5194-4943-b756-e4524349b115
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10443163091173076553287618852628962157116529376901173019966332079576
4369646653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1044316309117307655328
76188526289621571165293769011730199663320795764369646653
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.75677461944222565864091096359006588974338161303497906545268467842414029928733
Short name T825
Test name
Test status
Simulation time 228920555 ps
CPU time 2.78 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:19 PM PST 23
Peak memory 194496 kb
Host smart-58de293f-c9d4-414b-b17f-559d7aecb42d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75677461944222565864091096359006588974338161303497906545268467842414029928733 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.75677461944222565864091096359006588974338161303497906545268467842414029928733
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.55115248220746675430647085707727075386772117470503107945494855431790275000851
Short name T563
Test name
Test status
Simulation time 81278879 ps
CPU time 1.13 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 195584 kb
Host smart-94448894-8478-4362-aa63-b8117ec0b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55115248220746675430647085707727075386772117470503107945494855431790275000851 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.gpio_random_dout_din.55115248220746675430647085707727075386772117470503107945494855431790275000851
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.75690097185626623786318115929715252714413088598453071131222079119101946208024
Short name T56
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:01 PM PST 23
Peak memory 195352 kb
Host smart-817a3837-f06b-42ee-a6c1-43f150019071
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75690097185626623786318115929715252714413088598453071131222079119101946208024 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup_pulldown.75690097185626623786318115929715252714413088598453071131222079119101946208024
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.12486232468674280721965991263989796221665780204200194126354224262654892903784
Short name T772
Test name
Test status
Simulation time 572864232 ps
CPU time 4.91 seconds
Started Nov 22 12:27:57 PM PST 23
Finished Nov 22 12:28:03 PM PST 23
Peak memory 197784 kb
Host smart-9edf729b-fd26-4755-ae01-b894f23ed6ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12486232468674280721965991263989796221665780204200194126354224262654892903784 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_long_reg_writes_reg_reads.124862324686742807219659912639897962216657802042
00194126354224262654892903784
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.35372135996380117900192273238785576687734185002753264828826163037236089768652
Short name T619
Test name
Test status
Simulation time 112796484 ps
CPU time 1.33 seconds
Started Nov 22 12:26:51 PM PST 23
Finished Nov 22 12:26:56 PM PST 23
Peak memory 194528 kb
Host smart-170ca78b-d871-45a1-9c52-47b43c5cce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35372135996380117900192273238785576687734185002753264828826163037236089768652 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.gpio_smoke.35372135996380117900192273238785576687734185002753264828826163037236089768652
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.54894473094473694016953514917919229509840743181512412923232265908293611097313
Short name T864
Test name
Test status
Simulation time 112796484 ps
CPU time 1.21 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 195324 kb
Host smart-e045652f-b1dd-4068-affa-a22bdb730468
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54894473094473694016953514917919229509840743181512412923232265908293611097313 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.54894473094473694016953514917919229509840743181512412923232265908293611097313
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.54613593102128795207412971811153251580390339512994234399775371542081622121533
Short name T665
Test name
Test status
Simulation time 21104521406 ps
CPU time 172.14 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:29:24 PM PST 23
Peak memory 197964 kb
Host smart-bd3871aa-fe4d-444b-a9a6-271bd25157de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5461359310212879520741297181115325158039033951299423439977537154
2081622121533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all.546135931021287952074129718111532515803903395129942343997753715
42081622121533
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.100011141445049562864973595386651830316801676923633132712651569606478667052571
Short name T520
Test name
Test status
Simulation time 133069054254 ps
CPU time 1068.65 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:44:09 PM PST 23
Peak memory 197916 kb
Host smart-35ea68b3-569f-4029-9af5-adb97702c5b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=100011141445049562864973595386651830316801676923633132712651569606478667052571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_w
ith_rand_reset.100011141445049562864973595386651830316801676923633132712651569606478667052571
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.35423502744839607448266644041369411242174531310452556102228505992322193738586
Short name T422
Test name
Test status
Simulation time 22440064 ps
CPU time 0.62 seconds
Started Nov 22 12:20:52 PM PST 23
Finished Nov 22 12:20:54 PM PST 23
Peak memory 193840 kb
Host smart-fb305861-7190-4f47-b7c3-6c990db37bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35423502744839607448266644041369411242174531310452556102228505992322193738586 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.gpio_alert_test.35423502744839607448266644041369411242174531310452556102228505992322193738586
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.91283701156949499709041472054564859812743141117876407872180184085388212116041
Short name T513
Test name
Test status
Simulation time 57921923 ps
CPU time 0.91 seconds
Started Nov 22 12:22:19 PM PST 23
Finished Nov 22 12:22:21 PM PST 23
Peak memory 196160 kb
Host smart-c34775ba-2e3a-4611-9ae0-8eac36769d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91283701156949499709041472054564859812743141117876407872180184085388212116041 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.91283701156949499709041472054564859812743141117876407872180184085388212116041
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.77198136429741858640755577340512758431456044107879396838850910300735383690733
Short name T758
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.27 seconds
Started Nov 22 12:20:50 PM PST 23
Finished Nov 22 12:21:13 PM PST 23
Peak memory 195072 kb
Host smart-4401ff59-77f4-43f7-a281-d03fcdb486c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77198136429741858640755577340512758431456044107879396838850910300735383690733 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress.77198136429741858640755577340512758431456044107879396838850910300735383690733
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.113521465009251586861417785897146185853263016748695448630504343905160721227433
Short name T823
Test name
Test status
Simulation time 137439144 ps
CPU time 1.11 seconds
Started Nov 22 12:27:38 PM PST 23
Finished Nov 22 12:27:49 PM PST 23
Peak memory 195436 kb
Host smart-2b657349-6a4a-4799-8e37-f2c55aae30fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113521465009251586861417785897146185853263016748695448630504343905160721227433 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.113521465009251586861417785897146185853263016748695448630504343905160721227433
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.100589662604426873576311860155948240345939753347317818666980259954446922284018
Short name T845
Test name
Test status
Simulation time 119314289 ps
CPU time 1.26 seconds
Started Nov 22 12:22:19 PM PST 23
Finished Nov 22 12:22:21 PM PST 23
Peak memory 195040 kb
Host smart-8e2e3856-5faa-476f-a105-0fad283e8df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100589662604426873576311860155948240345939753347317818666980259954446922284018 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.100589662604426873576311860155948240345939753347317818666980259954446922284018
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.84590582567245179142472914807395715793279550918576598351870289577503982323478
Short name T374
Test name
Test status
Simulation time 134635595 ps
CPU time 3.35 seconds
Started Nov 22 12:27:02 PM PST 23
Finished Nov 22 12:27:13 PM PST 23
Peak memory 195516 kb
Host smart-6f952124-012f-4688-97b0-992d03e28cdb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84590582567245179142472914807395715793279550918576598351870289577503
982323478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.845905825672451791424729
14807395715793279550918576598351870289577503982323478
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.85284021536002811037048890860301673224764293006437439448672494600989322940169
Short name T635
Test name
Test status
Simulation time 228920555 ps
CPU time 2.73 seconds
Started Nov 22 12:27:13 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 195432 kb
Host smart-fd52c96e-2a72-4b68-9d9e-728bb7ee45b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85284021536002811037048890860301673224764293006437439448672494600989322940169 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.85284021536002811037048890860301673224764293006437439448672494600989322940169
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.105542334535759502993513717034387379010631238744989082721832435046536593612179
Short name T544
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:24:30 PM PST 23
Finished Nov 22 12:24:32 PM PST 23
Peak memory 195648 kb
Host smart-a0086b1e-8e45-4086-ad0d-37e08ddcbc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105542334535759502993513717034387379010631238744989082721832435046536593612179 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_random_dout_din.105542334535759502993513717034387379010631238744989082721832435046536593612179
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.61133776887584563630114639551239459210169246144217462524875335976173730451905
Short name T379
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:26:47 PM PST 23
Finished Nov 22 12:26:50 PM PST 23
Peak memory 195800 kb
Host smart-cee478a7-a62e-4351-a6c5-08c0b24f8c49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61133776887584563630114639551239459210169246144217462524875335976173730451905 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_pulldown.61133776887584563630114639551239459210169246144217462524875335976173730451905
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.71583219788488597187614362349662165069414484573621199397401971177587283524801
Short name T273
Test name
Test status
Simulation time 572864232 ps
CPU time 5.17 seconds
Started Nov 22 12:20:51 PM PST 23
Finished Nov 22 12:20:57 PM PST 23
Peak memory 197636 kb
Host smart-88788ed9-b037-4255-be62-e50690ab2758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71583219788488597187614362349662165069414484573621199397401971177587283524801 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_long_reg_writes_reg_reads.7158321978848859718761436234966216506941448457362
1199397401971177587283524801
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.93747645022067327491177359359323999326954846676664848349603577220986384344561
Short name T366
Test name
Test status
Simulation time 112796484 ps
CPU time 1.27 seconds
Started Nov 22 12:22:19 PM PST 23
Finished Nov 22 12:22:21 PM PST 23
Peak memory 195444 kb
Host smart-4ea3aa34-e046-4a3c-9a60-ce8cfe010a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93747645022067327491177359359323999326954846676664848349603577220986384344561 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.gpio_smoke.93747645022067327491177359359323999326954846676664848349603577220986384344561
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.74546223058753119213113421137131285898113870042302068732288259347875983910433
Short name T354
Test name
Test status
Simulation time 112796484 ps
CPU time 1.28 seconds
Started Nov 22 12:21:03 PM PST 23
Finished Nov 22 12:21:05 PM PST 23
Peak memory 195400 kb
Host smart-6e545fff-ece6-459b-8475-cc9509a00fc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74546223058753119213113421137131285898113870042302068732288259347875983910433 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.74546223058753119213113421137131285898113870042302068732288259347875983910433
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.9897244038315868632422477583230480554653013960633055956027227642681937844455
Short name T604
Test name
Test status
Simulation time 21104521406 ps
CPU time 167.51 seconds
Started Nov 22 12:26:22 PM PST 23
Finished Nov 22 12:29:15 PM PST 23
Peak memory 197496 kb
Host smart-e7f0b971-f3c1-4287-922f-95a46cb5ef0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9897244038315868632422477583230480554653013960633055956027227642
681937844455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all.9897244038315868632422477583230480554653013960633055956027227642681937844455
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.109223826281388334140672296877010770173602879261722300944292636283035254227219
Short name T61
Test name
Test status
Simulation time 22440064 ps
CPU time 0.56 seconds
Started Nov 22 12:27:40 PM PST 23
Finished Nov 22 12:27:49 PM PST 23
Peak memory 193416 kb
Host smart-880b40e8-1516-4e1c-a44d-1b8b5f12c5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109223826281388334140672296877010770173602879261722300944292636283035254227219 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.109223826281388334140672296877010770173602879261722300944292636283035254227219
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.45609634705998978801249557942700222241274329748214984493703703531710508521593
Short name T852
Test name
Test status
Simulation time 57921923 ps
CPU time 0.91 seconds
Started Nov 22 12:26:03 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 195312 kb
Host smart-01f9f511-0f6b-4c41-bcc8-101c8fdf8e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45609634705998978801249557942700222241274329748214984493703703531710508521593 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.45609634705998978801249557942700222241274329748214984493703703531710508521593
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.95535171721626265155125926397784386157207202322247284562711061477935575875784
Short name T529
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.72 seconds
Started Nov 22 12:27:46 PM PST 23
Finished Nov 22 12:28:14 PM PST 23
Peak memory 195140 kb
Host smart-cdad5d3e-0592-421c-b798-b5b8ebb9993f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95535171721626265155125926397784386157207202322247284562711061477935575875784 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress.95535171721626265155125926397784386157207202322247284562711061477935575875784
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.115347301206813289346095452771913273671279052980781093055993423129738353065266
Short name T425
Test name
Test status
Simulation time 137439144 ps
CPU time 0.95 seconds
Started Nov 22 12:27:54 PM PST 23
Finished Nov 22 12:27:57 PM PST 23
Peak memory 196148 kb
Host smart-1709dcc9-3769-4e61-b568-787cf9e42054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115347301206813289346095452771913273671279052980781093055993423129738353065266 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.115347301206813289346095452771913273671279052980781093055993423129738353065266
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.72215560601753535605226750820716341605612086174918027181210127036287208003692
Short name T744
Test name
Test status
Simulation time 119314289 ps
CPU time 1.33 seconds
Started Nov 22 12:27:44 PM PST 23
Finished Nov 22 12:27:52 PM PST 23
Peak memory 195388 kb
Host smart-41d7ce00-724c-4ecc-9ae7-916764a63f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72215560601753535605226750820716341605612086174918027181210127036287208003692 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.72215560601753535605226750820716341605612086174918027181210127036287208003692
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.27313843206813793231927670370332223649244643293421465943139468656535580885184
Short name T818
Test name
Test status
Simulation time 134635595 ps
CPU time 2.83 seconds
Started Nov 22 12:27:42 PM PST 23
Finished Nov 22 12:27:52 PM PST 23
Peak memory 196824 kb
Host smart-adff04ee-97f3-49d6-81a9-64c2c0485ed0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27313843206813793231927670370332223649244643293421465943139468656535
580885184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.273138432068137932319276
70370332223649244643293421465943139468656535580885184
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.73512497161023137600947116066657058658230574935267393691567206550357969190749
Short name T324
Test name
Test status
Simulation time 228920555 ps
CPU time 2.72 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 195276 kb
Host smart-d3b342d7-0784-4d51-94f0-d7e8f099293d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73512497161023137600947116066657058658230574935267393691567206550357969190749 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.73512497161023137600947116066657058658230574935267393691567206550357969190749
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.37344717346891052632613433843704879792667424732041165978383073437685778611281
Short name T565
Test name
Test status
Simulation time 81278879 ps
CPU time 1.12 seconds
Started Nov 22 12:23:55 PM PST 23
Finished Nov 22 12:24:01 PM PST 23
Peak memory 195696 kb
Host smart-406ffc0b-ce3e-4fcd-81ed-8b37cb4162c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37344717346891052632613433843704879792667424732041165978383073437685778611281 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.gpio_random_dout_din.37344717346891052632613433843704879792667424732041165978383073437685778611281
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.11570686389325162759399051258345979951841167872072149526831797534686700705831
Short name T211
Test name
Test status
Simulation time 81278879 ps
CPU time 1.14 seconds
Started Nov 22 12:26:55 PM PST 23
Finished Nov 22 12:27:01 PM PST 23
Peak memory 193560 kb
Host smart-2a7f5efb-cff7-48ae-b52f-5ff2470556e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570686389325162759399051258345979951841167872072149526831797534686700705831 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_pulldown.11570686389325162759399051258345979951841167872072149526831797534686700705831
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.33362357589142240779688962267686874067100104239981588693922375571718372812883
Short name T743
Test name
Test status
Simulation time 572864232 ps
CPU time 5.33 seconds
Started Nov 22 12:21:54 PM PST 23
Finished Nov 22 12:22:00 PM PST 23
Peak memory 197708 kb
Host smart-633fa798-e816-4161-95d3-9b7004774277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362357589142240779688962267686874067100104239981588693922375571718372812883 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_long_reg_writes_reg_reads.3336235758914224077968896226768687406710010423998
1588693922375571718372812883
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.27767719050764037167999648033332877607668824047454825749602917805668988206517
Short name T76
Test name
Test status
Simulation time 112796484 ps
CPU time 1.2 seconds
Started Nov 22 12:28:38 PM PST 23
Finished Nov 22 12:28:40 PM PST 23
Peak memory 195452 kb
Host smart-43ec8796-36e9-4dd1-b596-cdb3a595f054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27767719050764037167999648033332877607668824047454825749602917805668988206517 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.gpio_smoke.27767719050764037167999648033332877607668824047454825749602917805668988206517
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.45300068665298919593706275590670243103712940465023869506241334104862956420223
Short name T494
Test name
Test status
Simulation time 112796484 ps
CPU time 1.51 seconds
Started Nov 22 12:24:54 PM PST 23
Finished Nov 22 12:24:57 PM PST 23
Peak memory 194540 kb
Host smart-7966f4c9-c0c0-49a6-ad7a-34dbb3ec9698
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45300068665298919593706275590670243103712940465023869506241334104862956420223 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.45300068665298919593706275590670243103712940465023869506241334104862956420223
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.109699634516850192562212191158374329000711311228251461322082236025241268078910
Short name T411
Test name
Test status
Simulation time 21104521406 ps
CPU time 156.85 seconds
Started Nov 22 12:27:40 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 197556 kb
Host smart-9758c970-79dd-436f-b044-304a47b61d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096996345168501925622121911583743290007113112282514613220822360
25241268078910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all.109699634516850192562212191158374329000711311228251461322082236
025241268078910
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.92067957624699570462964063538422461341707182512264785163556469073590571378926
Short name T516
Test name
Test status
Simulation time 133069054254 ps
CPU time 1054.99 seconds
Started Nov 22 12:28:19 PM PST 23
Finished Nov 22 12:45:55 PM PST 23
Peak memory 197760 kb
Host smart-6af4b3d4-ed8a-4130-9d87-bceaebd034f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=92067957624699570462964063538422461341707182512264785163556469073590571378926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_wit
h_rand_reset.92067957624699570462964063538422461341707182512264785163556469073590571378926
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.111598753294409065079559415559373786296603569805988218773880606353519622678238
Short name T630
Test name
Test status
Simulation time 22440064 ps
CPU time 0.58 seconds
Started Nov 22 12:25:57 PM PST 23
Finished Nov 22 12:25:59 PM PST 23
Peak memory 193540 kb
Host smart-1c40de6e-3f41-45c9-9974-cbfedf07c585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111598753294409065079559415559373786296603569805988218773880606353519622678238 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.111598753294409065079559415559373786296603569805988218773880606353519622678238
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.94212779129457119403478547472569609624152475774566015442248075249261675914452
Short name T454
Test name
Test status
Simulation time 57921923 ps
CPU time 0.83 seconds
Started Nov 22 12:24:29 PM PST 23
Finished Nov 22 12:24:31 PM PST 23
Peak memory 196160 kb
Host smart-7587c524-918d-46d8-be99-ac91ead661d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94212779129457119403478547472569609624152475774566015442248075249261675914452 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.94212779129457119403478547472569609624152475774566015442248075249261675914452
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.71850834537261860824439065031257406969358957949791677277787523020523570523846
Short name T661
Test name
Test status
Simulation time 1135699015 ps
CPU time 21.39 seconds
Started Nov 22 12:27:58 PM PST 23
Finished Nov 22 12:28:20 PM PST 23
Peak memory 195464 kb
Host smart-fe639c4a-a3cd-4c42-8793-a81dd4ea4df1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71850834537261860824439065031257406969358957949791677277787523020523570523846 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress.71850834537261860824439065031257406969358957949791677277787523020523570523846
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.98905735183601375366469120712870818185896822011078275779423720559097428135314
Short name T409
Test name
Test status
Simulation time 137439144 ps
CPU time 0.94 seconds
Started Nov 22 12:22:09 PM PST 23
Finished Nov 22 12:22:10 PM PST 23
Peak memory 196180 kb
Host smart-73345e40-2039-482d-b66a-489befc28466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98905735183601375366469120712870818185896822011078275779423720559097428135314 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.98905735183601375366469120712870818185896822011078275779423720559097428135314
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.74716336257552921334266464068255379149483486970995847784974766599926277264602
Short name T467
Test name
Test status
Simulation time 119314289 ps
CPU time 1.2 seconds
Started Nov 22 12:21:24 PM PST 23
Finished Nov 22 12:21:27 PM PST 23
Peak memory 195672 kb
Host smart-984a23c1-18dc-4804-814e-2c61d2088253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74716336257552921334266464068255379149483486970995847784974766599926277264602 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.74716336257552921334266464068255379149483486970995847784974766599926277264602
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.35968699728723173591989034746368894188879579095234750927811480669141030175461
Short name T82
Test name
Test status
Simulation time 134635595 ps
CPU time 2.88 seconds
Started Nov 22 12:26:22 PM PST 23
Finished Nov 22 12:26:31 PM PST 23
Peak memory 196520 kb
Host smart-fee4eaa1-3ad9-43ad-8c15-6e4e8b01c959
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35968699728723173591989034746368894188879579095234750927811480669141
030175461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.359686997287231735919890
34746368894188879579095234750927811480669141030175461
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.109482403778264266320742135104681561663929691158145812591461025781024847977415
Short name T640
Test name
Test status
Simulation time 228920555 ps
CPU time 2.8 seconds
Started Nov 22 12:20:49 PM PST 23
Finished Nov 22 12:20:53 PM PST 23
Peak memory 194632 kb
Host smart-d5f88e77-fb8f-47c2-8ffb-7295efc68f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109482403778264266320742135104681561663929691158145812591461025781024847977415 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.109482403778264266320742135104681561663929691158145812591461025781024847977415
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3800469230401892371891973853153000570074096080642238312383592764444797249341
Short name T346
Test name
Test status
Simulation time 81278879 ps
CPU time 1.09 seconds
Started Nov 22 12:27:41 PM PST 23
Finished Nov 22 12:27:50 PM PST 23
Peak memory 195360 kb
Host smart-4a4d9424-24ca-48fd-a8fe-39126a574846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800469230401892371891973853153000570074096080642238312383592764444797249341 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_random_dout_din.3800469230401892371891973853153000570074096080642238312383592764444797249341
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.40516070479758088058773420296964082992932297297095593200350219905471747675614
Short name T358
Test name
Test status
Simulation time 81278879 ps
CPU time 1.29 seconds
Started Nov 22 12:27:47 PM PST 23
Finished Nov 22 12:27:54 PM PST 23
Peak memory 194680 kb
Host smart-3a179742-b6db-44aa-bac2-1b16bec31346
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40516070479758088058773420296964082992932297297095593200350219905471747675614 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_pulldown.40516070479758088058773420296964082992932297297095593200350219905471747675614
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_smoke.74923377595833975774895213999752140112394708711397623587231682158647808311834
Short name T787
Test name
Test status
Simulation time 112796484 ps
CPU time 1.19 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 195444 kb
Host smart-5955c647-810a-4266-a09f-e96559e0ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74923377595833975774895213999752140112394708711397623587231682158647808311834 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.gpio_smoke.74923377595833975774895213999752140112394708711397623587231682158647808311834
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.70883491691901612560716759887981626255623980009314223702410670918888182009287
Short name T597
Test name
Test status
Simulation time 112796484 ps
CPU time 1.26 seconds
Started Nov 22 12:22:51 PM PST 23
Finished Nov 22 12:22:53 PM PST 23
Peak memory 195464 kb
Host smart-0f644744-1888-4da3-9bb2-272364adc5c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70883491691901612560716759887981626255623980009314223702410670918888182009287 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.70883491691901612560716759887981626255623980009314223702410670918888182009287
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.87906803873873563281520515382108162575936618473427446178570886921960806480468
Short name T733
Test name
Test status
Simulation time 21104521406 ps
CPU time 171.13 seconds
Started Nov 22 12:26:36 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 198024 kb
Host smart-f46e88c4-2b1b-45b5-90e2-fa7ac1fa7408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8790680387387356328152051538210816257593661847342744617857088692
1960806480468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all.8790680387387356328152051538210816257593661847342744617857088692
1960806480468
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3528197506711825925571369878476786155636987064970395810346887377628189522889
Short name T483
Test name
Test status
Simulation time 133069054254 ps
CPU time 1125.71 seconds
Started Nov 22 12:20:58 PM PST 23
Finished Nov 22 12:39:44 PM PST 23
Peak memory 198152 kb
Host smart-5705ffb0-468f-425f-956a-77a260005403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3528197506711825925571369878476786155636987064970395810346887377628189522889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with
_rand_reset.3528197506711825925571369878476786155636987064970395810346887377628189522889
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.109504546735407959447752416484134280533489734241436323116888776380496266211940
Short name T784
Test name
Test status
Simulation time 22440064 ps
CPU time 0.59 seconds
Started Nov 22 12:20:58 PM PST 23
Finished Nov 22 12:21:00 PM PST 23
Peak memory 193820 kb
Host smart-9472dc06-9523-4da4-8b2e-85366cc0f4a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109504546735407959447752416484134280533489734241436323116888776380496266211940 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.109504546735407959447752416484134280533489734241436323116888776380496266211940
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.35502626455531620533043205918378176296551096910934602195700943296378207642366
Short name T325
Test name
Test status
Simulation time 57921923 ps
CPU time 0.88 seconds
Started Nov 22 12:20:57 PM PST 23
Finished Nov 22 12:20:59 PM PST 23
Peak memory 196276 kb
Host smart-d2957f30-9936-4d98-89d4-5653ff70cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35502626455531620533043205918378176296551096910934602195700943296378207642366 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.35502626455531620533043205918378176296551096910934602195700943296378207642366
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.100936978291228616121415018729956857226607578165815778747358652393095641269698
Short name T271
Test name
Test status
Simulation time 1135699015 ps
CPU time 23.43 seconds
Started Nov 22 12:25:35 PM PST 23
Finished Nov 22 12:26:05 PM PST 23
Peak memory 195412 kb
Host smart-b480d3df-a409-4c92-b649-69f240cff98a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100936978291228616121415018729956857226607578165815778747358652393095641269698 -ass
ert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress.100936978291228616121415018729956857226607578165815778747358652393095641269698
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.41907544324849924718652459511945492015545251813276916666920652070239423176685
Short name T647
Test name
Test status
Simulation time 137439144 ps
CPU time 0.98 seconds
Started Nov 22 12:20:57 PM PST 23
Finished Nov 22 12:20:58 PM PST 23
Peak memory 196328 kb
Host smart-4b4527b7-9ff2-44bd-93b7-d8ae96bc4300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41907544324849924718652459511945492015545251813276916666920652070239423176685 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.41907544324849924718652459511945492015545251813276916666920652070239423176685
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.63203080122040660622319467290810860237711740267494531212543373673700963402391
Short name T438
Test name
Test status
Simulation time 119314289 ps
CPU time 1.25 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 195672 kb
Host smart-5d668563-4a63-456a-80e5-8b6b3bfa0144
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63203080122040660622319467290810860237711740267494531212543373673700963402391 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.63203080122040660622319467290810860237711740267494531212543373673700963402391
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.62840883205070781727446198637525203313474100334101206676496857730324321632790
Short name T337
Test name
Test status
Simulation time 134635595 ps
CPU time 2.96 seconds
Started Nov 22 12:20:58 PM PST 23
Finished Nov 22 12:21:02 PM PST 23
Peak memory 197060 kb
Host smart-f09f5421-d450-477b-a68d-8b1ae4f19770
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62840883205070781727446198637525203313474100334101206676496857730324
321632790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.628408832050707817274461
98637525203313474100334101206676496857730324321632790
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.58814606375611748331755131949537621060632724553399071482781986002797500204188
Short name T408
Test name
Test status
Simulation time 228920555 ps
CPU time 3.02 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:35 PM PST 23
Peak memory 194036 kb
Host smart-c046177e-bb30-46fa-a844-cd47083cf9e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58814606375611748331755131949537621060632724553399071482781986002797500204188 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.58814606375611748331755131949537621060632724553399071482781986002797500204188
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.94676327048323987970819861689973533607917421448369632401057354327183389237334
Short name T655
Test name
Test status
Simulation time 81278879 ps
CPU time 1.2 seconds
Started Nov 22 12:25:35 PM PST 23
Finished Nov 22 12:25:43 PM PST 23
Peak memory 195544 kb
Host smart-b1a07f26-4015-4143-804e-a8f68f0d241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94676327048323987970819861689973533607917421448369632401057354327183389237334 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.gpio_random_dout_din.94676327048323987970819861689973533607917421448369632401057354327183389237334
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.100902164165808762911112728808562985327029258091314612438051046173982190876359
Short name T459
Test name
Test status
Simulation time 81278879 ps
CPU time 1.17 seconds
Started Nov 22 12:26:01 PM PST 23
Finished Nov 22 12:26:03 PM PST 23
Peak memory 194076 kb
Host smart-10b8bf86-a10f-4a5e-9ca7-a6e9458c047e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100902164165808762911112728808562985327029258091314612438051046173982190876359 -assert nopostproc
+UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_pulldown.100902164165808762911112728808562985327029258091314612438051046173982190876359
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.11351919181004003985253414249823758853224331824613918975437990621924798371803
Short name T405
Test name
Test status
Simulation time 572864232 ps
CPU time 5.15 seconds
Started Nov 22 12:22:09 PM PST 23
Finished Nov 22 12:22:15 PM PST 23
Peak memory 197664 kb
Host smart-bfddb193-19fb-4ba6-b2ab-83d85e4c9c48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351919181004003985253414249823758853224331824613918975437990621924798371803 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_long_reg_writes_reg_reads.1135191918100400398525341424982375885322433182461
3918975437990621924798371803
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.84993912837912324996417060646874141743863917515918425318829935733678002243669
Short name T796
Test name
Test status
Simulation time 112796484 ps
CPU time 1.4 seconds
Started Nov 22 12:26:31 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 195464 kb
Host smart-642a0835-1f4a-438d-ad31-79c4f429bb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84993912837912324996417060646874141743863917515918425318829935733678002243669 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.gpio_smoke.84993912837912324996417060646874141743863917515918425318829935733678002243669
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.67612147159078603145970092449900274589641501106167534695046660775096651676637
Short name T347
Test name
Test status
Simulation time 112796484 ps
CPU time 1.37 seconds
Started Nov 22 12:22:09 PM PST 23
Finished Nov 22 12:22:11 PM PST 23
Peak memory 195340 kb
Host smart-4bc14666-72ab-44ca-a006-f435db8b9448
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67612147159078603145970092449900274589641501106167534695046660775096651676637 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.67612147159078603145970092449900274589641501106167534695046660775096651676637
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.91849091940828073453305569005013243297201786927876110736507566165803145405318
Short name T502
Test name
Test status
Simulation time 21104521406 ps
CPU time 168.65 seconds
Started Nov 22 12:20:56 PM PST 23
Finished Nov 22 12:23:46 PM PST 23
Peak memory 197916 kb
Host smart-6076b851-3545-4e2b-b096-ce9047641689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9184909194082807345330556900501324329720178692787611073650756616
5803145405318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all.9184909194082807345330556900501324329720178692787611073650756616
5803145405318
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.717245963650635973595990553455705056591867134471915867842588703508479681881
Short name T718
Test name
Test status
Simulation time 133069054254 ps
CPU time 1090.34 seconds
Started Nov 22 12:25:58 PM PST 23
Finished Nov 22 12:44:09 PM PST 23
Peak memory 197892 kb
Host smart-965a417b-5153-4b9a-9d39-c695f3562e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=717245963650635973595990553455705056591867134471915867842588703508479681881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_
rand_reset.717245963650635973595990553455705056591867134471915867842588703508479681881
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.112604924977526340862266828057549895215160461355121111448805511107937819539515
Short name T863
Test name
Test status
Simulation time 22440064 ps
CPU time 0.54 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:26:56 PM PST 23
Peak memory 193804 kb
Host smart-4512f87b-62ed-4087-866c-f577c91be7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112604924977526340862266828057549895215160461355121111448805511107937819539515 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.112604924977526340862266828057549895215160461355121111448805511107937819539515
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.86437634011835302609852986383823660823641837646930117565713167761564284358001
Short name T617
Test name
Test status
Simulation time 57921923 ps
CPU time 0.9 seconds
Started Nov 22 12:26:59 PM PST 23
Finished Nov 22 12:27:07 PM PST 23
Peak memory 196164 kb
Host smart-9124ffcb-0e73-4cce-aad2-cd0dbc9aad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86437634011835302609852986383823660823641837646930117565713167761564284358001 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.86437634011835302609852986383823660823641837646930117565713167761564284358001
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.7530757948352840670169885844252407597744986562695136346905440618453081262356
Short name T322
Test name
Test status
Simulation time 1135699015 ps
CPU time 22.57 seconds
Started Nov 22 12:26:08 PM PST 23
Finished Nov 22 12:26:32 PM PST 23
Peak memory 195436 kb
Host smart-ae42e5da-9d9e-4a12-9e7c-83ea91227605
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7530757948352840670169885844252407597744986562695136346905440618453081262356 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress.7530757948352840670169885844252407597744986562695136346905440618453081262356
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.115106744902776558374527221393048618273312785005942957301785652654894319488093
Short name T233
Test name
Test status
Simulation time 137439144 ps
CPU time 0.92 seconds
Started Nov 22 12:26:54 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 196288 kb
Host smart-00f06c21-fb72-4909-ae5c-8d42f8afd9ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115106744902776558374527221393048618273312785005942957301785652654894319488093 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.115106744902776558374527221393048618273312785005942957301785652654894319488093
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.14816508933422958303234546713289176780965346326010899874480550599079136894327
Short name T340
Test name
Test status
Simulation time 119314289 ps
CPU time 1.3 seconds
Started Nov 22 12:26:31 PM PST 23
Finished Nov 22 12:26:34 PM PST 23
Peak memory 195680 kb
Host smart-a196e5c1-1160-4f1d-8fc7-dfb8cad29d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14816508933422958303234546713289176780965346326010899874480550599079136894327 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.14816508933422958303234546713289176780965346326010899874480550599079136894327
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.70950805003366404458608615098663687643426972152458519894296477487680028032717
Short name T537
Test name
Test status
Simulation time 134635595 ps
CPU time 3.11 seconds
Started Nov 22 12:20:57 PM PST 23
Finished Nov 22 12:21:01 PM PST 23
Peak memory 197200 kb
Host smart-c163acb2-6387-48c2-a32e-e57258003add
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70950805003366404458608615098663687643426972152458519894296477487680
028032717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.709508050033664044586086
15098663687643426972152458519894296477487680028032717
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.71469933494298764769455873862712375142210667652944499573122618755536085225589
Short name T674
Test name
Test status
Simulation time 228920555 ps
CPU time 2.9 seconds
Started Nov 22 12:21:59 PM PST 23
Finished Nov 22 12:22:05 PM PST 23
Peak memory 195684 kb
Host smart-73f083d4-98b9-408f-9aac-305f8a89fa39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71469933494298764769455873862712375142210667652944499573122618755536085225589 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.71469933494298764769455873862712375142210667652944499573122618755536085225589
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.73219425056547286613755750295238258248043116258704799338520840375640654280304
Short name T238
Test name
Test status
Simulation time 81278879 ps
CPU time 1.19 seconds
Started Nov 22 12:26:57 PM PST 23
Finished Nov 22 12:27:04 PM PST 23
Peak memory 195908 kb
Host smart-eb461bee-fa99-49b8-8352-a954c4fa9c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73219425056547286613755750295238258248043116258704799338520840375640654280304 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.gpio_random_dout_din.73219425056547286613755750295238258248043116258704799338520840375640654280304
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1765605111619208053355804961637521275999587074791002468239144924000238426799
Short name T317
Test name
Test status
Simulation time 81278879 ps
CPU time 1.2 seconds
Started Nov 22 12:25:42 PM PST 23
Finished Nov 22 12:25:46 PM PST 23
Peak memory 195680 kb
Host smart-ffdc1aaa-1060-4dcf-90f7-2ed271ec722d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765605111619208053355804961637521275999587074791002468239144924000238426799 -assert nopostproc +U
VM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_pulldown.1765605111619208053355804961637521275999587074791002468239144924000238426799
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.10634111750013240337028875138773454648454358599148608431754712432412846331995
Short name T395
Test name
Test status
Simulation time 572864232 ps
CPU time 5.35 seconds
Started Nov 22 12:26:30 PM PST 23
Finished Nov 22 12:26:38 PM PST 23
Peak memory 195120 kb
Host smart-bc7ee4fb-e294-4ebe-b357-9043a5ac0b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10634111750013240337028875138773454648454358599148608431754712432412846331995 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_long_reg_writes_reg_reads.1063411175001324033702887513877345464845435859914
8608431754712432412846331995
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.30506584732041952681865665158287124502768241459919242292074824810008094707507
Short name T868
Test name
Test status
Simulation time 112796484 ps
CPU time 1.29 seconds
Started Nov 22 12:25:35 PM PST 23
Finished Nov 22 12:25:43 PM PST 23
Peak memory 195448 kb
Host smart-3dd483a3-5c10-4410-a26b-ddac313a6209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30506584732041952681865665158287124502768241459919242292074824810008094707507 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.gpio_smoke.30506584732041952681865665158287124502768241459919242292074824810008094707507
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.54752649233106071277487137324913852977129290590125374389257175534132727465549
Short name T406
Test name
Test status
Simulation time 112796484 ps
CPU time 1.44 seconds
Started Nov 22 12:27:31 PM PST 23
Finished Nov 22 12:27:41 PM PST 23
Peak memory 192416 kb
Host smart-58b4cbd4-1bbb-49fb-a4de-a6c06b9427ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54752649233106071277487137324913852977129290590125374389257175534132727465549 -assert nopostproc +
UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.54752649233106071277487137324913852977129290590125374389257175534132727465549
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.103080149947205850721749088263501937690217319743999964861632981730484247537900
Short name T393
Test name
Test status
Simulation time 21104521406 ps
CPU time 157.94 seconds
Started Nov 22 12:27:04 PM PST 23
Finished Nov 22 12:29:49 PM PST 23
Peak memory 196764 kb
Host smart-cd89b212-eb26-4417-8b3d-022f9332c67a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030801499472058507217490882635019376902173197439999648616329817
30484247537900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all.103080149947205850721749088263501937690217319743999964861632981
730484247537900
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.17414634875565883470059197244836010696036532592120565740644543550551349709278
Short name T298
Test name
Test status
Simulation time 133069054254 ps
CPU time 1114.72 seconds
Started Nov 22 12:21:08 PM PST 23
Finished Nov 22 12:39:44 PM PST 23
Peak memory 198080 kb
Host smart-ac3df9b8-1717-447a-91db-d8d3dcc8b0bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=17414634875565883470059197244836010696036532592120565740644543550551349709278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_wit
h_rand_reset.17414634875565883470059197244836010696036532592120565740644543550551349709278
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.63417842101421813215569074043996112344920504742441708499433368559006611026723
Short name T130
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:08 PM PST 23
Finished Nov 22 12:27:15 PM PST 23
Peak memory 195088 kb
Host smart-a7183ab7-7814-419d-a0ff-222a530759d4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=63417842101421813215569074043996112344920504742441708499433368559006611026723 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 0.gpio_smoke_en_cdc_prim.63417842101421813215569074043996112344920504742441708499433368559006611026723
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.105004075297714165129874942611448377272476951984872549348247920988704198451482
Short name T138
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:26:21 PM PST 23
Finished Nov 22 12:26:27 PM PST 23
Peak memory 194868 kb
Host smart-092dc131-2d6e-4e78-83d4-3bd510d1ebe6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105004075297714165129874942611448377272476951984872549348247920988704198451482 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.105004075297714165129874942611448377272476951984872549348247920988704198451482
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.28576896438778823867797233212844518963463614795883131733003019678381487537272
Short name T69
Test name
Test status
Simulation time 115064323 ps
CPU time 1.44 seconds
Started Nov 22 12:27:02 PM PST 23
Finished Nov 22 12:27:11 PM PST 23
Peak memory 193664 kb
Host smart-d42b6572-c1b3-4cf3-9e89-d8f8c70f6d4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576896438778823867797233212844518963463614795883131733003019678381487537272 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.28576896438778823867797233212844518963463614795883131733003019678381487537272
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.111071262006466219638084025805524441860717076970461145536299780710801548558979
Short name T141
Test name
Test status
Simulation time 115064323 ps
CPU time 1.35 seconds
Started Nov 22 12:26:05 PM PST 23
Finished Nov 22 12:26:08 PM PST 23
Peak memory 195152 kb
Host smart-ffa8548a-8237-4e11-a1b6-8e38f4c869a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=111071262006466219638084025805524441860717076970461145536299780710801548558979 -assert nopostproc +UVM_TESTNAME=gpi
o_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/
null -cm_name 10.gpio_smoke_en_cdc_prim.111071262006466219638084025805524441860717076970461145536299780710801548558979
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.111829729136922848502581595063974930299002429085744869020620921095107825596544
Short name T147
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 194908 kb
Host smart-8125aab5-e8ae-4a98-acca-eb75a4468dab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111829729136922848502581595063974930299002429085744869020620921095107825596544 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11182972913692284850258159506397493029900242908574486902062092109
5107825596544
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.48189362433861526812516684411114620636929637420602184773779204769869902712506
Short name T125
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 194892 kb
Host smart-1248936a-d8fe-4ca0-a247-cf93a98e5cf5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=48189362433861526812516684411114620636929637420602184773779204769869902712506 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 11.gpio_smoke_en_cdc_prim.48189362433861526812516684411114620636929637420602184773779204769869902712506
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.111946144282049545790302661452490935228920982759371517640740743965341667750605
Short name T67
Test name
Test status
Simulation time 115064323 ps
CPU time 1.35 seconds
Started Nov 22 12:26:42 PM PST 23
Finished Nov 22 12:26:45 PM PST 23
Peak memory 195152 kb
Host smart-fc4482f2-c62d-4096-9476-90f30047f8fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111946144282049545790302661452490935228920982759371517640740743965341667750605 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11194614428204954579030266145249093522892098275937151764074074396
5341667750605
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.10528190448335153827589882601662997988167081052689705223389360424013021536396
Short name T199
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 194872 kb
Host smart-0205579c-5fb1-4097-b4b1-9708dcd2702d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=10528190448335153827589882601662997988167081052689705223389360424013021536396 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 12.gpio_smoke_en_cdc_prim.10528190448335153827589882601662997988167081052689705223389360424013021536396
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66795919829540313276326757625301863475534447203948884140521334056745860159542
Short name T128
Test name
Test status
Simulation time 115064323 ps
CPU time 1.48 seconds
Started Nov 22 12:25:34 PM PST 23
Finished Nov 22 12:25:42 PM PST 23
Peak memory 195236 kb
Host smart-8522b1e0-0f22-44ac-81e9-281c3fbf7565
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66795919829540313276326757625301863475534447203948884140521334056745860159542 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66795919829540313276326757625301863475534447203948884140521334056745860159542
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.19131383409785407691387667165415429892838827734060172821429053334476434514344
Short name T177
Test name
Test status
Simulation time 115064323 ps
CPU time 1.29 seconds
Started Nov 22 12:25:32 PM PST 23
Finished Nov 22 12:25:35 PM PST 23
Peak memory 195128 kb
Host smart-00dbaae1-1d54-4eca-9071-c9afc7e211bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=19131383409785407691387667165415429892838827734060172821429053334476434514344 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 13.gpio_smoke_en_cdc_prim.19131383409785407691387667165415429892838827734060172821429053334476434514344
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.112557036471744425441089729109790901300721848390110056374902418965246730527503
Short name T143
Test name
Test status
Simulation time 115064323 ps
CPU time 1.29 seconds
Started Nov 22 12:27:23 PM PST 23
Finished Nov 22 12:27:33 PM PST 23
Peak memory 194332 kb
Host smart-50282896-c14c-437b-994d-d79ae340b5d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112557036471744425441089729109790901300721848390110056374902418965246730527503 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11255703647174442544108972910979090130072184839011005637490241896
5246730527503
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.25725763834004676428726342357334290195872965688472870648637151758073626019276
Short name T171
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 194836 kb
Host smart-2cff25c0-bf69-4112-964c-b2c5ef701299
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=25725763834004676428726342357334290195872965688472870648637151758073626019276 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 14.gpio_smoke_en_cdc_prim.25725763834004676428726342357334290195872965688472870648637151758073626019276
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11788738335411294026929876061086524161621037557238107803066025222930429116921
Short name T172
Test name
Test status
Simulation time 115064323 ps
CPU time 1.34 seconds
Started Nov 22 12:27:48 PM PST 23
Finished Nov 22 12:27:55 PM PST 23
Peak memory 193700 kb
Host smart-c586c0cd-0ac9-4028-acc9-e5c3f9ffb945
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788738335411294026929876061086524161621037557238107803066025222930429116921 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11788738335411294026929876061086524161621037557238107803066025222930429116921
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.103535361579984203187559736901516320979364040381508593765454627691936102247555
Short name T153
Test name
Test status
Simulation time 115064323 ps
CPU time 1.32 seconds
Started Nov 22 12:25:36 PM PST 23
Finished Nov 22 12:25:43 PM PST 23
Peak memory 195192 kb
Host smart-e684be3e-12ab-48f6-9280-55474344d1e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=103535361579984203187559736901516320979364040381508593765454627691936102247555 -assert nopostproc +UVM_TESTNAME=gpi
o_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/
null -cm_name 15.gpio_smoke_en_cdc_prim.103535361579984203187559736901516320979364040381508593765454627691936102247555
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39269512041918091168000545813150125879307804317136292732874949973227586932794
Short name T173
Test name
Test status
Simulation time 115064323 ps
CPU time 1.59 seconds
Started Nov 22 12:27:48 PM PST 23
Finished Nov 22 12:27:55 PM PST 23
Peak memory 193064 kb
Host smart-25cf5f33-39c6-4243-9456-c4236ae88d63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269512041918091168000545813150125879307804317136292732874949973227586932794 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39269512041918091168000545813150125879307804317136292732874949973227586932794
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.60068415182010982655042822739856625497914230568021539235389867268218432701079
Short name T68
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:27:22 PM PST 23
Finished Nov 22 12:27:29 PM PST 23
Peak memory 195072 kb
Host smart-0a4e30b4-e43b-4c75-8827-37d1c76a5ae8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=60068415182010982655042822739856625497914230568021539235389867268218432701079 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 16.gpio_smoke_en_cdc_prim.60068415182010982655042822739856625497914230568021539235389867268218432701079
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.111657867076290725305859836505583653007772514090797124220674169885649353856145
Short name T174
Test name
Test status
Simulation time 115064323 ps
CPU time 1.35 seconds
Started Nov 22 12:28:02 PM PST 23
Finished Nov 22 12:28:04 PM PST 23
Peak memory 193348 kb
Host smart-e911df5b-e4f1-4d5c-9026-05974ba0f45f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111657867076290725305859836505583653007772514090797124220674169885649353856145 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11165786707629072530585983650558365300777251409079712422067416988
5649353856145
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.18687229915793967444333602594781452911176029997114936031193284652529671322703
Short name T66
Test name
Test status
Simulation time 115064323 ps
CPU time 1.23 seconds
Started Nov 22 12:27:37 PM PST 23
Finished Nov 22 12:27:48 PM PST 23
Peak memory 195160 kb
Host smart-414ff5c0-b3ce-4515-b454-a994410e7551
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=18687229915793967444333602594781452911176029997114936031193284652529671322703 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 17.gpio_smoke_en_cdc_prim.18687229915793967444333602594781452911176029997114936031193284652529671322703
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.63668621954992764401456333508091782043211950962394042771433910397358870945401
Short name T167
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:40 PM PST 23
Finished Nov 22 12:27:49 PM PST 23
Peak memory 195180 kb
Host smart-20781614-c70b-4e1f-baa3-d3dbf90f159a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63668621954992764401456333508091782043211950962394042771433910397358870945401 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.63668621954992764401456333508091782043211950962394042771433910397358870945401
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.59576126282301901697499352981931400650246023247473124147153099446369356768354
Short name T155
Test name
Test status
Simulation time 115064323 ps
CPU time 1.41 seconds
Started Nov 22 12:27:48 PM PST 23
Finished Nov 22 12:27:55 PM PST 23
Peak memory 192976 kb
Host smart-070605f9-be82-4618-8618-59df7144852b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=59576126282301901697499352981931400650246023247473124147153099446369356768354 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 18.gpio_smoke_en_cdc_prim.59576126282301901697499352981931400650246023247473124147153099446369356768354
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66807125852416590414866419832584542145825565952502716676015718305770484119479
Short name T114
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 194116 kb
Host smart-25d522e5-daf9-45ab-8fbd-211b127b560e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66807125852416590414866419832584542145825565952502716676015718305770484119479 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66807125852416590414866419832584542145825565952502716676015718305770484119479
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.52770744417231701059592541887080221803846505468844569878273352361661688738872
Short name T116
Test name
Test status
Simulation time 115064323 ps
CPU time 1.48 seconds
Started Nov 22 12:27:48 PM PST 23
Finished Nov 22 12:27:55 PM PST 23
Peak memory 193080 kb
Host smart-f2a7b26b-b615-4262-a561-725e3f353006
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=52770744417231701059592541887080221803846505468844569878273352361661688738872 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 19.gpio_smoke_en_cdc_prim.52770744417231701059592541887080221803846505468844569878273352361661688738872
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61382127099505657496925256939804854235637224455838802435219961999691531728108
Short name T120
Test name
Test status
Simulation time 115064323 ps
CPU time 1.35 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:27:22 PM PST 23
Peak memory 194900 kb
Host smart-56b9b856-e6c9-43af-b7e1-9f9de26e6e6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61382127099505657496925256939804854235637224455838802435219961999691531728108 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61382127099505657496925256939804854235637224455838802435219961999691531728108
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.93284589791624113338904995515535799166258541496539156866563385474488282351197
Short name T115
Test name
Test status
Simulation time 115064323 ps
CPU time 1.24 seconds
Started Nov 22 12:28:00 PM PST 23
Finished Nov 22 12:28:02 PM PST 23
Peak memory 195168 kb
Host smart-3c1cbaf0-34f7-4a67-8da5-dd69021774b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=93284589791624113338904995515535799166258541496539156866563385474488282351197 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 2.gpio_smoke_en_cdc_prim.93284589791624113338904995515535799166258541496539156866563385474488282351197
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77045379634208050368742775914823240084747758319010889336246897978987727042367
Short name T194
Test name
Test status
Simulation time 115064323 ps
CPU time 1.19 seconds
Started Nov 22 12:27:10 PM PST 23
Finished Nov 22 12:27:18 PM PST 23
Peak memory 195264 kb
Host smart-3b6196d5-cc2e-4cbe-9544-83b4d5aa6bdf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77045379634208050368742775914823240084747758319010889336246897978987727042367 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77045379634208050368742775914823240084747758319010889336246897978987727042367
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.114776458192577068845243781666490470573097661591530921393786888987694960089376
Short name T198
Test name
Test status
Simulation time 115064323 ps
CPU time 1.19 seconds
Started Nov 22 12:27:36 PM PST 23
Finished Nov 22 12:27:47 PM PST 23
Peak memory 195196 kb
Host smart-eda13f54-6539-446e-892d-4c15c00a10b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=114776458192577068845243781666490470573097661591530921393786888987694960089376 -assert nopostproc +UVM_TESTNAME=gpi
o_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/
null -cm_name 20.gpio_smoke_en_cdc_prim.114776458192577068845243781666490470573097661591530921393786888987694960089376
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3455448141445756907106019183185758664449580005589358525319666193152673343070
Short name T127
Test name
Test status
Simulation time 115064323 ps
CPU time 1.24 seconds
Started Nov 22 12:27:08 PM PST 23
Finished Nov 22 12:27:17 PM PST 23
Peak memory 195176 kb
Host smart-571ee4e5-d14b-493d-a48d-dd99611be942
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455448141445756907106019183185758664449580005589358525319666193152673343070 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pri
ms.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3455448141445756907106019183185758664449580005589358525319666193152673343070
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.55569558542282055190150387631317634561997699189986726219489571960173894901592
Short name T113
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 194916 kb
Host smart-15810151-f837-4443-aaeb-16cb0ece9f43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=55569558542282055190150387631317634561997699189986726219489571960173894901592 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 21.gpio_smoke_en_cdc_prim.55569558542282055190150387631317634561997699189986726219489571960173894901592
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.44180181285344472398786368964828837089972896899345051641548851262567278102173
Short name T112
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:27:16 PM PST 23
Finished Nov 22 12:27:24 PM PST 23
Peak memory 194936 kb
Host smart-92ddecef-b140-4ef6-810d-32ba82ebab05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44180181285344472398786368964828837089972896899345051641548851262567278102173 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.44180181285344472398786368964828837089972896899345051641548851262567278102173
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.88866080981114661356412517619003456131545419037480956592104044969537294746441
Short name T176
Test name
Test status
Simulation time 115064323 ps
CPU time 1.2 seconds
Started Nov 22 12:27:36 PM PST 23
Finished Nov 22 12:27:46 PM PST 23
Peak memory 195196 kb
Host smart-98f08ca4-26bf-4437-84cc-8a9a8f1c3c56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=88866080981114661356412517619003456131545419037480956592104044969537294746441 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 22.gpio_smoke_en_cdc_prim.88866080981114661356412517619003456131545419037480956592104044969537294746441
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76986821615284478844326604452419394857898570436886075675723941240562356416323
Short name T71
Test name
Test status
Simulation time 115064323 ps
CPU time 1.34 seconds
Started Nov 22 12:26:51 PM PST 23
Finished Nov 22 12:26:55 PM PST 23
Peak memory 195152 kb
Host smart-561257e4-1892-4efb-b65f-265935b1980f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76986821615284478844326604452419394857898570436886075675723941240562356416323 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76986821615284478844326604452419394857898570436886075675723941240562356416323
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.26893421143989741853326141743818237261129534913873398253203855336471229856210
Short name T134
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:27:15 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 194908 kb
Host smart-2c54f1a3-b9b0-45ef-8bd3-610580fb1e95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=26893421143989741853326141743818237261129534913873398253203855336471229856210 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 23.gpio_smoke_en_cdc_prim.26893421143989741853326141743818237261129534913873398253203855336471229856210
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.62150049426857350454405212513935297868151149969713880406068220796736748778961
Short name T156
Test name
Test status
Simulation time 115064323 ps
CPU time 1.34 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 193404 kb
Host smart-041ca0f0-ee55-4f05-9243-8101ac5dbf34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62150049426857350454405212513935297868151149969713880406068220796736748778961 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.62150049426857350454405212513935297868151149969713880406068220796736748778961
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.67599167696458544201475173808051521198397347313885969661482252120065508834725
Short name T169
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:27:13 PM PST 23
Finished Nov 22 12:27:22 PM PST 23
Peak memory 194372 kb
Host smart-56852a58-4615-43df-bb11-70c72e2538dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=67599167696458544201475173808051521198397347313885969661482252120065508834725 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 24.gpio_smoke_en_cdc_prim.67599167696458544201475173808051521198397347313885969661482252120065508834725
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49704020295258095169234805090239644249094152367059446027263053160118922517426
Short name T196
Test name
Test status
Simulation time 115064323 ps
CPU time 1.23 seconds
Started Nov 22 12:27:29 PM PST 23
Finished Nov 22 12:27:41 PM PST 23
Peak memory 195180 kb
Host smart-8793d9f6-f223-4d1f-b0c0-c21c5ff62059
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49704020295258095169234805090239644249094152367059446027263053160118922517426 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49704020295258095169234805090239644249094152367059446027263053160118922517426
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.93539509005983253931646402106154038685444872623966479449472649690891423496454
Short name T179
Test name
Test status
Simulation time 115064323 ps
CPU time 1.3 seconds
Started Nov 22 12:27:09 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 193820 kb
Host smart-9a49d414-0634-4534-808c-92c155779183
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=93539509005983253931646402106154038685444872623966479449472649690891423496454 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 25.gpio_smoke_en_cdc_prim.93539509005983253931646402106154038685444872623966479449472649690891423496454
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.57784729075696639969359292625091694059400418969035384394887279090428340959638
Short name T181
Test name
Test status
Simulation time 115064323 ps
CPU time 1.23 seconds
Started Nov 22 12:27:15 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 194892 kb
Host smart-7fa49251-7242-40d3-b6c2-23524a1b407d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57784729075696639969359292625091694059400418969035384394887279090428340959638 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.57784729075696639969359292625091694059400418969035384394887279090428340959638
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.38952946056941289900560637997172439909286942584306209438390442694790543062926
Short name T195
Test name
Test status
Simulation time 115064323 ps
CPU time 1.29 seconds
Started Nov 22 12:28:03 PM PST 23
Finished Nov 22 12:28:05 PM PST 23
Peak memory 194824 kb
Host smart-bbb9a914-4dc6-45cf-a514-74e721c88a81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=38952946056941289900560637997172439909286942584306209438390442694790543062926 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 26.gpio_smoke_en_cdc_prim.38952946056941289900560637997172439909286942584306209438390442694790543062926
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.99732006318490491243894238209493107796272398273428249927844500456414633258356
Short name T170
Test name
Test status
Simulation time 115064323 ps
CPU time 1.24 seconds
Started Nov 22 12:27:11 PM PST 23
Finished Nov 22 12:27:19 PM PST 23
Peak memory 194952 kb
Host smart-0f816b11-01ac-4625-8282-12f871b8187a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99732006318490491243894238209493107796272398273428249927844500456414633258356 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.99732006318490491243894238209493107796272398273428249927844500456414633258356
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.32660431192087066813083082450503924863659426918974861585502256946108342753610
Short name T140
Test name
Test status
Simulation time 115064323 ps
CPU time 1.29 seconds
Started Nov 22 12:25:50 PM PST 23
Finished Nov 22 12:25:53 PM PST 23
Peak memory 195160 kb
Host smart-29a2b78b-a1b5-4d9c-bb90-d73c2f9f1621
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=32660431192087066813083082450503924863659426918974861585502256946108342753610 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 27.gpio_smoke_en_cdc_prim.32660431192087066813083082450503924863659426918974861585502256946108342753610
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66220061441031061308637028149752644835912389955342112127090767328471337461351
Short name T191
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:27:27 PM PST 23
Finished Nov 22 12:27:38 PM PST 23
Peak memory 194908 kb
Host smart-ee257f3f-1f9a-4867-98cb-e6c3acec8d4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66220061441031061308637028149752644835912389955342112127090767328471337461351 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66220061441031061308637028149752644835912389955342112127090767328471337461351
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.94144653722857257683345309576344474382998447596153700285291923715647637599802
Short name T136
Test name
Test status
Simulation time 115064323 ps
CPU time 1.21 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 194912 kb
Host smart-7cca38d2-5a01-417c-9c23-4375c77c4ac1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=94144653722857257683345309576344474382998447596153700285291923715647637599802 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 28.gpio_smoke_en_cdc_prim.94144653722857257683345309576344474382998447596153700285291923715647637599802
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113400581983008766792265208108267966479938057278919903424752458809420418429638
Short name T123
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:27:47 PM PST 23
Finished Nov 22 12:27:54 PM PST 23
Peak memory 194904 kb
Host smart-88229841-2613-44b5-9fd6-757019198afc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113400581983008766792265208108267966479938057278919903424752458809420418429638 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11340058198300876679226520810826796647993805727891990342475245880
9420418429638
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.67984813251976567703481749108091228315328798103368660433124393800842198263612
Short name T129
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:27:12 PM PST 23
Finished Nov 22 12:27:20 PM PST 23
Peak memory 194912 kb
Host smart-c17611cc-e945-400c-b3cd-9b9b20d5a44a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=67984813251976567703481749108091228315328798103368660433124393800842198263612 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 29.gpio_smoke_en_cdc_prim.67984813251976567703481749108091228315328798103368660433124393800842198263612
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.12312516688683389027933954340584411905954966540890100060126864608623674613008
Short name T189
Test name
Test status
Simulation time 115064323 ps
CPU time 1.2 seconds
Started Nov 22 12:27:45 PM PST 23
Finished Nov 22 12:27:52 PM PST 23
Peak memory 194808 kb
Host smart-c3cbf200-40e8-4f0c-b1b4-a94e38a03618
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312516688683389027933954340584411905954966540890100060126864608623674613008 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.12312516688683389027933954340584411905954966540890100060126864608623674613008
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.10078650235322209348601011359460610284267375061933253386508430709907092060025
Short name T13
Test name
Test status
Simulation time 115064323 ps
CPU time 1.31 seconds
Started Nov 22 12:26:23 PM PST 23
Finished Nov 22 12:26:30 PM PST 23
Peak memory 195172 kb
Host smart-1819abfc-04f4-4087-b29d-83b6a5e30a79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=10078650235322209348601011359460610284267375061933253386508430709907092060025 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 3.gpio_smoke_en_cdc_prim.10078650235322209348601011359460610284267375061933253386508430709907092060025
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31417585270116789765795891907848945228436342456972884856231405424475791336750
Short name T184
Test name
Test status
Simulation time 115064323 ps
CPU time 1.4 seconds
Started Nov 22 12:28:02 PM PST 23
Finished Nov 22 12:28:04 PM PST 23
Peak memory 193480 kb
Host smart-b6844585-ea63-43d3-a854-2a22789c2f10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417585270116789765795891907848945228436342456972884856231405424475791336750 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31417585270116789765795891907848945228436342456972884856231405424475791336750
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.67224833959963583453054262637728775355705017789924699475922887029869218964647
Short name T146
Test name
Test status
Simulation time 115064323 ps
CPU time 1.32 seconds
Started Nov 22 12:27:26 PM PST 23
Finished Nov 22 12:27:38 PM PST 23
Peak memory 194892 kb
Host smart-a085436b-d9f2-46ab-a636-f9860f8a6f45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=67224833959963583453054262637728775355705017789924699475922887029869218964647 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 30.gpio_smoke_en_cdc_prim.67224833959963583453054262637728775355705017789924699475922887029869218964647
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110477399428911152563463583610253766186651235741410951129929995344579958959334
Short name T14
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:27:26 PM PST 23
Finished Nov 22 12:27:37 PM PST 23
Peak memory 194884 kb
Host smart-43c15708-ef68-4eae-9896-237a1f28afeb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110477399428911152563463583610253766186651235741410951129929995344579958959334 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11047739942891115256346358361025376618665123574141095112992999534
4579958959334
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.37843189872053262882004507314036643922510166192746878876362329345446641317404
Short name T159
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:26 PM PST 23
Finished Nov 22 12:27:36 PM PST 23
Peak memory 194880 kb
Host smart-b5a04a58-a556-45ac-8b1c-ecff3459bdbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=37843189872053262882004507314036643922510166192746878876362329345446641317404 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 31.gpio_smoke_en_cdc_prim.37843189872053262882004507314036643922510166192746878876362329345446641317404
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110401571507479107009390833975396305032746744918509694793687766623807219598297
Short name T163
Test name
Test status
Simulation time 115064323 ps
CPU time 1.35 seconds
Started Nov 22 12:25:52 PM PST 23
Finished Nov 22 12:25:54 PM PST 23
Peak memory 195232 kb
Host smart-016e1aa8-d29b-4678-8dc8-af5b9d7ef4c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110401571507479107009390833975396305032746744918509694793687766623807219598297 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11040157150747910700939083397539630503274674491850969479368776662
3807219598297
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2136220857731044436200439072092090939076387271277467460586610377111796904252
Short name T126
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:14 PM PST 23
Finished Nov 22 12:27:23 PM PST 23
Peak memory 194948 kb
Host smart-1d249048-924a-4c73-9338-ae3b985513c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2136220857731044436200439072092090939076387271277467460586610377111796904252 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/nu
ll -cm_name 32.gpio_smoke_en_cdc_prim.2136220857731044436200439072092090939076387271277467460586610377111796904252
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.96910481460897705073052147247263574113230097014794455672729870423110231254837
Short name T145
Test name
Test status
Simulation time 115064323 ps
CPU time 1.22 seconds
Started Nov 22 12:27:27 PM PST 23
Finished Nov 22 12:27:39 PM PST 23
Peak memory 194908 kb
Host smart-e95e737b-4429-4cd6-9a37-2c72d82bf2a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96910481460897705073052147247263574113230097014794455672729870423110231254837 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.96910481460897705073052147247263574113230097014794455672729870423110231254837
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.27065545372037544931469123194232358285838050481729113068739758309099573698962
Short name T201
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:27:26 PM PST 23
Finished Nov 22 12:27:36 PM PST 23
Peak memory 194472 kb
Host smart-6d3523c6-6fd4-4e33-9533-39c5e3aa0fb0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=27065545372037544931469123194232358285838050481729113068739758309099573698962 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 33.gpio_smoke_en_cdc_prim.27065545372037544931469123194232358285838050481729113068739758309099573698962
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.25100464186522117396421834211459449173916871350838504292475405913518763714309
Short name T166
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:27:07 PM PST 23
Finished Nov 22 12:27:16 PM PST 23
Peak memory 194372 kb
Host smart-89902290-2781-4c8c-9ac2-1af653e10557
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100464186522117396421834211459449173916871350838504292475405913518763714309 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.25100464186522117396421834211459449173916871350838504292475405913518763714309
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.96289087089557333827070627304397049431007306491867306041633042195814591718015
Short name T188
Test name
Test status
Simulation time 115064323 ps
CPU time 1.24 seconds
Started Nov 22 12:29:16 PM PST 23
Finished Nov 22 12:29:18 PM PST 23
Peak memory 195196 kb
Host smart-a211a799-f125-41e6-91f8-eda34c8b1425
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=96289087089557333827070627304397049431007306491867306041633042195814591718015 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 34.gpio_smoke_en_cdc_prim.96289087089557333827070627304397049431007306491867306041633042195814591718015
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.56002027785112117176981892195164556723858894600324875674155341448745002766049
Short name T132
Test name
Test status
Simulation time 115064323 ps
CPU time 1.43 seconds
Started Nov 22 12:29:06 PM PST 23
Finished Nov 22 12:29:09 PM PST 23
Peak memory 195156 kb
Host smart-2e307a5d-d891-407d-9c79-91f5ceff3eff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56002027785112117176981892195164556723858894600324875674155341448745002766049 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.56002027785112117176981892195164556723858894600324875674155341448745002766049
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.99627757038488108362305509838788247359061062460093927670602973681965773147217
Short name T142
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:29:07 PM PST 23
Finished Nov 22 12:29:09 PM PST 23
Peak memory 195172 kb
Host smart-6808ebb9-b4a4-4dfc-8e09-9bff3d2299e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=99627757038488108362305509838788247359061062460093927670602973681965773147217 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 35.gpio_smoke_en_cdc_prim.99627757038488108362305509838788247359061062460093927670602973681965773147217
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77317265927808531031890995808327777939601942893533849387000761152656384939968
Short name T178
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:06 PM PST 23
Finished Nov 22 12:29:09 PM PST 23
Peak memory 195156 kb
Host smart-5b82a599-bedd-436b-b01c-7a2d11f38b36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77317265927808531031890995808327777939601942893533849387000761152656384939968 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77317265927808531031890995808327777939601942893533849387000761152656384939968
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.48612700406945414247958105508791091130655093338059013753498161319594066515350
Short name T122
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:15 PM PST 23
Finished Nov 22 12:29:17 PM PST 23
Peak memory 195196 kb
Host smart-e11d568c-93a5-4e80-a005-1c56e19ccf02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=48612700406945414247958105508791091130655093338059013753498161319594066515350 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 36.gpio_smoke_en_cdc_prim.48612700406945414247958105508791091130655093338059013753498161319594066515350
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.82266109650871065752950795996416871185923919371128193543721776609772229499115
Short name T139
Test name
Test status
Simulation time 115064323 ps
CPU time 1.42 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:11 PM PST 23
Peak memory 195216 kb
Host smart-e1a2e17d-2ff1-46be-add4-5b9716b77461
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82266109650871065752950795996416871185923919371128193543721776609772229499115 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.82266109650871065752950795996416871185923919371128193543721776609772229499115
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.35126333432318414687155341088013005362099396626784349466663180568107994295611
Short name T148
Test name
Test status
Simulation time 115064323 ps
CPU time 1.29 seconds
Started Nov 22 12:29:10 PM PST 23
Finished Nov 22 12:29:13 PM PST 23
Peak memory 195196 kb
Host smart-5a5be808-f89f-40d7-b416-a263d13cd005
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=35126333432318414687155341088013005362099396626784349466663180568107994295611 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 37.gpio_smoke_en_cdc_prim.35126333432318414687155341088013005362099396626784349466663180568107994295611
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77876534644115135448434005335450382942279979452776903367485427617910763852696
Short name T149
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:11 PM PST 23
Peak memory 195216 kb
Host smart-773f87d8-22bc-486d-ba19-32f438530bd3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77876534644115135448434005335450382942279979452776903367485427617910763852696 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77876534644115135448434005335450382942279979452776903367485427617910763852696
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.37465740443301080780652994004392226767597523363653846322505469192965650248822
Short name T133
Test name
Test status
Simulation time 115064323 ps
CPU time 1.35 seconds
Started Nov 22 12:29:05 PM PST 23
Finished Nov 22 12:29:07 PM PST 23
Peak memory 195140 kb
Host smart-37e3dc52-02e1-42d9-95dc-9f94263143af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=37465740443301080780652994004392226767597523363653846322505469192965650248822 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 38.gpio_smoke_en_cdc_prim.37465740443301080780652994004392226767597523363653846322505469192965650248822
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23776084754114873661193079537998984381998369743734331265005885021412427362974
Short name T186
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:03 PM PST 23
Finished Nov 22 12:29:05 PM PST 23
Peak memory 195124 kb
Host smart-be321320-7f99-4e10-90da-de292a9ce90f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776084754114873661193079537998984381998369743734331265005885021412427362974 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23776084754114873661193079537998984381998369743734331265005885021412427362974
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.21474859113450687147433238471643200326576310120851093247946131968134388663134
Short name T164
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:28:59 PM PST 23
Finished Nov 22 12:29:01 PM PST 23
Peak memory 195148 kb
Host smart-90ce9cd0-7787-4105-a71a-421c5f485210
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=21474859113450687147433238471643200326576310120851093247946131968134388663134 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 39.gpio_smoke_en_cdc_prim.21474859113450687147433238471643200326576310120851093247946131968134388663134
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76573319147037828548876698149775186715683073958829855143896252180917768020301
Short name T135
Test name
Test status
Simulation time 115064323 ps
CPU time 1.3 seconds
Started Nov 22 12:29:19 PM PST 23
Finished Nov 22 12:29:22 PM PST 23
Peak memory 195124 kb
Host smart-94a16513-d39d-4929-ba3c-a2889d932815
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76573319147037828548876698149775186715683073958829855143896252180917768020301 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76573319147037828548876698149775186715683073958829855143896252180917768020301
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.96897901511442945045712813220258133084946370756905727566538688884105807850906
Short name T175
Test name
Test status
Simulation time 115064323 ps
CPU time 1.36 seconds
Started Nov 22 12:27:04 PM PST 23
Finished Nov 22 12:27:12 PM PST 23
Peak memory 194808 kb
Host smart-6fb051ad-186d-4141-843e-2596a59bf71e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=96897901511442945045712813220258133084946370756905727566538688884105807850906 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 4.gpio_smoke_en_cdc_prim.96897901511442945045712813220258133084946370756905727566538688884105807850906
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.103308790443693246290016622106341112167317650274352051852618697351642850654857
Short name T200
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:26:17 PM PST 23
Finished Nov 22 12:26:22 PM PST 23
Peak memory 195156 kb
Host smart-b3b1b126-baba-4ff2-b9a7-fbbe51886717
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103308790443693246290016622106341112167317650274352051852618697351642850654857 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.103308790443693246290016622106341112167317650274352051852618697351642850654857
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.35080530986950786037917597680641468107272699606963976307008321485213169201516
Short name T117
Test name
Test status
Simulation time 115064323 ps
CPU time 1.33 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:11 PM PST 23
Peak memory 195232 kb
Host smart-043ab7b4-bd5f-4406-8b62-20ba0c2f6dc2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=35080530986950786037917597680641468107272699606963976307008321485213169201516 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 40.gpio_smoke_en_cdc_prim.35080530986950786037917597680641468107272699606963976307008321485213169201516
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.15348451019452599210046149227313184622121533673977563024919476926629621883760
Short name T131
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:29:18 PM PST 23
Finished Nov 22 12:29:21 PM PST 23
Peak memory 195124 kb
Host smart-e449b284-9532-4588-bbe7-d452352da455
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15348451019452599210046149227313184622121533673977563024919476926629621883760 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.15348451019452599210046149227313184622121533673977563024919476926629621883760
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.93926516524022674863850525618427383963359427645214545455714366330343956632611
Short name T160
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:20 PM PST 23
Finished Nov 22 12:29:23 PM PST 23
Peak memory 195140 kb
Host smart-279bab41-c113-416a-8e7c-2dc30b80715f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=93926516524022674863850525618427383963359427645214545455714366330343956632611 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 41.gpio_smoke_en_cdc_prim.93926516524022674863850525618427383963359427645214545455714366330343956632611
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.70833173510333925416945819892115032187290084025402308927389976002415900680962
Short name T193
Test name
Test status
Simulation time 115064323 ps
CPU time 1.29 seconds
Started Nov 22 12:29:09 PM PST 23
Finished Nov 22 12:29:12 PM PST 23
Peak memory 195080 kb
Host smart-2f8c9ab3-7618-4069-8db5-4018c1a9b75a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70833173510333925416945819892115032187290084025402308927389976002415900680962 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.70833173510333925416945819892115032187290084025402308927389976002415900680962
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.98044779077477744375055495561057326725580582338026030065242631920653231791124
Short name T144
Test name
Test status
Simulation time 115064323 ps
CPU time 1.31 seconds
Started Nov 22 12:29:17 PM PST 23
Finished Nov 22 12:29:19 PM PST 23
Peak memory 195140 kb
Host smart-83c8b756-7ab0-4c57-96ef-4d694cf71f92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=98044779077477744375055495561057326725580582338026030065242631920653231791124 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 42.gpio_smoke_en_cdc_prim.98044779077477744375055495561057326725580582338026030065242631920653231791124
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.102870601148113362352297342516557028276211201933202815661748652050072016156369
Short name T168
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:12 PM PST 23
Peak memory 195212 kb
Host smart-be1e1ea5-b5ab-4af9-875b-e9d4532fbe20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102870601148113362352297342516557028276211201933202815661748652050072016156369 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.10287060114811336235229734251655702827621120193320281566174865205
0072016156369
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.102536134302850357238866622029842509012719033840101248409245496398810206123241
Short name T154
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:17 PM PST 23
Finished Nov 22 12:29:19 PM PST 23
Peak memory 195140 kb
Host smart-691fa2eb-6d9c-40e8-a757-e0df54c83c0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=102536134302850357238866622029842509012719033840101248409245496398810206123241 -assert nopostproc +UVM_TESTNAME=gpi
o_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/
null -cm_name 43.gpio_smoke_en_cdc_prim.102536134302850357238866622029842509012719033840101248409245496398810206123241
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2213725662778438776139377957644810001887889910746726298956007599970735654199
Short name T65
Test name
Test status
Simulation time 115064323 ps
CPU time 1.28 seconds
Started Nov 22 12:29:09 PM PST 23
Finished Nov 22 12:29:12 PM PST 23
Peak memory 195236 kb
Host smart-42a430af-d85f-409f-8a64-3a21d0074e4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213725662778438776139377957644810001887889910746726298956007599970735654199 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pri
ms.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2213725662778438776139377957644810001887889910746726298956007599970735654199
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.27472523367829072223581478883592592350245805265588027819608455402502996584136
Short name T124
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:10 PM PST 23
Peak memory 195232 kb
Host smart-64f0b3f8-6f8d-4277-a93f-393c181c0380
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=27472523367829072223581478883592592350245805265588027819608455402502996584136 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 44.gpio_smoke_en_cdc_prim.27472523367829072223581478883592592350245805265588027819608455402502996584136
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.80566688256824861362145910219673342255249340636549055809675324407080852621804
Short name T157
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:29:18 PM PST 23
Finished Nov 22 12:29:21 PM PST 23
Peak memory 195124 kb
Host smart-e52cc6ad-b27a-4307-98de-008057d4fd9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80566688256824861362145910219673342255249340636549055809675324407080852621804 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.80566688256824861362145910219673342255249340636549055809675324407080852621804
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.66354447543126903480321739868844411101577245634568070497785390799255428158169
Short name T150
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 195144 kb
Host smart-a88469ee-36df-44d9-92d3-9d6f91d84c39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=66354447543126903480321739868844411101577245634568070497785390799255428158169 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 45.gpio_smoke_en_cdc_prim.66354447543126903480321739868844411101577245634568070497785390799255428158169
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.75937283350499411163017820099392222324795759163014306087757881316787522887003
Short name T162
Test name
Test status
Simulation time 115064323 ps
CPU time 1.25 seconds
Started Nov 22 12:29:07 PM PST 23
Finished Nov 22 12:29:10 PM PST 23
Peak memory 195216 kb
Host smart-d559fa0c-7fab-43aa-b25c-3423e22ff1c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75937283350499411163017820099392222324795759163014306087757881316787522887003 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.75937283350499411163017820099392222324795759163014306087757881316787522887003
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.99080898258143356717629552745588653875726725833749469581131476596603101531810
Short name T180
Test name
Test status
Simulation time 115064323 ps
CPU time 1.36 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:11 PM PST 23
Peak memory 195232 kb
Host smart-973148ad-7159-4bc7-995c-ce87f6dc526c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=99080898258143356717629552745588653875726725833749469581131476596603101531810 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 46.gpio_smoke_en_cdc_prim.99080898258143356717629552745588653875726725833749469581131476596603101531810
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.104917686885200901526524448774097153454400369462617621934476680959652032603895
Short name T118
Test name
Test status
Simulation time 115064323 ps
CPU time 1.23 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 195128 kb
Host smart-de2558bd-71b3-483b-b418-6b1f278b1fc7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104917686885200901526524448774097153454400369462617621934476680959652032603895 -assert nopost
proc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_p
rims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.10491768688520090152652444877409715345440036946261762193447668095
9652032603895
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.99195623668892556001565201430696673607785396309671274963141995654313332401390
Short name T121
Test name
Test status
Simulation time 115064323 ps
CPU time 1.31 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:28 PM PST 23
Peak memory 195152 kb
Host smart-727adfee-cf80-4215-8f18-56b1abd0ebd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=99195623668892556001565201430696673607785396309671274963141995654313332401390 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 47.gpio_smoke_en_cdc_prim.99195623668892556001565201430696673607785396309671274963141995654313332401390
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6723593359988452875413069675878449510700245988055498107312284531514134771790
Short name T137
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:29:09 PM PST 23
Finished Nov 22 12:29:12 PM PST 23
Peak memory 195128 kb
Host smart-802c7bf8-cdb6-4f98-8a30-d891cd8e8ed4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6723593359988452875413069675878449510700245988055498107312284531514134771790 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pri
ms.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6723593359988452875413069675878449510700245988055498107312284531514134771790
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.77856866866096983627463856262650299293730994536272549882821563315757350619538
Short name T15
Test name
Test status
Simulation time 115064323 ps
CPU time 1.31 seconds
Started Nov 22 12:29:24 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 194852 kb
Host smart-3d5b59f5-52ff-4d8c-ba56-9ca582708d53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=77856866866096983627463856262650299293730994536272549882821563315757350619538 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 48.gpio_smoke_en_cdc_prim.77856866866096983627463856262650299293730994536272549882821563315757350619538
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98507773594656226594630572816361489153936948991797454396555364790889463632307
Short name T158
Test name
Test status
Simulation time 115064323 ps
CPU time 1.33 seconds
Started Nov 22 12:29:08 PM PST 23
Finished Nov 22 12:29:12 PM PST 23
Peak memory 195216 kb
Host smart-daa9b0dc-c8ca-4d6b-b424-411792e8bdc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98507773594656226594630572816361489153936948991797454396555364790889463632307 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98507773594656226594630572816361489153936948991797454396555364790889463632307
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.33716423472906744397665717958553985516784824385238397604521992020556739814292
Short name T165
Test name
Test status
Simulation time 115064323 ps
CPU time 1.3 seconds
Started Nov 22 12:29:23 PM PST 23
Finished Nov 22 12:29:27 PM PST 23
Peak memory 194904 kb
Host smart-dac134ff-5bd6-49f4-bd81-38c4cc35918a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=33716423472906744397665717958553985516784824385238397604521992020556739814292 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 49.gpio_smoke_en_cdc_prim.33716423472906744397665717958553985516784824385238397604521992020556739814292
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.50472339443177699549467409901001062906217478205598641144332405658096889597403
Short name T190
Test name
Test status
Simulation time 115064323 ps
CPU time 1.36 seconds
Started Nov 22 12:29:17 PM PST 23
Finished Nov 22 12:29:19 PM PST 23
Peak memory 195172 kb
Host smart-2d851f26-fd08-413e-aab9-a2e8ad93d561
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50472339443177699549467409901001062906217478205598641144332405658096889597403 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.50472339443177699549467409901001062906217478205598641144332405658096889597403
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.113606728666936025986421783956216346608802001336275946798998589259610136981392
Short name T185
Test name
Test status
Simulation time 115064323 ps
CPU time 1.26 seconds
Started Nov 22 12:26:35 PM PST 23
Finished Nov 22 12:26:37 PM PST 23
Peak memory 195196 kb
Host smart-d56c4b49-1162-4a24-8ac7-09e25b85b077
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=113606728666936025986421783956216346608802001336275946798998589259610136981392 -assert nopostproc +UVM_TESTNAME=gpi
o_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/
null -cm_name 5.gpio_smoke_en_cdc_prim.113606728666936025986421783956216346608802001336275946798998589259610136981392
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.34628110930370388754241928577604355962786399808254254618734174848092276468273
Short name T183
Test name
Test status
Simulation time 115064323 ps
CPU time 1.27 seconds
Started Nov 22 12:26:18 PM PST 23
Finished Nov 22 12:26:24 PM PST 23
Peak memory 195176 kb
Host smart-728af5ca-0ae1-4cad-ab81-a0bbfefb8b82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34628110930370388754241928577604355962786399808254254618734174848092276468273 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.34628110930370388754241928577604355962786399808254254618734174848092276468273
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.65671493293808344090186519952820655126527341521511015552251167378378383093817
Short name T119
Test name
Test status
Simulation time 115064323 ps
CPU time 1.39 seconds
Started Nov 22 12:26:13 PM PST 23
Finished Nov 22 12:26:16 PM PST 23
Peak memory 195148 kb
Host smart-c65a0970-169b-48e5-b304-e32c7a0ea1b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=65671493293808344090186519952820655126527341521511015552251167378378383093817 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 6.gpio_smoke_en_cdc_prim.65671493293808344090186519952820655126527341521511015552251167378378383093817
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.82791639760082885654420731094162574986215608653703371312293495099857863421208
Short name T187
Test name
Test status
Simulation time 115064323 ps
CPU time 1.32 seconds
Started Nov 22 12:27:35 PM PST 23
Finished Nov 22 12:27:46 PM PST 23
Peak memory 194332 kb
Host smart-4e9bdfe2-2176-4477-b4e6-737951aed570
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82791639760082885654420731094162574986215608653703371312293495099857863421208 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.82791639760082885654420731094162574986215608653703371312293495099857863421208
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.12928538368590395499440720291727100685710842592308867721579550010427229370246
Short name T151
Test name
Test status
Simulation time 115064323 ps
CPU time 1.4 seconds
Started Nov 22 12:25:52 PM PST 23
Finished Nov 22 12:25:55 PM PST 23
Peak memory 195124 kb
Host smart-2a5807be-8339-4ccf-8b81-603aaf0fd4c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=12928538368590395499440720291727100685710842592308867721579550010427229370246 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 7.gpio_smoke_en_cdc_prim.12928538368590395499440720291727100685710842592308867721579550010427229370246
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.18019284664002616222478300872834536558460777406842840720198550874309087689744
Short name T152
Test name
Test status
Simulation time 115064323 ps
CPU time 1.3 seconds
Started Nov 22 12:27:41 PM PST 23
Finished Nov 22 12:27:50 PM PST 23
Peak memory 194936 kb
Host smart-2e9b2438-9fde-4888-8528-ed90ffc323a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18019284664002616222478300872834536558460777406842840720198550874309087689744 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.18019284664002616222478300872834536558460777406842840720198550874309087689744
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2133050590412512389526118991396919999290977632270022741640340988252797815785
Short name T197
Test name
Test status
Simulation time 115064323 ps
CPU time 1.23 seconds
Started Nov 22 12:26:53 PM PST 23
Finished Nov 22 12:26:58 PM PST 23
Peak memory 195172 kb
Host smart-d58c4b9b-1c01-4833-a1f3-34ada484ffad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2133050590412512389526118991396919999290977632270022741640340988252797815785 -assert nopostproc +UVM_TESTNAME=gpio_
base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_smoke_en_cdc_prim.2133050590412512389526118991396919999290977632270022741640340988252797815785
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.90129454442401822241124542702320174556364379773770603716762737871969549475760
Short name T161
Test name
Test status
Simulation time 115064323 ps
CPU time 1.23 seconds
Started Nov 22 12:27:38 PM PST 23
Finished Nov 22 12:27:49 PM PST 23
Peak memory 194936 kb
Host smart-8db14280-0f5a-4d34-a341-f23fa9396263
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90129454442401822241124542702320174556364379773770603716762737871969549475760 -assert nopostp
roc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pr
ims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.90129454442401822241124542702320174556364379773770603716762737871969549475760
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.13637669170176562112097849998181921251024010368436459106493698211950040900201
Short name T182
Test name
Test status
Simulation time 115064323 ps
CPU time 1.21 seconds
Started Nov 22 12:26:16 PM PST 23
Finished Nov 22 12:26:21 PM PST 23
Peak memory 194820 kb
Host smart-6d5aa513-6909-4fcb-b57d-8a63cca3f914
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=13637669170176562112097849998181921251024010368436459106493698211950040900201 -assert nopostproc +UVM_TESTNAME=gpio
_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/n
ull -cm_name 9.gpio_smoke_en_cdc_prim.13637669170176562112097849998181921251024010368436459106493698211950040900201
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.7974932602508391442028320759526385888148622043697032306588918259747839088311
Short name T192
Test name
Test status
Simulation time 115064323 ps
CPU time 1.49 seconds
Started Nov 22 12:27:02 PM PST 23
Finished Nov 22 12:27:11 PM PST 23
Peak memory 193668 kb
Host smart-289a327e-6966-4c6b-a724-76f8a581a5a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7974932602508391442028320759526385888148622043697032306588918259747839088311 -assert nopostpr
oc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_pri
ms.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.7974932602508391442028320759526385888148622043697032306588918259747839088311
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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