Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5325249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24788380

1

T22

1584

T23

46

T24

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11766680	1			T22	1154		T23	29		T24	20
values[0x0]	9001469	1			T22	589		T23	16		T24	9
values[0x1]	9345480	1			T22	562		T23	13		T24	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4069868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26043761

1

T22

1714

T23

48

T24

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	114365	1			T22	19		T25	8		T12	5
valid_sources[0x01]	114894	1			T22	7		T26	1		T11	1
valid_sources[0x02]	117322	1			T23	1		T26	3		T12	2
valid_sources[0x03]	114174	1			T22	2		T25	27		T26	1
valid_sources[0x04]	114454	1			T22	2		T11	1		T12	4
valid_sources[0x05]	114376	1			T26	1		T11	2		T12	3
valid_sources[0x06]	118142	1			T22	7		T24	3		T26	2
valid_sources[0x07]	118181	1			T22	1		T25	3		T12	2
valid_sources[0x08]	116100	1			T22	12		T26	1		T12	1
valid_sources[0x09]	112540	1			T26	1		T11	1		T12	4
valid_sources[0x0a]	114514	1			T26	1		T11	3		T12	3
valid_sources[0x0b]	114537	1			T22	13		T11	1		T12	3
valid_sources[0x0c]	116924	1			T22	3		T26	1		T11	2
valid_sources[0x0d]	115879	1			T22	1		T26	1		T11	5
valid_sources[0x0e]	117535	1			T22	14		T25	15		T26	1
valid_sources[0x0f]	115522	1			T22	6		T23	1		T12	5
valid_sources[0x10]	191014	1			T22	3		T25	3		T11	1
valid_sources[0x11]	116408	1			T22	15		T23	1		T11	1
valid_sources[0x12]	117483	1			T22	6		T1	1		T11	3
valid_sources[0x13]	113045	1			T22	24		T11	1		T14	4
valid_sources[0x14]	115595	1			T22	10		T25	12		T2	128
valid_sources[0x15]	114470	1			T22	19		T11	1		T12	1
valid_sources[0x16]	113248	1			T22	3		T26	2		T11	2
valid_sources[0x17]	114307	1			T24	1		T26	2		T11	1
valid_sources[0x18]	116165	1			T26	4		T11	2		T12	2
valid_sources[0x19]	119584	1			T22	5		T26	3		T12	2
valid_sources[0x1a]	116362	1			T26	1		T11	2		T12	3
valid_sources[0x1b]	115098	1			T22	12		T26	2		T11	2
valid_sources[0x1c]	115953	1			T22	6		T23	1		T25	18
valid_sources[0x1d]	114633	1			T22	7		T24	3		T25	20
valid_sources[0x1e]	117542	1			T22	3		T26	2		T11	5
valid_sources[0x1f]	115940	1			T23	2		T26	2		T11	1
valid_sources[0x20]	116540	1			T22	10		T11	5		T12	2
valid_sources[0x21]	117187	1			T22	3		T26	2		T12	1
valid_sources[0x22]	118892	1			T22	11		T23	1		T26	2
valid_sources[0x23]	115211	1			T22	3		T11	1		T12	3
valid_sources[0x24]	128087	1			T26	3		T11	1		T12	1
valid_sources[0x25]	113319	1			T22	23		T23	1		T26	1
valid_sources[0x26]	118638	1			T22	14		T11	1		T12	5
valid_sources[0x27]	117086	1			T22	4		T23	2		T24	1
valid_sources[0x28]	115144	1			T22	5		T11	6		T14	1
valid_sources[0x29]	113127	1			T22	14		T26	3		T11	4
valid_sources[0x2a]	112343	1			T22	10		T24	2		T26	1
valid_sources[0x2b]	110807	1			T22	6		T23	1		T26	1
valid_sources[0x2c]	118149	1			T22	10		T23	1		T26	2
valid_sources[0x2d]	109350	1			T22	1		T23	1		T25	4
valid_sources[0x2e]	113375	1			T22	8		T26	1		T11	1
valid_sources[0x2f]	111455	1			T24	1		T27	1		T12	1
valid_sources[0x30]	114901	1			T22	30		T26	2		T1	1
valid_sources[0x31]	112859	1			T22	8		T11	4		T12	1
valid_sources[0x32]	119563	1			T22	12		T26	2		T12	3
valid_sources[0x33]	114516	1			T22	11		T26	2		T12	3
valid_sources[0x34]	113570	1			T22	1		T23	1		T26	1
valid_sources[0x35]	113613	1			T22	14		T26	1		T11	1
valid_sources[0x36]	115321	1			T22	1		T23	1		T12	7
valid_sources[0x37]	114948	1			T22	6		T11	3		T12	5
valid_sources[0x38]	118339	1			T22	9		T26	1		T11	2
valid_sources[0x39]	112700	1			T22	14		T12	2		T5	4
valid_sources[0x3a]	113710	1			T22	4		T23	1		T25	7
valid_sources[0x3b]	113315	1			T22	11		T26	2		T11	5
valid_sources[0x3c]	119238	1			T22	6		T12	7		T14	5
valid_sources[0x3d]	121319	1			T22	13		T12	2		T3	4
valid_sources[0x3e]	112437	1			T22	1		T12	3		T16	2
valid_sources[0x3f]	112527	1			T22	9		T12	5		T14	5
valid_sources[0x40]	114189	1			T26	1		T11	4		T12	3
valid_sources[0x41]	111226	1			T22	20		T23	1		T26	2
valid_sources[0x42]	119367	1			T22	15		T26	2		T12	1
valid_sources[0x43]	112487	1			T22	25		T23	1		T26	2
valid_sources[0x44]	113481	1			T22	4		T26	1		T11	3
valid_sources[0x45]	115799	1			T22	4		T23	1		T25	20
valid_sources[0x46]	115051	1			T22	7		T24	1		T1	4
valid_sources[0x47]	112998	1			T22	5		T24	1		T25	9
valid_sources[0x48]	117628	1			T22	8		T26	2		T12	2
valid_sources[0x49]	116505	1			T22	5		T23	1		T26	2
valid_sources[0x4a]	115956	1			T22	3		T25	21		T11	1
valid_sources[0x4b]	117797	1			T22	16		T26	4		T12	7
valid_sources[0x4c]	114426	1			T22	3		T25	6		T26	3
valid_sources[0x4d]	114940	1			T22	7		T24	2		T26	2
valid_sources[0x4e]	122106	1			T22	12		T2	128		T14	2
valid_sources[0x4f]	116545	1			T22	18		T26	1		T11	2
valid_sources[0x50]	114485	1			T22	3		T26	1		T11	2
valid_sources[0x51]	112726	1			T22	14		T11	1		T12	1
valid_sources[0x52]	110728	1			T22	2		T24	2		T26	1
valid_sources[0x53]	116169	1			T22	25		T25	20		T26	3
valid_sources[0x54]	116935	1			T22	7		T26	1		T3	7
valid_sources[0x55]	115408	1			T22	9		T26	2		T11	1
valid_sources[0x56]	116900	1			T22	11		T23	1		T26	1
valid_sources[0x57]	114498	1			T22	11		T23	1		T26	1
valid_sources[0x58]	117473	1			T22	13		T26	1		T11	3
valid_sources[0x59]	117708	1			T22	8		T25	20		T26	1
valid_sources[0x5a]	113588	1			T22	23		T26	1		T11	2
valid_sources[0x5b]	117337	1			T22	4		T26	1		T11	1
valid_sources[0x5c]	174643	1			T22	6		T23	2		T26	2
valid_sources[0x5d]	115674	1			T22	9		T26	1		T12	4
valid_sources[0x5e]	117912	1			T22	11		T24	1		T11	1
valid_sources[0x5f]	113191	1			T22	10		T26	1		T11	5
valid_sources[0x60]	115571	1			T22	4		T26	1		T11	5
valid_sources[0x61]	117010	1			T22	15		T26	2		T12	2
valid_sources[0x62]	114805	1			T22	3		T26	2		T11	1
valid_sources[0x63]	114857	1			T22	5		T23	2		T11	1
valid_sources[0x64]	120005	1			T22	9		T24	1		T26	1
valid_sources[0x65]	122617	1			T22	10		T26	1		T11	3
valid_sources[0x66]	120040	1			T22	16		T11	1		T12	2
valid_sources[0x67]	112009	1			T22	15		T11	1		T12	1
valid_sources[0x68]	110599	1			T22	7		T25	4		T26	1
valid_sources[0x69]	114217	1			T22	15		T26	2		T11	1
valid_sources[0x6a]	113234	1			T22	10		T11	2		T12	4
valid_sources[0x6b]	113583	1			T22	8		T23	1		T25	24
valid_sources[0x6c]	115545	1			T22	18		T23	1		T24	1
valid_sources[0x6d]	115981	1			T22	17		T24	1		T25	20
valid_sources[0x6e]	115863	1			T22	27		T12	1		T41	2
valid_sources[0x6f]	117679	1			T22	6		T26	1		T11	1
valid_sources[0x70]	116242	1			T22	11		T11	2		T13	7
valid_sources[0x71]	112575	1			T22	4		T23	1		T25	20
valid_sources[0x72]	111171	1			T22	2		T25	20		T11	1
valid_sources[0x73]	114050	1			T22	13		T26	1		T11	2
valid_sources[0x74]	199779	1			T22	4		T26	1		T11	4
valid_sources[0x75]	114286	1			T22	10		T23	1		T26	1
valid_sources[0x76]	111390	1			T22	7		T24	1		T26	1
valid_sources[0x77]	114176	1			T22	2		T26	1		T27	11
valid_sources[0x78]	115555	1			T22	3		T11	2		T12	1
valid_sources[0x79]	114989	1			T22	1		T25	1		T26	2
valid_sources[0x7a]	114518	1			T22	4		T11	2		T14	3
valid_sources[0x7b]	116328	1			T22	4		T26	1		T11	1
valid_sources[0x7c]	118709	1			T22	15		T26	4		T11	4
valid_sources[0x7d]	117107	1			T22	12		T23	1		T26	1
valid_sources[0x7e]	112109	1			T23	1		T11	1		T12	5
valid_sources[0x7f]	112538	1			T22	11		T26	1		T11	2
valid_sources[0x80]	115789	1			T22	7		T26	3		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6853077

1

T22

529

T23

17

T24

6

values[0x0]

all_enables

biggest_size

8966959

1

T22

548

T23

16

T24

9

values[0x1]

all_enables

biggest_size

8968344

1

T22

507

T23

13

T24

11