Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	307403165	0	0	0
ctrl_en_input_filter_rd_A	307403165	473438	0	0
intr_ctrl_en_falling_rd_A	307403165	506571	0	0
intr_ctrl_en_lvlhigh_rd_A	307403165	475490	0	0
intr_ctrl_en_lvllow_rd_A	307403165	503806	0	0
intr_ctrl_en_rising_rd_A	307403165	474441	0	0
intr_enable_rd_A	307403165	476884	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	473438	0	0
T1	1378	9	0	0
T2	37616	727	0	0
T3	11327	89	0	0
T4	0	16	0	0
T5	0	72	0	0
T6	0	5	0	0
T7	0	18	0	0
T8	0	48	0	0
T9	0	11	0	0
T10	0	6	0	0
T11	1767	0	0	0
T12	8187	0	0	0
T13	1910	0	0	0
T14	5902	0	0	0
T15	1631	0	0	0
T16	3097	0	0	0
T17	2920	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	506571	0	0
T1	1378	3	0	0
T2	37616	684	0	0
T3	11327	62	0	0
T4	0	10	0	0
T5	0	23	0	0
T6	0	9	0	0
T7	0	5	0	0
T8	0	37	0	0
T9	0	14	0	0
T10	0	5	0	0
T11	1767	0	0	0
T12	8187	0	0	0
T13	1910	0	0	0
T14	5902	0	0	0
T15	1631	0	0	0
T16	3097	0	0	0
T17	2920	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	475490	0	0
T1	1378	1	0	0
T2	37616	690	0	0
T3	11327	66	0	0
T4	0	8	0	0
T5	0	35	0	0
T6	0	8	0	0
T7	0	26	0	0
T8	0	19	0	0
T9	0	18	0	0
T10	0	9	0	0
T11	1767	0	0	0
T12	8187	0	0	0
T13	1910	0	0	0
T14	5902	0	0	0
T15	1631	0	0	0
T16	3097	0	0	0
T17	2920	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	503806	0	0
T1	1378	3	0	0
T2	37616	595	0	0
T3	11327	78	0	0
T4	0	19	0	0
T5	0	94	0	0
T6	0	5	0	0
T7	0	8	0	0
T8	0	16	0	0
T9	0	8	0	0
T10	0	11	0	0
T11	1767	0	0	0
T12	8187	0	0	0
T13	1910	0	0	0
T14	5902	0	0	0
T15	1631	0	0	0
T16	3097	0	0	0
T17	2920	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	474441	0	0
T1	1378	3	0	0
T2	37616	698	0	0
T3	11327	101	0	0
T4	0	9	0	0
T5	0	53	0	0
T6	0	1	0	0
T7	0	20	0	0
T8	0	11	0	0
T9	0	13	0	0
T10	0	6	0	0
T11	1767	0	0	0
T12	8187	0	0	0
T13	1910	0	0	0
T14	5902	0	0	0
T15	1631	0	0	0
T16	3097	0	0	0
T17	2920	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307403165	476884	0	0
T1	1378	4	0	0
T2	37616	630	0	0
T3	11327	75	0	0
T4	0	10	0	0
T5	0	49	0	0
T7	0	19	0	0
T11	1767	0	0	0
T12	8187	0	0	0
T13	1910	0	0	0
T14	5902	0	0	0
T15	1631	0	0	0
T16	3097	0	0	0
T17	2920	0	0	0
T18	0	29	0	0
T19	0	30	0	0
T20	0	12	0	0
T21	0	17	0	0