Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6110481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28935888

1

T21

407

T22

34

T1

359

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13574082	1			T21	108		T22	20		T1	171
values[0x0]	10523666	1			T21	147		T22	12		T1	106
values[0x1]	10948621	1			T21	159		T22	8		T1	82

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4655181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30391188

1

T21

411

T22

34

T1

359

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	143465	1			T21	2		T1	3		T2	1
valid_sources[0x01]	137260	1			T1	6		T76	1		T5	1
valid_sources[0x02]	129531	1			T2	2		T23	1		T37	2
valid_sources[0x03]	139741	1			T12	1		T15	5		T23	1
valid_sources[0x04]	132783	1			T2	1		T14	3		T23	2
valid_sources[0x05]	132760	1			T1	2		T12	3		T14	2
valid_sources[0x06]	135385	1			T21	8		T1	5		T11	20
valid_sources[0x07]	228762	1			T12	3		T23	2		T76	1
valid_sources[0x08]	129883	1			T21	3		T1	2		T14	2
valid_sources[0x09]	141181	1			T12	2		T14	1		T23	5
valid_sources[0x0a]	129619	1			T2	1		T14	3		T23	2
valid_sources[0x0b]	129720	1			T11	20		T14	1		T23	3
valid_sources[0x0c]	130189	1			T1	4		T14	1		T23	1
valid_sources[0x0d]	219020	1			T1	5		T2	3		T23	2
valid_sources[0x0e]	148528	1			T21	8		T12	5		T23	1
valid_sources[0x0f]	128602	1			T21	6		T1	1		T2	3
valid_sources[0x10]	124213	1			T1	4		T12	8		T14	1
valid_sources[0x11]	125055	1			T1	5		T14	3		T23	3
valid_sources[0x12]	136074	1			T21	10		T1	2		T12	1
valid_sources[0x13]	134119	1			T22	40		T23	2		T27	2
valid_sources[0x14]	130954	1			T1	1		T2	6		T17	1
valid_sources[0x15]	127894	1			T12	2		T14	1		T23	6
valid_sources[0x16]	130436	1			T1	3		T14	4		T18	1
valid_sources[0x17]	134709	1			T2	3		T14	2		T23	2
valid_sources[0x18]	134677	1			T14	3		T23	1		T27	2
valid_sources[0x19]	137302	1			T1	5		T12	1		T2	1
valid_sources[0x1a]	132979	1			T2	1		T23	2		T27	2
valid_sources[0x1b]	128110	1			T12	3		T14	10		T3	1
valid_sources[0x1c]	124026	1			T21	2		T12	1		T2	7
valid_sources[0x1d]	131132	1			T1	1		T2	1		T14	1
valid_sources[0x1e]	129400	1			T23	3		T28	5		T30	3
valid_sources[0x1f]	131025	1			T2	5		T14	2		T3	1
valid_sources[0x20]	132304	1			T2	3		T14	1		T23	3
valid_sources[0x21]	133643	1			T2	2		T14	16		T23	2
valid_sources[0x22]	134091	1			T21	7		T1	2		T14	2
valid_sources[0x23]	135742	1			T2	1		T23	3		T28	1
valid_sources[0x24]	138961	1			T21	1		T1	1		T14	3
valid_sources[0x25]	133641	1			T1	2		T2	4		T14	1
valid_sources[0x26]	132683	1			T2	1		T23	4		T28	2
valid_sources[0x27]	132844	1			T21	2		T1	4		T12	1
valid_sources[0x28]	128135	1			T1	1		T11	10		T12	4
valid_sources[0x29]	120008	1			T21	35		T2	3		T14	2
valid_sources[0x2a]	127032	1			T12	3		T2	1		T30	5
valid_sources[0x2b]	133214	1			T14	2		T23	1		T100	1
valid_sources[0x2c]	140355	1			T21	8		T1	5		T2	3
valid_sources[0x2d]	135509	1			T12	3		T2	6		T3	1
valid_sources[0x2e]	134379	1			T1	2		T12	1		T14	6
valid_sources[0x2f]	135312	1			T14	3		T3	1		T23	2
valid_sources[0x30]	134118	1			T1	1		T2	1		T14	4
valid_sources[0x31]	133239	1			T1	1		T27	1		T76	1
valid_sources[0x32]	129093	1			T1	1		T12	1		T14	1
valid_sources[0x33]	131796	1			T12	1		T2	6		T14	3
valid_sources[0x34]	130479	1			T1	4		T12	6		T14	4
valid_sources[0x35]	135014	1			T1	1		T12	2		T2	1
valid_sources[0x36]	133245	1			T21	3		T17	1		T23	2
valid_sources[0x37]	125295	1			T12	2		T23	1		T28	4
valid_sources[0x38]	244667	1			T21	2		T12	1		T14	8
valid_sources[0x39]	129994	1			T2	2		T27	1		T28	6
valid_sources[0x3a]	131494	1			T21	1		T2	10		T14	2
valid_sources[0x3b]	129218	1			T1	2		T2	4		T14	11
valid_sources[0x3c]	129975	1			T21	4		T2	3		T23	1
valid_sources[0x3d]	128348	1			T21	2		T1	1		T12	2
valid_sources[0x3e]	129488	1			T11	20		T23	5		T28	1
valid_sources[0x3f]	130392	1			T1	6		T12	1		T23	2
valid_sources[0x40]	133265	1			T1	2		T2	2		T15	3
valid_sources[0x41]	127307	1			T21	8		T1	1		T18	1
valid_sources[0x42]	133572	1			T2	6		T23	2		T27	2
valid_sources[0x43]	135328	1			T21	7		T1	1		T12	1
valid_sources[0x44]	138751	1			T1	1		T2	1		T14	2
valid_sources[0x45]	132053	1			T1	3		T12	5		T14	8
valid_sources[0x46]	129750	1			T1	1		T2	1		T14	3
valid_sources[0x47]	131840	1			T1	1		T12	2		T2	1
valid_sources[0x48]	135654	1			T1	1		T2	2		T3	1
valid_sources[0x49]	124209	1			T2	1		T14	4		T23	5
valid_sources[0x4a]	130994	1			T2	2		T23	1		T27	1
valid_sources[0x4b]	125855	1			T11	10		T12	5		T14	9
valid_sources[0x4c]	130328	1			T21	3		T1	3		T11	20
valid_sources[0x4d]	129289	1			T1	3		T12	1		T23	2
valid_sources[0x4e]	132180	1			T2	3		T14	3		T28	3
valid_sources[0x4f]	135807	1			T1	4		T11	20		T2	3
valid_sources[0x50]	130243	1			T1	8		T15	2		T23	5
valid_sources[0x51]	128071	1			T21	6		T11	20		T13	27
valid_sources[0x52]	137181	1			T1	1		T2	1		T14	9
valid_sources[0x53]	127534	1			T2	1		T23	5		T27	1
valid_sources[0x54]	136375	1			T1	6		T12	1		T2	1
valid_sources[0x55]	137234	1			T21	2		T12	2		T14	2
valid_sources[0x56]	134124	1			T21	7		T1	1		T12	1
valid_sources[0x57]	125572	1			T1	1		T12	5		T14	3
valid_sources[0x58]	130152	1			T1	2		T12	1		T14	2
valid_sources[0x59]	139148	1			T1	1		T2	2		T14	3
valid_sources[0x5a]	124521	1			T1	3		T2	6		T23	3
valid_sources[0x5b]	131643	1			T1	3		T12	1		T27	3
valid_sources[0x5c]	128275	1			T14	2		T23	5		T28	3
valid_sources[0x5d]	125871	1			T1	1		T14	2		T18	1
valid_sources[0x5e]	128801	1			T2	2		T14	1		T23	2
valid_sources[0x5f]	127979	1			T2	1		T14	4		T18	1
valid_sources[0x60]	137931	1			T1	3		T2	1		T14	8
valid_sources[0x61]	134899	1			T1	5		T2	1		T28	6
valid_sources[0x62]	128274	1			T17	4		T18	1		T23	1
valid_sources[0x63]	129335	1			T1	1		T14	6		T3	1
valid_sources[0x64]	132827	1			T1	1		T12	5		T3	1
valid_sources[0x65]	133631	1			T1	1		T23	2		T28	3
valid_sources[0x66]	129560	1			T21	1		T12	3		T2	1
valid_sources[0x67]	129698	1			T2	3		T3	1		T18	2
valid_sources[0x68]	132270	1			T1	5		T14	5		T23	1
valid_sources[0x69]	122709	1			T21	3		T1	2		T14	5
valid_sources[0x6a]	128267	1			T2	3		T14	2		T23	1
valid_sources[0x6b]	134208	1			T1	5		T14	6		T15	3
valid_sources[0x6c]	139865	1			T21	10		T1	1		T2	2
valid_sources[0x6d]	133686	1			T1	3		T14	4		T23	5
valid_sources[0x6e]	125408	1			T21	5		T1	1		T23	1
valid_sources[0x6f]	131401	1			T1	1		T12	1		T2	4
valid_sources[0x70]	254568	1			T12	1		T14	7		T16	23
valid_sources[0x71]	138824	1			T1	11		T2	3		T14	3
valid_sources[0x72]	135092	1			T1	5		T23	5		T27	1
valid_sources[0x73]	137333	1			T1	4		T14	10		T23	3
valid_sources[0x74]	129746	1			T1	2		T12	2		T2	4
valid_sources[0x75]	131409	1			T1	4		T14	1		T23	2
valid_sources[0x76]	142699	1			T21	7		T2	10		T14	1
valid_sources[0x77]	128890	1			T1	6		T12	1		T14	4
valid_sources[0x78]	126761	1			T13	137		T2	2		T14	1
valid_sources[0x79]	139141	1			T12	1		T2	1		T14	5
valid_sources[0x7a]	125994	1			T1	3		T12	2		T76	2
valid_sources[0x7b]	131338	1			T21	2		T1	1		T12	1
valid_sources[0x7c]	126527	1			T1	2		T12	1		T14	3
valid_sources[0x7d]	128178	1			T1	1		T2	1		T23	4
valid_sources[0x7e]	129680	1			T21	1		T1	2		T11	20
valid_sources[0x7f]	138963	1			T21	16		T1	2		T23	1
valid_sources[0x80]	134538	1			T2	2		T14	6		T23	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7971478

1

T21

101

T22

14

T1

171

values[0x0]

all_enables

biggest_size

10481441

1

T21

147

T22

12

T1

106

values[0x1]

all_enables

biggest_size

10482969

1

T21

159

T22

8

T1

82