Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	346930816	0	0	0
ctrl_en_input_filter_rd_A	346930816	353441	0	0
intr_ctrl_en_falling_rd_A	346930816	375778	0	0
intr_ctrl_en_lvlhigh_rd_A	346930816	351612	0	0
intr_ctrl_en_lvllow_rd_A	346930816	374763	0	0
intr_ctrl_en_rising_rd_A	346930816	352266	0	0
intr_enable_rd_A	346930816	353297	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	353441	0	0
T1	3835	108	0	0
T2	3994	67	0	0
T3	1457	8	0	0
T4	0	3	0	0
T5	0	10	0	0
T6	0	20	0	0
T7	0	60	0	0
T8	0	2	0	0
T9	0	103	0	0
T10	0	19	0	0
T11	7576	0	0	0
T12	4695	0	0	0
T13	13469	0	0	0
T14	2121	0	0	0
T15	717	0	0	0
T16	1296	0	0	0
T17	698	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	375778	0	0
T1	3835	75	0	0
T2	3994	90	0	0
T3	1457	1	0	0
T4	0	1	0	0
T5	0	12	0	0
T6	0	16	0	0
T7	0	85	0	0
T8	0	14	0	0
T9	0	118	0	0
T10	0	18	0	0
T11	7576	0	0	0
T12	4695	0	0	0
T13	13469	0	0	0
T14	2121	0	0	0
T15	717	0	0	0
T16	1296	0	0	0
T17	698	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	351612	0	0
T1	3835	89	0	0
T2	3994	79	0	0
T3	1457	2	0	0
T4	0	6	0	0
T5	0	11	0	0
T6	0	14	0	0
T7	0	75	0	0
T8	0	21	0	0
T9	0	135	0	0
T10	0	13	0	0
T11	7576	0	0	0
T12	4695	0	0	0
T13	13469	0	0	0
T14	2121	0	0	0
T15	717	0	0	0
T16	1296	0	0	0
T17	698	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	374763	0	0
T1	3835	42	0	0
T2	3994	54	0	0
T3	1457	7	0	0
T4	0	2	0	0
T5	0	14	0	0
T6	0	19	0	0
T7	0	70	0	0
T8	0	5	0	0
T9	0	133	0	0
T10	0	21	0	0
T11	7576	0	0	0
T12	4695	0	0	0
T13	13469	0	0	0
T14	2121	0	0	0
T15	717	0	0	0
T16	1296	0	0	0
T17	698	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	352266	0	0
T1	3835	155	0	0
T2	3994	92	0	0
T3	1457	3	0	0
T4	0	6	0	0
T5	0	14	0	0
T6	0	24	0	0
T7	0	56	0	0
T8	0	6	0	0
T9	0	100	0	0
T10	0	31	0	0
T11	7576	0	0	0
T12	4695	0	0	0
T13	13469	0	0	0
T14	2121	0	0	0
T15	717	0	0	0
T16	1296	0	0	0
T17	698	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346930816	353297	0	0
T1	3835	41	0	0
T2	3994	52	0	0
T3	1457	0	0	0
T4	0	2	0	0
T5	0	4	0	0
T6	0	21	0	0
T7	0	57	0	0
T11	7576	0	0	0
T12	4695	0	0	0
T13	13469	0	0	0
T14	2121	0	0	0
T15	717	0	0	0
T16	1296	26	0	0
T17	698	0	0	0
T18	0	45	0	0
T19	0	29	0	0
T20	0	18	0	0