Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5541274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26212772

1

T22

45

T23

52

T19

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12321424	1			T22	27		T23	98		T19	11
values[0x0]	9530657	1			T22	13		T23	7		T19	5
values[0x1]	9901965	1			T22	17		T23	3		T19	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4221570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27532476

1

T22

47

T23

64

T19

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	126203	1			T11	1		T13	1		T101	1
valid_sources[0x01]	234637	1			T11	2		T12	2		T13	2
valid_sources[0x02]	113069	1			T11	1		T30	2		T5	3
valid_sources[0x03]	120504	1			T16	1		T26	1		T30	1
valid_sources[0x04]	113840	1			T11	1		T17	128		T74	1
valid_sources[0x05]	120442	1			T11	1		T12	1		T15	1
valid_sources[0x06]	125258	1			T19	3		T13	3		T24	26
valid_sources[0x07]	117897	1			T11	1		T17	128		T4	1
valid_sources[0x08]	115102	1			T23	1		T1	1		T11	4
valid_sources[0x09]	116350	1			T1	2		T11	2		T12	3
valid_sources[0x0a]	117830	1			T12	1		T75	1		T26	2
valid_sources[0x0b]	125659	1			T21	20		T12	2		T30	4
valid_sources[0x0c]	117011	1			T23	1		T11	1		T75	1
valid_sources[0x0d]	116721	1			T12	1		T24	10		T76	2
valid_sources[0x0e]	111932	1			T12	2		T3	66		T16	1
valid_sources[0x0f]	118466	1			T25	1		T108	2		T109	1
valid_sources[0x10]	124640	1			T11	1		T26	1		T30	1
valid_sources[0x11]	115407	1			T22	1		T12	5		T16	2
valid_sources[0x12]	124954	1			T75	1		T4	1		T76	9
valid_sources[0x13]	123329	1			T23	4		T13	1		T16	3
valid_sources[0x14]	117566	1			T23	4		T11	1		T12	1
valid_sources[0x15]	122366	1			T22	2		T75	1		T30	1
valid_sources[0x16]	111906	1			T23	1		T1	1		T11	1
valid_sources[0x17]	128996	1			T23	1		T11	1		T17	128
valid_sources[0x18]	116585	1			T22	1		T11	1		T13	1
valid_sources[0x19]	126074	1			T22	2		T23	2		T15	1
valid_sources[0x1a]	117965	1			T22	1		T75	1		T4	1
valid_sources[0x1b]	121161	1			T22	1		T21	27		T1	2
valid_sources[0x1c]	117196	1			T22	1		T19	1		T12	1
valid_sources[0x1d]	113704	1			T1	1		T12	1		T2	5
valid_sources[0x1e]	121231	1			T23	2		T16	2		T25	2
valid_sources[0x1f]	114738	1			T12	4		T26	3		T30	1
valid_sources[0x20]	116068	1			T11	1		T12	1		T13	1
valid_sources[0x21]	117824	1			T11	1		T75	1		T26	2
valid_sources[0x22]	113060	1			T12	2		T4	1		T30	1
valid_sources[0x23]	119410	1			T11	1		T12	2		T16	1
valid_sources[0x24]	120854	1			T23	1		T11	4		T12	1
valid_sources[0x25]	113667	1			T22	1		T26	1		T30	1
valid_sources[0x26]	128686	1			T22	1		T26	2		T30	1
valid_sources[0x27]	116847	1			T12	3		T75	1		T26	2
valid_sources[0x28]	116108	1			T23	1		T11	2		T12	5
valid_sources[0x29]	111204	1			T23	2		T11	2		T12	4
valid_sources[0x2a]	122321	1			T22	1		T12	3		T24	20
valid_sources[0x2b]	125764	1			T22	1		T11	1		T12	3
valid_sources[0x2c]	119463	1			T23	1		T1	1		T11	1
valid_sources[0x2d]	117963	1			T23	2		T11	1		T12	1
valid_sources[0x2e]	120465	1			T12	3		T4	1		T30	2
valid_sources[0x2f]	155405	1			T23	1		T11	2		T75	1
valid_sources[0x30]	120027	1			T30	2		T25	3		T6	1
valid_sources[0x31]	119562	1			T11	1		T26	1		T30	3
valid_sources[0x32]	113102	1			T23	1		T11	1		T12	4
valid_sources[0x33]	122032	1			T21	20		T11	2		T24	5
valid_sources[0x34]	119866	1			T23	1		T11	2		T12	1
valid_sources[0x35]	115971	1			T11	1		T12	3		T76	1
valid_sources[0x36]	115349	1			T12	1		T26	1		T30	2
valid_sources[0x37]	117732	1			T1	1		T12	2		T13	1
valid_sources[0x38]	122180	1			T22	1		T26	1		T30	4
valid_sources[0x39]	112991	1			T23	3		T12	2		T16	3
valid_sources[0x3a]	120092	1			T22	1		T11	1		T75	1
valid_sources[0x3b]	120433	1			T12	1		T75	1		T76	1
valid_sources[0x3c]	195553	1			T12	2		T24	7		T26	1
valid_sources[0x3d]	112384	1			T22	1		T23	1		T12	1
valid_sources[0x3e]	110581	1			T12	1		T4	1		T76	1
valid_sources[0x3f]	121567	1			T21	4		T12	4		T14	58
valid_sources[0x40]	129883	1			T1	1		T12	4		T17	128
valid_sources[0x41]	123051	1			T13	1		T17	131		T75	2
valid_sources[0x42]	115557	1			T22	1		T21	5		T12	1
valid_sources[0x43]	115546	1			T22	1		T11	1		T12	2
valid_sources[0x44]	113607	1			T11	1		T26	2		T30	1
valid_sources[0x45]	147845	1			T22	1		T76	1		T30	2
valid_sources[0x46]	118739	1			T13	2		T2	1		T75	1
valid_sources[0x47]	225427	1			T12	2		T75	2		T26	1
valid_sources[0x48]	121248	1			T23	1		T11	2		T17	128
valid_sources[0x49]	115882	1			T23	2		T12	7		T30	2
valid_sources[0x4a]	122859	1			T12	3		T4	1		T26	2
valid_sources[0x4b]	120214	1			T2	3		T74	3		T76	1
valid_sources[0x4c]	119802	1			T11	3		T26	1		T30	2
valid_sources[0x4d]	227747	1			T13	2		T4	3		T26	1
valid_sources[0x4e]	123456	1			T22	1		T11	1		T13	1
valid_sources[0x4f]	177613	1			T22	2		T23	3		T11	2
valid_sources[0x50]	126433	1			T19	5		T12	1		T75	1
valid_sources[0x51]	115162	1			T1	1		T11	2		T12	2
valid_sources[0x52]	114633	1			T11	1		T15	1		T26	2
valid_sources[0x53]	112680	1			T12	5		T75	1		T26	1
valid_sources[0x54]	115439	1			T22	1		T11	2		T12	1
valid_sources[0x55]	174938	1			T22	1		T1	1		T24	20
valid_sources[0x56]	116928	1			T17	128		T25	1		T8	5
valid_sources[0x57]	114498	1			T23	3		T11	1		T12	3
valid_sources[0x58]	114850	1			T23	1		T12	3		T30	3
valid_sources[0x59]	129077	1			T1	2		T15	2		T17	256
valid_sources[0x5a]	115823	1			T1	2		T11	2		T12	1
valid_sources[0x5b]	121673	1			T11	1		T74	3		T26	1
valid_sources[0x5c]	124846	1			T11	1		T12	3		T3	12
valid_sources[0x5d]	119086	1			T11	2		T13	1		T24	20
valid_sources[0x5e]	110397	1			T75	1		T26	2		T25	1
valid_sources[0x5f]	120715	1			T12	2		T75	3		T26	1
valid_sources[0x60]	113275	1			T11	1		T12	2		T2	3
valid_sources[0x61]	115482	1			T12	1		T13	1		T75	1
valid_sources[0x62]	115747	1			T12	3		T75	1		T26	3
valid_sources[0x63]	121538	1			T22	1		T11	3		T12	2
valid_sources[0x64]	119681	1			T11	3		T26	1		T30	2
valid_sources[0x65]	125612	1			T30	3		T109	1		T8	12
valid_sources[0x66]	120484	1			T75	2		T76	3		T26	2
valid_sources[0x67]	118770	1			T11	4		T12	3		T30	1
valid_sources[0x68]	117541	1			T12	1		T76	5		T30	3
valid_sources[0x69]	132195	1			T23	1		T21	20		T12	1
valid_sources[0x6a]	118633	1			T23	1		T12	1		T13	3
valid_sources[0x6b]	118881	1			T11	3		T12	1		T24	19
valid_sources[0x6c]	128865	1			T22	1		T11	2		T12	1
valid_sources[0x6d]	120614	1			T12	2		T4	1		T26	1
valid_sources[0x6e]	112379	1			T11	4		T12	2		T75	1
valid_sources[0x6f]	270944	1			T12	3		T76	1		T26	1
valid_sources[0x70]	118129	1			T1	2		T11	2		T75	1
valid_sources[0x71]	119951	1			T22	2		T1	1		T11	1
valid_sources[0x72]	126171	1			T23	3		T19	8		T11	3
valid_sources[0x73]	122450	1			T12	1		T4	1		T30	1
valid_sources[0x74]	120686	1			T1	1		T12	2		T4	2
valid_sources[0x75]	114148	1			T1	1		T11	1		T12	1
valid_sources[0x76]	119413	1			T12	2		T26	3		T30	4
valid_sources[0x77]	202421	1			T22	1		T11	1		T12	6
valid_sources[0x78]	133675	1			T23	2		T11	1		T12	1
valid_sources[0x79]	135640	1			T26	2		T30	2		T25	1
valid_sources[0x7a]	121033	1			T76	1		T30	2		T99	1
valid_sources[0x7b]	117138	1			T11	1		T4	6		T26	1
valid_sources[0x7c]	117926	1			T11	1		T16	3		T26	1
valid_sources[0x7d]	120805	1			T11	2		T12	1		T3	7
valid_sources[0x7e]	123632	1			T23	1		T11	1		T12	1
valid_sources[0x7f]	120027	1			T12	1		T75	1		T26	6
valid_sources[0x80]	110429	1			T12	2		T26	3		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7233328

1

T22

18

T23

42

T19

5

values[0x0]

all_enables

biggest_size

9493234

1

T22

12

T23

7

T19

5

values[0x1]

all_enables

biggest_size

9486210

1

T22

15

T23

3

T19

6