Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	321974969	0	0	0
ctrl_en_input_filter_rd_A	321974969	357533	0	0
intr_ctrl_en_falling_rd_A	321974969	377871	0	0
intr_ctrl_en_lvlhigh_rd_A	321974969	354860	0	0
intr_ctrl_en_lvllow_rd_A	321974969	377831	0	0
intr_ctrl_en_rising_rd_A	321974969	352676	0	0
intr_enable_rd_A	321974969	354875	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	357533	0	0
T1	1225	10	0	0
T2	1898	9	0	0
T3	2230	6	0	0
T4	0	20	0	0
T5	0	16	0	0
T6	0	21	0	0
T7	0	58	0	0
T8	0	428	0	0
T9	0	1	0	0
T10	0	54	0	0
T11	1097	0	0	0
T12	2904	0	0	0
T13	1361	0	0	0
T14	1208	0	0	0
T15	863	0	0	0
T16	1572	0	0	0
T17	5521	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	377871	0	0
T1	1225	9	0	0
T2	1898	20	0	0
T3	2230	8	0	0
T4	0	9	0	0
T5	0	37	0	0
T6	0	9	0	0
T7	0	51	0	0
T8	0	436	0	0
T9	0	12	0	0
T11	1097	0	0	0
T12	2904	0	0	0
T13	1361	0	0	0
T14	1208	0	0	0
T15	863	6	0	0
T16	1572	0	0	0
T17	5521	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	354860	0	0
T1	1225	2	0	0
T2	1898	26	0	0
T3	2230	11	0	0
T4	0	7	0	0
T5	0	16	0	0
T6	0	23	0	0
T7	0	69	0	0
T8	0	438	0	0
T9	0	8	0	0
T11	1097	0	0	0
T12	2904	0	0	0
T13	1361	0	0	0
T14	1208	0	0	0
T15	863	6	0	0
T16	1572	0	0	0
T17	5521	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	377831	0	0
T1	1225	1	0	0
T2	1898	28	0	0
T3	2230	9	0	0
T4	0	22	0	0
T5	0	28	0	0
T6	0	18	0	0
T7	0	32	0	0
T8	0	488	0	0
T9	0	9	0	0
T11	1097	0	0	0
T12	2904	0	0	0
T13	1361	0	0	0
T14	1208	0	0	0
T15	863	5	0	0
T16	1572	0	0	0
T17	5521	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	352676	0	0
T1	1225	8	0	0
T2	1898	16	0	0
T3	2230	16	0	0
T4	0	8	0	0
T5	0	12	0	0
T6	0	12	0	0
T7	0	48	0	0
T8	0	414	0	0
T10	0	44	0	0
T11	1097	0	0	0
T12	2904	0	0	0
T13	1361	0	0	0
T14	1208	0	0	0
T15	863	0	0	0
T16	1572	0	0	0
T17	5521	0	0	0
T18	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321974969	354875	0	0
T1	1225	6	0	0
T2	1898	20	0	0
T3	2230	17	0	0
T4	0	2	0	0
T5	0	25	0	0
T6	0	24	0	0
T11	1097	0	0	0
T12	2904	0	0	0
T13	1361	0	0	0
T14	1208	0	0	0
T15	863	9	0	0
T16	0	31	0	0
T19	1134	6	0	0
T20	0	13	0	0
T21	4620	0	0	0