Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5777912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26713450

1

T22

43

T23

322

T24

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12743362	1			T22	29		T23	78		T24	52
values[0x0]	9691644	1			T22	16		T23	129		T24	24
values[0x1]	10056356	1			T22	13		T23	131		T24	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4420084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28071278

1

T22

47

T23

334

T24

96

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	122852	1			T26	1		T1	5		T2	1
valid_sources[0x01]	111704	1			T23	5		T25	6		T26	1
valid_sources[0x02]	113243	1			T1	4		T15	1		T17	1
valid_sources[0x03]	121537	1			T23	3		T1	3		T15	2
valid_sources[0x04]	120054	1			T26	4		T1	5		T14	2
valid_sources[0x05]	129634	1			T26	2		T1	3		T2	2
valid_sources[0x06]	121766	1			T26	1		T1	4		T2	10
valid_sources[0x07]	127512	1			T26	1		T1	4		T14	1
valid_sources[0x08]	115984	1			T23	3		T26	3		T1	4
valid_sources[0x09]	138666	1			T23	23		T26	4		T1	5
valid_sources[0x0a]	120440	1			T23	3		T25	3		T26	4
valid_sources[0x0b]	129377	1			T23	3		T26	2		T1	6
valid_sources[0x0c]	113971	1			T26	4		T1	5		T14	1
valid_sources[0x0d]	115003	1			T26	3		T1	1		T18	1
valid_sources[0x0e]	130747	1			T26	2		T1	3		T2	2
valid_sources[0x0f]	119427	1			T1	6		T14	1		T16	4
valid_sources[0x10]	115316	1			T24	12		T26	1		T28	1
valid_sources[0x11]	118922	1			T26	1		T1	6		T15	3
valid_sources[0x12]	127486	1			T1	3		T2	3		T79	3
valid_sources[0x13]	112794	1			T23	6		T26	1		T1	7
valid_sources[0x14]	128755	1			T23	1		T15	2		T18	1
valid_sources[0x15]	128474	1			T26	4		T1	1		T2	1
valid_sources[0x16]	118637	1			T26	5		T1	4		T2	8
valid_sources[0x17]	130241	1			T26	7		T28	1		T1	6
valid_sources[0x18]	125172	1			T23	9		T26	1		T1	11
valid_sources[0x19]	123775	1			T23	2		T26	2		T1	5
valid_sources[0x1a]	129724	1			T26	1		T1	2		T2	2
valid_sources[0x1b]	125754	1			T1	2		T15	2		T84	1
valid_sources[0x1c]	122324	1			T1	7		T13	12		T14	2
valid_sources[0x1d]	118624	1			T23	2		T26	1		T28	1
valid_sources[0x1e]	213488	1			T26	1		T1	5		T15	1
valid_sources[0x1f]	121671	1			T23	4		T26	7		T28	2
valid_sources[0x20]	130458	1			T26	5		T1	3		T2	1
valid_sources[0x21]	114676	1			T23	2		T26	4		T1	3
valid_sources[0x22]	130758	1			T23	4		T28	1		T1	6
valid_sources[0x23]	118022	1			T23	4		T26	5		T1	1
valid_sources[0x24]	124440	1			T23	8		T26	5		T1	5
valid_sources[0x25]	120842	1			T26	3		T1	2		T18	2
valid_sources[0x26]	116721	1			T1	4		T2	1		T15	1
valid_sources[0x27]	124231	1			T26	2		T1	4		T2	1
valid_sources[0x28]	131242	1			T26	4		T1	6		T2	2
valid_sources[0x29]	127296	1			T23	3		T24	19		T1	4
valid_sources[0x2a]	123857	1			T23	2		T26	4		T1	5
valid_sources[0x2b]	122440	1			T1	5		T11	8		T15	1
valid_sources[0x2c]	121538	1			T1	3		T2	1		T14	1
valid_sources[0x2d]	126264	1			T26	2		T27	3		T1	3
valid_sources[0x2e]	121799	1			T26	1		T1	4		T2	1
valid_sources[0x2f]	118496	1			T26	6		T1	5		T15	1
valid_sources[0x30]	132284	1			T26	3		T1	5		T2	2
valid_sources[0x31]	125175	1			T26	4		T1	5		T15	1
valid_sources[0x32]	116027	1			T26	6		T28	1		T1	6
valid_sources[0x33]	126962	1			T26	6		T1	6		T15	1
valid_sources[0x34]	124421	1			T23	1		T1	3		T2	3
valid_sources[0x35]	168474	1			T23	1		T25	7		T26	2
valid_sources[0x36]	132139	1			T26	5		T1	5		T2	23
valid_sources[0x37]	245332	1			T26	1		T1	5		T108	9
valid_sources[0x38]	127578	1			T1	2		T2	1		T13	1
valid_sources[0x39]	122761	1			T24	10		T26	3		T1	5
valid_sources[0x3a]	107383	1			T26	1		T1	2		T2	1
valid_sources[0x3b]	123617	1			T26	5		T1	12		T2	7
valid_sources[0x3c]	115061	1			T26	3		T28	1		T1	9
valid_sources[0x3d]	119729	1			T26	2		T1	7		T104	1
valid_sources[0x3e]	114470	1			T1	2		T15	1		T18	4
valid_sources[0x3f]	129239	1			T1	4		T11	1		T15	1
valid_sources[0x40]	123727	1			T26	9		T1	4		T2	4
valid_sources[0x41]	128521	1			T23	1		T27	2		T1	6
valid_sources[0x42]	132612	1			T26	3		T1	4		T2	4
valid_sources[0x43]	116981	1			T26	6		T1	4		T32	1
valid_sources[0x44]	123038	1			T26	1		T1	7		T11	7
valid_sources[0x45]	117712	1			T25	2		T26	1		T1	7
valid_sources[0x46]	131148	1			T23	3		T26	3		T1	5
valid_sources[0x47]	131908	1			T24	7		T27	1		T1	4
valid_sources[0x48]	111436	1			T23	4		T25	2		T1	5
valid_sources[0x49]	114854	1			T23	13		T1	6		T15	1
valid_sources[0x4a]	123845	1			T28	1		T1	5		T2	1
valid_sources[0x4b]	120957	1			T23	2		T26	3		T27	3
valid_sources[0x4c]	125289	1			T26	1		T1	5		T2	1
valid_sources[0x4d]	126082	1			T26	1		T1	5		T2	4
valid_sources[0x4e]	124628	1			T25	2		T1	7		T13	5
valid_sources[0x4f]	115534	1			T23	3		T28	1		T1	2
valid_sources[0x50]	118282	1			T23	1		T26	13		T1	4
valid_sources[0x51]	114992	1			T26	4		T28	1		T1	6
valid_sources[0x52]	123127	1			T25	1		T26	3		T1	4
valid_sources[0x53]	128371	1			T1	2		T2	2		T14	6
valid_sources[0x54]	122095	1			T26	4		T1	6		T14	3
valid_sources[0x55]	126961	1			T26	1		T1	5		T15	3
valid_sources[0x56]	124045	1			T26	2		T1	2		T15	2
valid_sources[0x57]	121196	1			T1	6		T2	24		T15	2
valid_sources[0x58]	125164	1			T24	3		T27	4		T1	4
valid_sources[0x59]	118982	1			T26	5		T28	1		T1	5
valid_sources[0x5a]	122059	1			T23	3		T1	5		T15	2
valid_sources[0x5b]	119712	1			T23	2		T26	1		T1	6
valid_sources[0x5c]	118098	1			T23	7		T26	1		T1	5
valid_sources[0x5d]	133994	1			T26	1		T1	3		T15	1
valid_sources[0x5e]	126512	1			T23	1		T26	9		T1	5
valid_sources[0x5f]	103790	1			T26	2		T1	1		T2	3
valid_sources[0x60]	132631	1			T1	5		T2	1		T15	1
valid_sources[0x61]	117098	1			T23	3		T26	7		T1	4
valid_sources[0x62]	124473	1			T23	4		T26	3		T1	5
valid_sources[0x63]	194004	1			T25	2		T1	7		T15	1
valid_sources[0x64]	122059	1			T26	1		T1	3		T11	1
valid_sources[0x65]	122686	1			T26	4		T1	7		T2	4
valid_sources[0x66]	119900	1			T24	1		T1	8		T15	1
valid_sources[0x67]	144678	1			T26	5		T28	1		T1	10
valid_sources[0x68]	117947	1			T26	6		T1	5		T15	2
valid_sources[0x69]	119131	1			T26	5		T1	5		T2	1
valid_sources[0x6a]	118579	1			T23	7		T26	2		T1	4
valid_sources[0x6b]	120412	1			T23	8		T26	5		T1	7
valid_sources[0x6c]	121013	1			T26	2		T1	6		T2	4
valid_sources[0x6d]	121726	1			T23	1		T1	6		T2	2
valid_sources[0x6e]	123068	1			T1	3		T2	1		T15	1
valid_sources[0x6f]	103591	1			T26	4		T1	3		T15	2
valid_sources[0x70]	115224	1			T26	4		T28	1		T1	4
valid_sources[0x71]	114873	1			T27	5		T1	3		T15	2
valid_sources[0x72]	160425	1			T25	1		T26	9		T1	9
valid_sources[0x73]	121857	1			T26	3		T1	8		T2	1
valid_sources[0x74]	124420	1			T25	2		T28	3		T1	8
valid_sources[0x75]	120453	1			T1	2		T18	3		T4	1
valid_sources[0x76]	125024	1			T26	2		T1	4		T14	1
valid_sources[0x77]	127018	1			T26	3		T1	7		T15	2
valid_sources[0x78]	120383	1			T26	9		T1	4		T15	3
valid_sources[0x79]	119584	1			T23	5		T26	2		T27	2
valid_sources[0x7a]	129485	1			T1	6		T17	1		T4	1
valid_sources[0x7b]	119095	1			T26	5		T1	4		T2	4
valid_sources[0x7c]	128771	1			T26	4		T1	4		T2	4
valid_sources[0x7d]	126405	1			T23	2		T26	1		T1	5
valid_sources[0x7e]	117720	1			T26	2		T1	5		T14	2
valid_sources[0x7f]	133236	1			T25	3		T26	3		T1	7
valid_sources[0x80]	123483	1			T24	6		T26	2		T1	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7403069

1

T22

14

T23

77

T24

52

values[0x0]

all_enables

biggest_size

9655305

1

T22

16

T23

128

T24

24

values[0x1]

all_enables

biggest_size

9655076

1

T22

13

T23

117

T24

20