Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	309494594	0	0	0
ctrl_en_input_filter_rd_A	309494594	418011	0	0
intr_ctrl_en_falling_rd_A	309494594	447754	0	0
intr_ctrl_en_lvlhigh_rd_A	309494594	419888	0	0
intr_ctrl_en_lvllow_rd_A	309494594	443661	0	0
intr_ctrl_en_rising_rd_A	309494594	418482	0	0
intr_enable_rd_A	309494594	420211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	418011	0	0
T1	11276	118	0	0
T2	7815	91	0	0
T3	0	89	0	0
T4	0	23	0	0
T5	0	147	0	0
T6	0	11	0	0
T7	0	88	0	0
T8	0	25	0	0
T9	0	29	0	0
T10	0	99	0	0
T11	937	0	0	0
T12	1435	0	0	0
T13	1350	0	0	0
T14	1471	0	0	0
T15	3971	0	0	0
T16	1287	0	0	0
T17	1130	0	0	0
T18	1623	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	447754	0	0
T1	11276	95	0	0
T2	7815	82	0	0
T3	0	14	0	0
T4	0	2	0	0
T5	0	51	0	0
T6	0	11	0	0
T7	0	99	0	0
T8	0	14	0	0
T9	0	44	0	0
T10	0	109	0	0
T11	937	0	0	0
T12	1435	0	0	0
T13	1350	0	0	0
T14	1471	0	0	0
T15	3971	0	0	0
T16	1287	0	0	0
T17	1130	0	0	0
T18	1623	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	419888	0	0
T1	11276	168	0	0
T2	7815	83	0	0
T3	0	37	0	0
T4	0	16	0	0
T5	0	101	0	0
T6	0	20	0	0
T7	0	81	0	0
T8	0	31	0	0
T9	0	34	0	0
T10	0	104	0	0
T11	937	0	0	0
T12	1435	0	0	0
T13	1350	0	0	0
T14	1471	0	0	0
T15	3971	0	0	0
T16	1287	0	0	0
T17	1130	0	0	0
T18	1623	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	443661	0	0
T1	11276	110	0	0
T2	7815	86	0	0
T3	0	105	0	0
T4	0	29	0	0
T5	0	64	0	0
T6	0	7	0	0
T7	0	90	0	0
T8	0	7	0	0
T9	0	25	0	0
T10	0	135	0	0
T11	937	0	0	0
T12	1435	0	0	0
T13	1350	0	0	0
T14	1471	0	0	0
T15	3971	0	0	0
T16	1287	0	0	0
T17	1130	0	0	0
T18	1623	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	418482	0	0
T1	11276	133	0	0
T2	7815	88	0	0
T3	0	4	0	0
T4	0	19	0	0
T5	0	62	0	0
T6	0	7	0	0
T7	0	82	0	0
T8	0	13	0	0
T9	0	48	0	0
T10	0	94	0	0
T11	937	0	0	0
T12	1435	0	0	0
T13	1350	0	0	0
T14	1471	0	0	0
T15	3971	0	0	0
T16	1287	0	0	0
T17	1130	0	0	0
T18	1623	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309494594	420211	0	0
T1	11276	169	0	0
T2	7815	57	0	0
T3	0	51	0	0
T4	0	25	0	0
T5	0	63	0	0
T6	0	12	0	0
T7	0	68	0	0
T11	937	0	0	0
T12	1435	0	0	0
T13	1350	0	0	0
T14	1471	0	0	0
T15	3971	0	0	0
T16	1287	0	0	0
T17	1130	0	0	0
T18	1623	0	0	0
T19	0	34	0	0
T20	0	8	0	0
T21	0	25	0	0