Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5402643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25900623

1

T28

294

T29

17

T1

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12077034	1			T28	150		T29	11		T1	46
values[0x0]	9421107	1			T28	76		T29	7		T1	25
values[0x1]	9805125	1			T28	68		T29	4		T1	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4107250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27196016

1

T28

294

T29

19

T1

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	119594	1			T28	3		T12	2		T13	1
valid_sources[0x01]	116547	1			T12	2		T15	3		T3	2
valid_sources[0x02]	122432	1			T28	1		T12	4		T15	1
valid_sources[0x03]	118976	1			T13	4		T2	13		T4	1
valid_sources[0x04]	117479	1			T29	1		T12	3		T14	1
valid_sources[0x05]	129953	1			T28	1		T15	1		T4	2
valid_sources[0x06]	111926	1			T28	1		T12	1		T15	2
valid_sources[0x07]	119463	1			T29	1		T15	6		T2	16
valid_sources[0x08]	117785	1			T28	2		T12	3		T13	5
valid_sources[0x09]	123162	1			T12	3		T13	2		T24	6
valid_sources[0x0a]	123920	1			T28	1		T12	2		T15	2
valid_sources[0x0b]	125965	1			T28	1		T4	4		T23	4
valid_sources[0x0c]	112990	1			T12	3		T13	2		T15	3
valid_sources[0x0d]	120116	1			T12	3		T23	4		T24	5
valid_sources[0x0e]	121130	1			T12	1		T14	2		T3	7
valid_sources[0x0f]	117312	1			T28	4		T12	1		T15	2
valid_sources[0x10]	125034	1			T29	4		T12	1		T4	1
valid_sources[0x11]	119833	1			T12	2		T13	1		T14	1
valid_sources[0x12]	111746	1			T28	3		T12	2		T15	1
valid_sources[0x13]	140452	1			T28	2		T12	1		T4	1
valid_sources[0x14]	112096	1			T12	4		T15	6		T4	1
valid_sources[0x15]	172310	1			T28	2		T11	4		T12	1
valid_sources[0x16]	120039	1			T12	2		T15	3		T3	3
valid_sources[0x17]	120196	1			T28	2		T12	3		T13	2
valid_sources[0x18]	166737	1			T28	3		T12	2		T15	4
valid_sources[0x19]	133769	1			T28	2		T18	5		T23	1
valid_sources[0x1a]	138548	1			T12	1		T13	8		T15	2
valid_sources[0x1b]	126083	1			T28	7		T15	4		T3	1
valid_sources[0x1c]	116803	1			T12	2		T13	8		T2	14
valid_sources[0x1d]	117636	1			T12	1		T13	7		T15	1
valid_sources[0x1e]	119329	1			T12	1		T14	2		T15	2
valid_sources[0x1f]	115209	1			T11	2		T12	2		T15	1
valid_sources[0x20]	116405	1			T28	2		T13	1		T15	2
valid_sources[0x21]	119201	1			T12	2		T15	3		T4	2
valid_sources[0x22]	116798	1			T28	1		T12	1		T23	10
valid_sources[0x23]	113101	1			T28	1		T12	3		T18	1
valid_sources[0x24]	113903	1			T12	2		T15	1		T18	1
valid_sources[0x25]	121228	1			T28	1		T12	2		T18	2
valid_sources[0x26]	118121	1			T29	1		T12	1		T13	3
valid_sources[0x27]	111348	1			T28	3		T15	3		T3	2
valid_sources[0x28]	117381	1			T28	1		T12	1		T15	1
valid_sources[0x29]	118884	1			T28	1		T12	4		T14	1
valid_sources[0x2a]	120087	1			T28	2		T13	3		T3	1
valid_sources[0x2b]	117330	1			T12	4		T16	21		T18	1
valid_sources[0x2c]	117607	1			T28	2		T13	3		T15	6
valid_sources[0x2d]	171077	1			T12	2		T3	1		T23	4
valid_sources[0x2e]	123193	1			T18	1		T24	11		T108	1
valid_sources[0x2f]	119570	1			T12	2		T24	7		T25	1
valid_sources[0x30]	119997	1			T28	2		T12	2		T15	1
valid_sources[0x31]	117994	1			T12	2		T15	1		T24	4
valid_sources[0x32]	122952	1			T12	3		T18	2		T3	1
valid_sources[0x33]	117125	1			T18	3		T4	1		T23	3
valid_sources[0x34]	112830	1			T12	2		T15	2		T3	5
valid_sources[0x35]	115219	1			T21	1		T24	13		T102	1
valid_sources[0x36]	113390	1			T28	1		T12	1		T15	1
valid_sources[0x37]	121472	1			T29	1		T12	2		T13	1
valid_sources[0x38]	110149	1			T28	1		T12	2		T15	4
valid_sources[0x39]	117877	1			T28	2		T12	3		T14	3
valid_sources[0x3a]	117695	1			T28	2		T12	2		T15	3
valid_sources[0x3b]	114898	1			T12	4		T15	2		T23	1
valid_sources[0x3c]	128229	1			T15	3		T3	4		T23	2
valid_sources[0x3d]	119398	1			T28	2		T12	2		T13	3
valid_sources[0x3e]	118764	1			T28	1		T13	1		T15	1
valid_sources[0x3f]	114502	1			T1	7		T12	2		T21	1
valid_sources[0x40]	119576	1			T1	7		T13	2		T2	31
valid_sources[0x41]	113196	1			T28	4		T15	2		T24	8
valid_sources[0x42]	117345	1			T11	1		T14	1		T15	2
valid_sources[0x43]	118478	1			T28	1		T12	1		T13	1
valid_sources[0x44]	123453	1			T12	2		T4	4		T23	2
valid_sources[0x45]	125698	1			T28	2		T12	1		T3	4
valid_sources[0x46]	120432	1			T12	1		T15	1		T3	3
valid_sources[0x47]	126593	1			T12	1		T15	2		T4	1
valid_sources[0x48]	116890	1			T12	1		T13	9		T15	1
valid_sources[0x49]	118092	1			T28	2		T12	2		T21	2
valid_sources[0x4a]	194270	1			T28	2		T12	1		T3	2
valid_sources[0x4b]	115212	1			T12	3		T13	1		T15	3
valid_sources[0x4c]	111822	1			T28	3		T12	3		T15	1
valid_sources[0x4d]	167201	1			T4	1		T23	2		T24	7
valid_sources[0x4e]	118203	1			T28	3		T12	1		T15	8
valid_sources[0x4f]	122145	1			T28	2		T12	1		T3	1
valid_sources[0x50]	115196	1			T28	3		T12	2		T13	5
valid_sources[0x51]	120503	1			T28	1		T12	1		T14	4
valid_sources[0x52]	118770	1			T28	2		T29	1		T11	1
valid_sources[0x53]	109447	1			T28	2		T11	1		T12	4
valid_sources[0x54]	121312	1			T28	3		T12	4		T15	1
valid_sources[0x55]	114745	1			T12	4		T15	1		T2	2
valid_sources[0x56]	113118	1			T12	6		T14	1		T23	1
valid_sources[0x57]	112951	1			T28	2		T3	1		T4	1
valid_sources[0x58]	119214	1			T28	1		T12	1		T15	1
valid_sources[0x59]	123360	1			T28	4		T12	1		T13	8
valid_sources[0x5a]	111741	1			T15	2		T3	8		T4	3
valid_sources[0x5b]	175231	1			T28	4		T12	3		T4	3
valid_sources[0x5c]	118763	1			T28	1		T15	1		T18	1
valid_sources[0x5d]	116369	1			T12	1		T15	1		T24	12
valid_sources[0x5e]	113189	1			T12	4		T15	1		T23	6
valid_sources[0x5f]	128017	1			T28	1		T12	1		T13	1
valid_sources[0x60]	129098	1			T28	1		T12	1		T13	4
valid_sources[0x61]	115310	1			T28	5		T11	2		T12	1
valid_sources[0x62]	112698	1			T12	1		T18	1		T3	3
valid_sources[0x63]	110160	1			T28	1		T1	7		T12	3
valid_sources[0x64]	118976	1			T28	1		T12	2		T13	6
valid_sources[0x65]	116623	1			T28	1		T11	5		T12	3
valid_sources[0x66]	112979	1			T15	2		T2	21		T21	2
valid_sources[0x67]	115005	1			T11	1		T12	2		T15	1
valid_sources[0x68]	114605	1			T12	2		T15	2		T4	3
valid_sources[0x69]	115308	1			T28	1		T29	1		T12	1
valid_sources[0x6a]	121705	1			T12	2		T15	2		T18	1
valid_sources[0x6b]	117998	1			T28	2		T12	3		T15	2
valid_sources[0x6c]	121352	1			T29	2		T12	2		T17	130
valid_sources[0x6d]	116142	1			T28	4		T11	1		T12	1
valid_sources[0x6e]	125785	1			T28	1		T12	2		T13	1
valid_sources[0x6f]	115830	1			T13	2		T15	3		T3	4
valid_sources[0x70]	110104	1			T12	1		T15	6		T18	1
valid_sources[0x71]	286595	1			T28	3		T12	3		T13	3
valid_sources[0x72]	113297	1			T29	1		T12	3		T15	4
valid_sources[0x73]	124680	1			T14	1		T15	1		T18	1
valid_sources[0x74]	114164	1			T12	1		T15	1		T3	1
valid_sources[0x75]	111723	1			T11	1		T15	4		T3	1
valid_sources[0x76]	111953	1			T12	1		T15	4		T3	2
valid_sources[0x77]	314434	1			T1	7		T15	6		T3	2
valid_sources[0x78]	115754	1			T28	2		T13	1		T15	2
valid_sources[0x79]	121371	1			T12	4		T15	2		T4	2
valid_sources[0x7a]	111422	1			T28	4		T3	3		T23	2
valid_sources[0x7b]	117538	1			T28	1		T12	5		T15	1
valid_sources[0x7c]	109422	1			T12	3		T4	1		T23	1
valid_sources[0x7d]	120715	1			T28	1		T12	1		T15	1
valid_sources[0x7e]	129047	1			T28	2		T12	1		T13	5
valid_sources[0x7f]	114098	1			T28	1		T15	3		T18	1
valid_sources[0x80]	118509	1			T28	4		T11	1		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7141695

1

T28

150

T29

6

T1

22

values[0x0]

all_enables

biggest_size

9382029

1

T28

76

T29

7

T1

24

values[0x1]

all_enables

biggest_size

9376899

1

T28

68

T29

4

T1

18