Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	338781419	0	0	0
ctrl_en_input_filter_rd_A	338781419	456343	0	0
intr_ctrl_en_falling_rd_A	338781419	486515	0	0
intr_ctrl_en_lvlhigh_rd_A	338781419	458223	0	0
intr_ctrl_en_lvllow_rd_A	338781419	486634	0	0
intr_ctrl_en_rising_rd_A	338781419	458526	0	0
intr_enable_rd_A	338781419	458422	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	456343	0	0
T1	2096	7	0	0
T2	3207	4	0	0
T3	0	41	0	0
T4	0	21	0	0
T5	0	5	0	0
T6	0	73	0	0
T7	0	14	0	0
T8	0	101	0	0
T9	0	8	0	0
T10	0	2	0	0
T11	1531	0	0	0
T12	3405	0	0	0
T13	2052	0	0	0
T14	749	0	0	0
T15	3197	0	0	0
T16	1324	0	0	0
T17	4405	0	0	0
T18	1184	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	486515	0	0
T1	2096	4	0	0
T2	3207	9	0	0
T3	0	36	0	0
T4	0	23	0	0
T5	0	5	0	0
T6	0	90	0	0
T7	0	8	0	0
T8	0	75	0	0
T10	0	6	0	0
T11	1531	0	0	0
T12	3405	0	0	0
T13	2052	0	0	0
T14	749	0	0	0
T15	3197	0	0	0
T16	1324	0	0	0
T17	4405	0	0	0
T18	1184	0	0	0
T19	0	61	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	458223	0	0
T1	2096	14	0	0
T2	3207	32	0	0
T3	0	41	0	0
T4	0	2	0	0
T5	0	8	0	0
T6	0	75	0	0
T7	0	4	0	0
T8	0	128	0	0
T10	0	4	0	0
T11	1531	0	0	0
T12	3405	0	0	0
T13	2052	0	0	0
T14	749	0	0	0
T15	3197	0	0	0
T16	1324	0	0	0
T17	4405	0	0	0
T18	1184	0	0	0
T20	0	2	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	486634	0	0
T2	3207	60	0	0
T3	5211	36	0	0
T4	2848	13	0	0
T5	0	9	0	0
T6	0	86	0	0
T7	0	10	0	0
T8	0	112	0	0
T9	0	7	0	0
T10	0	14	0	0
T17	4405	0	0	0
T18	1184	0	0	0
T20	1483	5	0	0
T21	1162	0	0	0
T22	1366	0	0	0
T23	3368	0	0	0
T24	5646	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	458526	0	0
T1	2096	11	0	0
T2	3207	73	0	0
T3	0	36	0	0
T4	0	35	0	0
T5	0	11	0	0
T6	0	39	0	0
T7	0	11	0	0
T8	0	84	0	0
T9	0	3	0	0
T10	0	10	0	0
T11	1531	0	0	0
T12	3405	0	0	0
T13	2052	0	0	0
T14	749	0	0	0
T15	3197	0	0	0
T16	1324	0	0	0
T17	4405	0	0	0
T18	1184	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	338781419	458422	0	0
T2	3207	26	0	0
T3	5211	19	0	0
T4	2848	30	0	0
T16	1324	29	0	0
T17	4405	0	0	0
T18	1184	0	0	0
T20	0	4	0	0
T21	1162	8	0	0
T22	1366	41	0	0
T23	3368	0	0	0
T24	5646	0	0	0
T25	0	23	0	0
T26	0	44	0	0
T27	0	10	0	0