Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4946749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23968672

1

T23

239

T24

174

T25

214

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11105536	1			T23	111		T24	299		T25	106
values[0x0]	8717655	1			T23	78		T24	20		T25	53
values[0x1]	9092230	1			T23	75		T24	10		T25	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3751530	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25163891

1

T23

243

T24

207

T25

214

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	109470	1			T11	1		T15	21		T29	1
valid_sources[0x01]	114986	1			T23	1		T21	1		T2	2
valid_sources[0x02]	109348	1			T12	40		T2	1		T72	3
valid_sources[0x03]	110905	1			T23	1		T11	2		T2	1
valid_sources[0x04]	107949	1			T25	9		T28	1		T13	1
valid_sources[0x05]	104430	1			T23	2		T25	17		T28	6
valid_sources[0x06]	109140	1			T29	2		T3	6		T4	1
valid_sources[0x07]	104963	1			T25	12		T26	1		T28	2
valid_sources[0x08]	106349	1			T23	1		T25	2		T26	1
valid_sources[0x09]	106199	1			T23	1		T28	3		T2	1
valid_sources[0x0a]	106629	1			T24	5		T28	3		T21	1
valid_sources[0x0b]	103772	1			T1	6		T72	1		T22	1
valid_sources[0x0c]	112051	1			T24	5		T26	2		T28	2
valid_sources[0x0d]	112308	1			T28	2		T21	1		T1	9
valid_sources[0x0e]	104313	1			T23	2		T21	1		T72	1
valid_sources[0x0f]	117412	1			T21	1		T1	9		T11	3
valid_sources[0x10]	108827	1			T23	5		T2	1		T29	1
valid_sources[0x11]	103171	1			T23	1		T13	2		T3	3
valid_sources[0x12]	103314	1			T23	1		T29	3		T3	3
valid_sources[0x13]	103397	1			T23	1		T28	3		T2	1
valid_sources[0x14]	109890	1			T23	3		T13	1		T2	1
valid_sources[0x15]	112327	1			T23	2		T28	1		T72	2
valid_sources[0x16]	110168	1			T23	1		T29	1		T3	9
valid_sources[0x17]	112316	1			T28	4		T13	1		T72	1
valid_sources[0x18]	109516	1			T25	3		T21	1		T2	3
valid_sources[0x19]	108786	1			T23	3		T24	5		T2	3
valid_sources[0x1a]	105877	1			T23	2		T28	2		T2	2
valid_sources[0x1b]	223826	1			T23	1		T27	159		T21	1
valid_sources[0x1c]	105703	1			T11	3		T2	1		T15	3
valid_sources[0x1d]	107245	1			T33	208		T3	7		T4	3
valid_sources[0x1e]	110778	1			T21	1		T2	3		T15	15
valid_sources[0x1f]	104100	1			T26	1		T28	1		T11	16
valid_sources[0x20]	100524	1			T23	1		T21	1		T2	2
valid_sources[0x21]	141535	1			T23	2		T26	1		T28	2
valid_sources[0x22]	106550	1			T23	3		T29	2		T3	5
valid_sources[0x23]	111469	1			T1	3		T11	1		T2	1
valid_sources[0x24]	100823	1			T2	1		T72	4		T29	3
valid_sources[0x25]	103520	1			T23	1		T26	1		T28	1
valid_sources[0x26]	105666	1			T23	1		T27	7		T28	3
valid_sources[0x27]	110988	1			T23	3		T25	15		T11	1
valid_sources[0x28]	105402	1			T23	2		T28	1		T2	1
valid_sources[0x29]	112025	1			T2	1		T18	3		T72	2
valid_sources[0x2a]	107163	1			T23	1		T2	1		T29	3
valid_sources[0x2b]	104424	1			T24	65		T25	21		T11	5
valid_sources[0x2c]	110615	1			T23	3		T2	4		T72	1
valid_sources[0x2d]	136177	1			T23	1		T28	1		T21	1
valid_sources[0x2e]	105855	1			T26	1		T28	4		T11	2
valid_sources[0x2f]	105902	1			T23	1		T28	1		T15	14
valid_sources[0x30]	113032	1			T23	1		T26	1		T2	1
valid_sources[0x31]	113359	1			T26	1		T1	3		T2	1
valid_sources[0x32]	103924	1			T23	3		T28	3		T2	1
valid_sources[0x33]	105626	1			T23	2		T25	4		T11	1
valid_sources[0x34]	108594	1			T18	10		T72	3		T3	1
valid_sources[0x35]	103702	1			T23	2		T11	1		T72	2
valid_sources[0x36]	108370	1			T23	3		T2	1		T72	1
valid_sources[0x37]	114028	1			T23	3		T2	1		T72	3
valid_sources[0x38]	109416	1			T2	1		T72	1		T33	74
valid_sources[0x39]	104203	1			T23	2		T26	1		T28	2
valid_sources[0x3a]	105146	1			T23	3		T25	6		T27	2
valid_sources[0x3b]	106985	1			T23	2		T24	5		T28	1
valid_sources[0x3c]	223222	1			T72	2		T29	2		T3	1
valid_sources[0x3d]	106148	1			T23	3		T2	2		T18	30
valid_sources[0x3e]	208804	1			T23	1		T26	1		T21	1
valid_sources[0x3f]	108429	1			T23	2		T26	2		T28	1
valid_sources[0x40]	104594	1			T23	1		T28	3		T2	3
valid_sources[0x41]	104103	1			T23	2		T2	3		T72	5
valid_sources[0x42]	105721	1			T24	5		T25	4		T21	1
valid_sources[0x43]	110305	1			T23	1		T24	3		T21	1
valid_sources[0x44]	108448	1			T23	1		T28	2		T2	1
valid_sources[0x45]	107381	1			T23	1		T24	5		T2	1
valid_sources[0x46]	108083	1			T25	4		T28	3		T15	4
valid_sources[0x47]	114893	1			T23	2		T2	4		T72	1
valid_sources[0x48]	107793	1			T23	1		T28	1		T21	1
valid_sources[0x49]	112295	1			T23	1		T28	3		T11	1
valid_sources[0x4a]	112255	1			T23	1		T11	3		T2	2
valid_sources[0x4b]	199271	1			T13	2		T2	1		T72	1
valid_sources[0x4c]	107651	1			T23	1		T26	1		T72	1
valid_sources[0x4d]	108177	1			T23	1		T28	1		T18	15
valid_sources[0x4e]	103217	1			T23	2		T21	1		T11	6
valid_sources[0x4f]	106191	1			T23	1		T28	3		T1	21
valid_sources[0x50]	103033	1			T23	1		T28	1		T72	1
valid_sources[0x51]	107986	1			T72	1		T33	1		T22	1
valid_sources[0x52]	106862	1			T28	1		T21	1		T2	1
valid_sources[0x53]	103759	1			T23	2		T24	5		T28	1
valid_sources[0x54]	113127	1			T23	1		T26	1		T28	3
valid_sources[0x55]	103861	1			T23	1		T72	3		T3	5
valid_sources[0x56]	106968	1			T23	1		T28	1		T11	1
valid_sources[0x57]	107447	1			T23	1		T24	5		T28	2
valid_sources[0x58]	105893	1			T23	1		T26	1		T28	2
valid_sources[0x59]	105937	1			T2	1		T72	1		T29	3
valid_sources[0x5a]	108833	1			T28	1		T11	4		T13	1
valid_sources[0x5b]	108207	1			T21	1		T13	1		T15	7
valid_sources[0x5c]	107147	1			T24	5		T26	1		T21	1
valid_sources[0x5d]	105382	1			T21	1		T2	2		T72	1
valid_sources[0x5e]	103714	1			T23	3		T28	1		T2	1
valid_sources[0x5f]	105931	1			T28	2		T21	2		T72	3
valid_sources[0x60]	103507	1			T23	1		T24	5		T72	1
valid_sources[0x61]	105293	1			T23	1		T24	5		T2	3
valid_sources[0x62]	108212	1			T23	1		T72	1		T29	1
valid_sources[0x63]	106743	1			T23	2		T28	2		T21	1
valid_sources[0x64]	111900	1			T23	1		T72	2		T29	4
valid_sources[0x65]	264954	1			T26	1		T28	3		T21	1
valid_sources[0x66]	106089	1			T23	4		T13	1		T2	1
valid_sources[0x67]	106179	1			T28	1		T72	2		T22	1
valid_sources[0x68]	107230	1			T23	1		T26	1		T27	1
valid_sources[0x69]	110637	1			T27	1		T11	14		T4	1
valid_sources[0x6a]	113195	1			T2	3		T18	10		T99	22
valid_sources[0x6b]	102249	1			T24	116		T26	1		T28	6
valid_sources[0x6c]	114591	1			T72	1		T29	8		T5	1
valid_sources[0x6d]	111081	1			T23	1		T28	1		T11	1
valid_sources[0x6e]	108469	1			T23	4		T2	1		T15	14
valid_sources[0x6f]	110066	1			T2	2		T72	4		T29	3
valid_sources[0x70]	109127	1			T23	2		T21	1		T15	1
valid_sources[0x71]	108705	1			T28	2		T72	4		T29	2
valid_sources[0x72]	258297	1			T23	1		T24	5		T28	2
valid_sources[0x73]	107895	1			T23	1		T28	1		T18	13
valid_sources[0x74]	107780	1			T23	2		T26	2		T28	1
valid_sources[0x75]	109046	1			T21	1		T2	3		T72	4
valid_sources[0x76]	236613	1			T23	2		T11	3		T29	4
valid_sources[0x77]	182383	1			T28	3		T1	34		T2	1
valid_sources[0x78]	105142	1			T23	2		T72	2		T29	5
valid_sources[0x79]	110663	1			T23	2		T21	2		T2	4
valid_sources[0x7a]	113220	1			T72	2		T22	1		T29	2
valid_sources[0x7b]	103770	1			T26	1		T72	1		T29	5
valid_sources[0x7c]	107244	1			T23	1		T24	5		T4	2
valid_sources[0x7d]	106880	1			T23	1		T25	5		T26	3
valid_sources[0x7e]	106739	1			T23	3		T28	5		T2	1
valid_sources[0x7f]	105426	1			T23	1		T28	1		T2	1
valid_sources[0x80]	103047	1			T23	1		T21	3		T2	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6604931

1

T23

88

T24

146

T25

106

values[0x0]

all_enables

biggest_size

8680882

1

T23

77

T24

20

T25

53

values[0x1]

all_enables

biggest_size

8682859

1

T23

74

T24

8

T25

55