Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	309588488	0	0	0
ctrl_en_input_filter_rd_A	309588488	389089	0	0
intr_ctrl_en_falling_rd_A	309588488	418643	0	0
intr_ctrl_en_lvlhigh_rd_A	309588488	391076	0	0
intr_ctrl_en_lvllow_rd_A	309588488	419231	0	0
intr_ctrl_en_rising_rd_A	309588488	390667	0	0
intr_enable_rd_A	309588488	390507	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	389089	0	0
T1	2413	40	0	0
T2	3985	13	0	0
T3	0	137	0	0
T4	0	26	0	0
T5	0	75	0	0
T6	0	30	0	0
T7	0	6	0	0
T8	0	28937	0	0
T9	0	233	0	0
T10	0	18492	0	0
T11	2525	0	0	0
T12	1050	0	0	0
T13	842	0	0	0
T14	1138	0	0	0
T15	3711	0	0	0
T16	1281	0	0	0
T17	841	0	0	0
T18	8597	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	418643	0	0
T1	2413	29	0	0
T2	3985	11	0	0
T3	0	157	0	0
T4	0	15	0	0
T5	0	81	0	0
T6	0	33	0	0
T7	0	2	0	0
T8	0	31288	0	0
T9	0	216	0	0
T10	0	19578	0	0
T11	2525	0	0	0
T12	1050	0	0	0
T13	842	0	0	0
T14	1138	0	0	0
T15	3711	0	0	0
T16	1281	0	0	0
T17	841	0	0	0
T18	8597	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	391076	0	0
T1	2413	44	0	0
T2	3985	9	0	0
T3	0	110	0	0
T4	0	20	0	0
T5	0	54	0	0
T6	0	49	0	0
T7	0	8	0	0
T8	0	29176	0	0
T9	0	200	0	0
T11	2525	0	0	0
T12	1050	0	0	0
T13	842	0	0	0
T14	1138	0	0	0
T15	3711	0	0	0
T16	1281	0	0	0
T17	841	0	0	0
T18	8597	0	0	0
T19	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	419231	0	0
T1	2413	49	0	0
T2	3985	8	0	0
T3	0	130	0	0
T4	0	18	0	0
T5	0	74	0	0
T6	0	40	0	0
T8	0	31424	0	0
T9	0	203	0	0
T10	0	20630	0	0
T11	2525	0	0	0
T12	1050	0	0	0
T13	842	0	0	0
T14	1138	0	0	0
T15	3711	0	0	0
T16	1281	0	0	0
T17	841	0	0	0
T18	8597	0	0	0
T20	0	9238	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	390667	0	0
T1	2413	61	0	0
T2	3985	27	0	0
T3	0	122	0	0
T4	0	15	0	0
T5	0	89	0	0
T6	0	44	0	0
T7	0	3	0	0
T8	0	28921	0	0
T9	0	199	0	0
T11	2525	0	0	0
T12	1050	0	0	0
T13	842	0	0	0
T14	1138	0	0	0
T15	3711	0	0	0
T16	1281	0	0	0
T17	841	0	0	0
T18	8597	0	0	0
T19	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309588488	390507	0	0
T1	2413	44	0	0
T2	3985	9	0	0
T3	0	142	0	0
T4	0	20	0	0
T5	0	70	0	0
T6	0	55	0	0
T8	0	28867	0	0
T11	2525	0	0	0
T12	1050	19	0	0
T13	842	0	0	0
T14	1138	0	0	0
T15	3711	0	0	0
T16	1281	0	0	0
T17	841	0	0	0
T21	1423	29	0	0
T22	0	34	0	0