Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5495206	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25782102

1

T1

53

T11

658

T2

159

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12177649	1			T1	30		T11	190		T2	77
values[0x0]	9366498	1			T1	19		T11	261		T2	56
values[0x1]	9733161	1			T1	18		T11	259		T2	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4193159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27084149

1

T1

55

T11

677

T2

164

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	117540	1			T11	1		T2	1		T13	43
valid_sources[0x01]	220491	1			T11	2		T2	1		T16	2
valid_sources[0x02]	113230	1			T16	4		T17	2		T18	1
valid_sources[0x03]	121394	1			T11	1		T16	1		T17	1
valid_sources[0x04]	119176	1			T11	1		T13	1		T16	2
valid_sources[0x05]	113494	1			T2	1		T16	3		T17	9
valid_sources[0x06]	114790	1			T16	2		T17	1		T4	1
valid_sources[0x07]	111452	1			T11	3		T2	2		T13	27
valid_sources[0x08]	124684	1			T16	3		T17	3		T19	8
valid_sources[0x09]	126530	1			T13	12		T16	2		T17	1
valid_sources[0x0a]	114821	1			T2	1		T16	5		T17	1
valid_sources[0x0b]	114547	1			T11	18		T16	2		T18	1
valid_sources[0x0c]	126050	1			T11	6		T2	1		T16	3
valid_sources[0x0d]	123285	1			T11	19		T2	3		T16	2
valid_sources[0x0e]	119045	1			T11	3		T16	2		T17	2
valid_sources[0x0f]	116165	1			T1	2		T11	5		T16	2
valid_sources[0x10]	109210	1			T11	1		T14	3		T16	2
valid_sources[0x11]	111814	1			T13	11		T16	5		T20	2
valid_sources[0x12]	114393	1			T16	1		T17	1		T18	1
valid_sources[0x13]	118982	1			T2	1		T13	28		T16	3
valid_sources[0x14]	239836	1			T2	2		T13	1		T15	9
valid_sources[0x15]	128446	1			T16	2		T20	1		T77	1
valid_sources[0x16]	110892	1			T1	7		T11	7		T13	27
valid_sources[0x17]	116008	1			T11	2		T13	7		T16	2
valid_sources[0x18]	118399	1			T11	1		T2	1		T16	2
valid_sources[0x19]	116899	1			T2	1		T13	8		T16	2
valid_sources[0x1a]	120665	1			T11	4		T2	1		T13	9
valid_sources[0x1b]	123076	1			T11	4		T13	35		T16	6
valid_sources[0x1c]	112267	1			T2	1		T16	2		T17	5
valid_sources[0x1d]	115677	1			T13	4		T16	2		T3	3
valid_sources[0x1e]	116557	1			T13	94		T16	2		T17	2
valid_sources[0x1f]	109998	1			T16	4		T17	1		T19	7
valid_sources[0x20]	222719	1			T13	41		T17	2		T77	2
valid_sources[0x21]	114661	1			T2	1		T13	6		T16	4
valid_sources[0x22]	115817	1			T2	1		T16	7		T73	1
valid_sources[0x23]	120129	1			T1	7		T11	12		T13	3
valid_sources[0x24]	111946	1			T2	2		T13	4		T16	3
valid_sources[0x25]	115438	1			T13	21		T16	3		T17	4
valid_sources[0x26]	118651	1			T16	2		T17	3		T4	2
valid_sources[0x27]	118116	1			T16	1		T17	4		T18	2
valid_sources[0x28]	123510	1			T11	15		T2	1		T13	8
valid_sources[0x29]	122050	1			T11	15		T2	1		T16	3
valid_sources[0x2a]	116138	1			T2	1		T16	4		T17	1
valid_sources[0x2b]	111699	1			T16	2		T17	2		T20	1
valid_sources[0x2c]	114870	1			T2	1		T16	3		T17	1
valid_sources[0x2d]	116115	1			T11	4		T13	35		T16	6
valid_sources[0x2e]	116084	1			T11	1		T13	13		T16	3
valid_sources[0x2f]	126132	1			T16	3		T17	3		T20	1
valid_sources[0x30]	252027	1			T11	1		T13	17		T16	2
valid_sources[0x31]	198025	1			T11	3		T2	1		T16	3
valid_sources[0x32]	180460	1			T13	27		T16	2		T17	1
valid_sources[0x33]	122523	1			T11	1		T16	4		T17	1
valid_sources[0x34]	116127	1			T11	6		T13	6		T16	5
valid_sources[0x35]	110831	1			T11	4		T2	1		T13	22
valid_sources[0x36]	124309	1			T2	1		T13	5		T16	2
valid_sources[0x37]	120978	1			T11	3		T2	1		T13	3
valid_sources[0x38]	120869	1			T11	3		T13	1		T16	2
valid_sources[0x39]	118639	1			T1	1		T11	4		T13	16
valid_sources[0x3a]	116433	1			T13	6		T16	4		T17	1
valid_sources[0x3b]	115736	1			T1	1		T2	1		T13	9
valid_sources[0x3c]	113008	1			T16	3		T17	2		T73	1
valid_sources[0x3d]	110460	1			T11	4		T2	1		T13	16
valid_sources[0x3e]	121395	1			T11	1		T2	1		T16	4
valid_sources[0x3f]	118861	1			T11	2		T13	2		T16	1
valid_sources[0x40]	111871	1			T11	5		T2	2		T16	3
valid_sources[0x41]	119365	1			T13	4		T16	5		T18	2
valid_sources[0x42]	115780	1			T16	2		T17	1		T18	1
valid_sources[0x43]	123197	1			T11	2		T13	17		T16	1
valid_sources[0x44]	113757	1			T11	5		T2	2		T13	8
valid_sources[0x45]	122084	1			T11	4		T16	3		T17	3
valid_sources[0x46]	125585	1			T11	12		T13	2		T16	1
valid_sources[0x47]	113063	1			T11	24		T2	1		T13	9
valid_sources[0x48]	120131	1			T11	1		T2	2		T16	4
valid_sources[0x49]	123536	1			T11	11		T16	1		T19	6
valid_sources[0x4a]	120195	1			T11	10		T2	1		T13	45
valid_sources[0x4b]	111266	1			T11	4		T13	2		T14	6
valid_sources[0x4c]	212532	1			T11	1		T16	3		T73	2
valid_sources[0x4d]	114908	1			T2	1		T16	3		T18	1
valid_sources[0x4e]	118714	1			T2	3		T16	1		T17	5
valid_sources[0x4f]	116694	1			T13	5		T16	3		T17	2
valid_sources[0x50]	118760	1			T11	7		T2	1		T13	43
valid_sources[0x51]	116297	1			T11	4		T12	84		T13	27
valid_sources[0x52]	113493	1			T11	5		T2	2		T13	59
valid_sources[0x53]	114436	1			T11	10		T2	1		T16	3
valid_sources[0x54]	114148	1			T1	1		T2	1		T16	2
valid_sources[0x55]	115938	1			T2	1		T13	1		T4	7
valid_sources[0x56]	117715	1			T11	9		T13	12		T16	2
valid_sources[0x57]	111309	1			T11	5		T2	1		T16	2
valid_sources[0x58]	112536	1			T13	10		T16	3		T73	2
valid_sources[0x59]	126588	1			T13	6		T16	4		T17	3
valid_sources[0x5a]	120988	1			T11	12		T2	1		T13	3
valid_sources[0x5b]	115510	1			T13	3		T16	2		T17	3
valid_sources[0x5c]	120909	1			T16	4		T17	11		T4	3
valid_sources[0x5d]	120079	1			T2	1		T13	10		T16	3
valid_sources[0x5e]	124080	1			T13	23		T16	1		T18	2
valid_sources[0x5f]	129186	1			T13	31		T16	2		T17	3
valid_sources[0x60]	122117	1			T2	1		T13	25		T16	3
valid_sources[0x61]	112305	1			T1	1		T2	1		T16	3
valid_sources[0x62]	117125	1			T2	1		T16	2		T17	3
valid_sources[0x63]	121122	1			T2	3		T12	7		T16	3
valid_sources[0x64]	118846	1			T11	4		T16	2		T17	2
valid_sources[0x65]	113691	1			T11	4		T16	1		T17	1
valid_sources[0x66]	118466	1			T11	9		T2	1		T12	10
valid_sources[0x67]	115344	1			T2	1		T16	3		T17	6
valid_sources[0x68]	117890	1			T2	2		T13	12		T16	2
valid_sources[0x69]	119609	1			T11	1		T13	36		T16	2
valid_sources[0x6a]	118892	1			T2	1		T16	5		T17	1
valid_sources[0x6b]	115714	1			T11	2		T13	6		T16	1
valid_sources[0x6c]	111457	1			T11	4		T2	3		T15	9
valid_sources[0x6d]	188159	1			T13	15		T16	1		T20	1
valid_sources[0x6e]	120490	1			T1	1		T2	1		T16	3
valid_sources[0x6f]	139465	1			T11	1		T13	11		T16	2
valid_sources[0x70]	110008	1			T11	8		T2	1		T13	6
valid_sources[0x71]	114022	1			T2	2		T13	17		T16	1
valid_sources[0x72]	117206	1			T2	1		T16	1		T17	6
valid_sources[0x73]	123502	1			T2	1		T12	3		T13	10
valid_sources[0x74]	113477	1			T11	1		T2	1		T16	5
valid_sources[0x75]	118775	1			T1	5		T13	74		T16	1
valid_sources[0x76]	119130	1			T2	1		T16	4		T17	4
valid_sources[0x77]	123150	1			T11	2		T2	1		T13	15
valid_sources[0x78]	117608	1			T2	3		T13	8		T16	2
valid_sources[0x79]	115663	1			T1	3		T11	11		T2	1
valid_sources[0x7a]	122612	1			T1	1		T11	7		T16	1
valid_sources[0x7b]	108669	1			T2	1		T16	1		T17	9
valid_sources[0x7c]	112671	1			T2	1		T16	2		T17	5
valid_sources[0x7d]	112927	1			T11	7		T2	2		T13	20
valid_sources[0x7e]	123368	1			T11	3		T16	1		T17	1
valid_sources[0x7f]	108177	1			T11	15		T2	1		T13	9
valid_sources[0x80]	115899	1			T11	7		T13	2		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7118938

1

T1

17

T11

155

T2

58

values[0x0]

all_enables

biggest_size

9330432

1

T1

19

T11

258

T2

55

values[0x1]

all_enables

biggest_size

9332732

1

T1

17

T11

245

T2

46