Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	321809707	0	0	0
ctrl_en_input_filter_rd_A	321809707	485068	0	0
intr_ctrl_en_falling_rd_A	321809707	515815	0	0
intr_ctrl_en_lvlhigh_rd_A	321809707	486023	0	0
intr_ctrl_en_lvllow_rd_A	321809707	515765	0	0
intr_ctrl_en_rising_rd_A	321809707	483606	0	0
intr_enable_rd_A	321809707	484524	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	485068	0	0
T1	1379	15	0	0
T2	2585	18	0	0
T3	0	53	0	0
T4	0	113	0	0
T5	0	93	0	0
T6	0	43	0	0
T7	0	6	0	0
T8	0	20	0	0
T9	0	2	0	0
T10	0	147	0	0
T11	2863	0	0	0
T12	1936	0	0	0
T13	5587	0	0	0
T14	1363	0	0	0
T15	1043	0	0	0
T16	4994	0	0	0
T17	8582	0	0	0
T18	2414	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	515815	0	0
T1	1379	11	0	0
T2	2585	32	0	0
T3	0	89	0	0
T4	0	122	0	0
T5	0	64	0	0
T6	0	36	0	0
T7	0	8	0	0
T8	0	24	0	0
T9	0	5	0	0
T11	2863	0	0	0
T12	1936	0	0	0
T13	5587	0	0	0
T14	1363	0	0	0
T15	1043	0	0	0
T16	4994	0	0	0
T17	8582	0	0	0
T18	2414	0	0	0
T19	0	25	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	486023	0	0
T1	1379	11	0	0
T2	2585	8	0	0
T3	0	63	0	0
T4	0	127	0	0
T5	0	61	0	0
T6	0	48	0	0
T7	0	7	0	0
T8	0	31	0	0
T9	0	7	0	0
T11	2863	0	0	0
T12	1936	0	0	0
T13	5587	0	0	0
T14	1363	0	0	0
T15	1043	0	0	0
T16	4994	0	0	0
T17	8582	0	0	0
T18	2414	0	0	0
T19	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	515765	0	0
T1	1379	17	0	0
T2	2585	17	0	0
T3	0	73	0	0
T4	0	128	0	0
T5	0	106	0	0
T6	0	18	0	0
T7	0	4	0	0
T8	0	12	0	0
T9	0	4	0	0
T11	2863	0	0	0
T12	1936	0	0	0
T13	5587	0	0	0
T14	1363	0	0	0
T15	1043	0	0	0
T16	4994	0	0	0
T17	8582	0	0	0
T18	2414	0	0	0
T19	0	5	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	483606	0	0
T1	1379	7	0	0
T2	2585	23	0	0
T3	0	51	0	0
T4	0	111	0	0
T5	0	45	0	0
T6	0	41	0	0
T7	0	8	0	0
T8	0	12	0	0
T9	0	11	0	0
T11	2863	0	0	0
T12	1936	0	0	0
T13	5587	0	0	0
T14	1363	0	0	0
T15	1043	0	0	0
T16	4994	0	0	0
T17	8582	0	0	0
T18	2414	0	0	0
T19	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	484524	0	0
T1	1379	6	0	0
T2	2585	24	0	0
T3	0	85	0	0
T4	0	134	0	0
T5	0	114	0	0
T6	0	34	0	0
T7	0	9	0	0
T8	0	35	0	0
T9	0	2	0	0
T11	2863	0	0	0
T12	1936	0	0	0
T13	5587	0	0	0
T14	1363	0	0	0
T15	1043	0	0	0
T16	4994	0	0	0
T17	8582	0	0	0
T18	2414	0	0	0
T19	0	8	0	0