Unified Coverage Report :: Module :: gpio_reg_top

Module : gpio_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	98.54			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.63	100.00	98.54			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	98.54			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	97.69	98.24	100.00		98.95	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_en_input_filter	100.00	100.00	100.00			100.00
u_data_in	67.59	77.78	50.00			75.00
u_direct_oe	100.00	100.00
u_direct_out	100.00	100.00
u_intr_ctrl_en_falling	100.00	100.00	100.00			100.00
u_intr_ctrl_en_lvlhigh	100.00	100.00	100.00			100.00
u_intr_ctrl_en_lvllow	100.00	100.00	100.00			100.00
u_intr_ctrl_en_rising	100.00	100.00	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_masked_oe_lower_data	100.00	100.00
u_masked_oe_lower_mask	75.00	75.00
u_masked_oe_upper_data	100.00	100.00
u_masked_oe_upper_mask	75.00	75.00
u_masked_out_lower_data	100.00	100.00
u_masked_out_lower_mask	66.67	66.67
u_masked_out_upper_data	100.00	100.00
u_masked_out_upper_mask	66.67	66.67
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : gpio_reg_top

	Line No.	Total	Covered	Percent
TOTAL		129	129	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
ALWAYS	640	17	17	100.00
CONT_ASSIGN	659	1	1	100.00
ALWAYS	663	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	692	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
ALWAYS	745	17	17	100.00
ALWAYS	766	22	22	100.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	856	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
244	1	1
258	1	1
264	1	1
278	1	1
312	1	1
326	1	1
332	1	1
347	1	1
363	1	1
369	1	1
384	1	1
400	1	1
406	1	1
420	1	1
426	1	1
441	1	1
457	1	1
463	1	1
478	1	1
494	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
652	1	1
653	1	1
654	1	1
655	1	1
656	1	1
659	1	1
663	1	1
683	1	1
685	1	1
686	1	1
688	1	1
689	1	1
691	1	1
692	1	1
694	1	1
695	1	1
696	1	1
698	1	1
699	1	1
700	1	1
702	1	1
704	1	1
705	1	1
706	1	1
708	1	1
710	1	1
711	1	1
712	1	1
714	1	1
715	1	1
716	1	1
718	1	1
720	1	1
721	1	1
722	1	1
724	1	1
726	1	1
727	1	1
729	1	1
730	1	1
732	1	1
733	1	1
735	1	1
736	1	1
738	1	1
739	1	1
741	1	1
745	1	1
746	1	1
747	1	1
748	1	1
749	1	1
750	1	1
751	1	1
752	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
758	1	1
759	1	1
760	1	1
761	1	1
766	1	1
767	1	1
769	1	1
773	1	1
777	1	1
781	1	1
785	1	1
789	1	1
793	1	1
794	1	1
798	1	1
799	1	1
803	1	1
807	1	1
808	1	1
812	1	1
813	1	1
817	1	1
821	1	1
825	1	1
829	1	1
833	1	1
847		unreachable
855	1	1
856	1	1

---

Cond Coverage for Module : gpio_reg_top

	Total	Covered	Percent
Conditions	205	202	98.54
Logical	205	202	98.54
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Not Covered
1	1	Covered	T1,T11,T2

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T4,T22,T23

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T11,T2
0	0	1	Covered	T24,T25,T26
0	1	0	Covered	T4,T22,T23
1	0	0	Covered	T4,T22,T23

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T11,T2
0	0	1	Covered	T4,T22,T23
0	1	0	Covered	T11,T12,T16
1	0	0	Not Covered

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T11,T2
1	1	Not Covered

 LINE       641
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       642
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       643
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       644
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       645
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DATA_IN_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       646
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DIRECT_OUT_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       647
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OUT_LOWER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       648
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OUT_UPPER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       649
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DIRECT_OE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       650
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OE_LOWER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       651
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OE_UPPER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       652
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_RISING_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       653
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_FALLING_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       654
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       655
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_LVLLOW_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       656
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_CTRL_EN_INPUT_FILTER_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       659
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T2

 LINE       659
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T2
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2

 LINE       663
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T12,T16

 LINE       663
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T11,T12,T13
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T1,T11,T2
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T11,T2,T12
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T11,T12,T13
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T1,T11,T12
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T11,T2
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T11,T2,T12
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T11,T2,T12
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T11,T12
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T11,T12,T16

 LINE       663
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T12,T16

 LINE       663
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T12

 LINE       663
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T2,T12

 LINE       663
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T2,T12

 LINE       663
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T11,T2,T12
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T12

 LINE       663
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T12,T13

 LINE       663
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T2,T12

 LINE       663
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T1,T11,T2

 LINE       663
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T2
1	0	Covered	T1,T11,T2
1	1	Covered	T11,T12,T13

 LINE       683
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T13,T20,T21

 LINE       686
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T12,T16
1	1	1	Covered	T1,T11,T2

 LINE       689
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T20,T21,T27

 LINE       692
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T1,T11,T2

 LINE       695
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T4,T28,T29
1	1	1	Covered	T1,T11,T2

 LINE       696
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T1,T11,T2

 LINE       699
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T23,T29,T30
1	1	1	Covered	T1,T11,T2

 LINE       700
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T27,T31,T32

 LINE       705
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T23,T33,T34
1	1	1	Covered	T1,T11,T2

 LINE       706
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T27,T31,T32

 LINE       711
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T23,T35,T36
1	1	1	Covered	T1,T11,T2

 LINE       712
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T1,T11,T2

 LINE       715
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T4,T35,T37
1	1	1	Covered	T1,T11,T2

 LINE       716
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T12,T16
1	1	1	Covered	T27,T31,T32

 LINE       721
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T4,T22,T38
1	1	1	Covered	T1,T11,T2

 LINE       722
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T27,T31,T32

 LINE       727
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T1,T11,T2

 LINE       730
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T16,T17,T4
1	1	1	Covered	T1,T11,T2

 LINE       733
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T17,T18,T4
1	1	1	Covered	T1,T11,T2

 LINE       736
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T11,T16,T17
1	1	1	Covered	T1,T11,T2

 LINE       739
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T2
1	0	1	Covered	T1,T11,T2
1	1	0	Covered	T17,T18,T39
1	1	1	Covered	T1,T11,T2

---

Branch Coverage for Module : gpio_reg_top

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	659	2	2	100.00
IF	71	3	3	100.00
CASE	767	17	17	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	659	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T2
0	Covered	T1,T11,T2

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T2
0	1	Covered	T4,T22,T23
0	0	Covered	T1,T11,T2

	LineNo.	Expression
-1-:	767	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T11,T2
addr_hit[1]	Covered	T1,T11,T2
addr_hit[2]	Covered	T1,T11,T2
addr_hit[3]	Covered	T1,T11,T2
addr_hit[4]	Covered	T1,T11,T2
addr_hit[5]	Covered	T1,T11,T2
addr_hit[6]	Covered	T1,T11,T2
addr_hit[7]	Covered	T1,T11,T2
addr_hit[8]	Covered	T1,T11,T2
addr_hit[9]	Covered	T1,T11,T2
addr_hit[10]	Covered	T1,T11,T2
addr_hit[11]	Covered	T1,T11,T2
addr_hit[12]	Covered	T1,T11,T2
addr_hit[13]	Covered	T1,T11,T2
addr_hit[14]	Covered	T1,T11,T2
addr_hit[15]	Covered	T1,T11,T2
default	Covered	T1,T2,T13

---

Assert Coverage for Module : gpio_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	321809707	23025742	0	0
reAfterRv	321809707	23025696	0	0
rePulse	321809707	10115609	0	0
wePulse	321809707	12910087	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	23025742	0	0
T1	1379	34	0	0
T2	2585	79	0	0
T11	2863	114	0	0
T12	1936	84	0	0
T13	5587	2306	0	0
T14	1363	36	0	0
T15	1043	55	0	0
T16	4994	35	0	0
T17	8582	35	0	0
T18	2414	14	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	23025696	0	0
T1	1379	34	0	0
T2	2585	78	0	0
T11	2863	114	0	0
T12	1936	84	0	0
T13	5587	2306	0	0
T14	1363	36	0	0
T15	1043	55	0	0
T16	4994	35	0	0
T17	8582	35	0	0
T18	2414	14	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	10115609	0	0
T1	1379	24	0	0
T2	2585	53	0	0
T11	2863	70	0	0
T12	1936	63	0	0
T13	5587	1154	0	0
T14	1363	16	0	0
T15	1043	26	0	0
T16	4994	1	0	0
T17	8582	1	0	0
T18	2414	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	321809707	12910087	0	0
T1	1379	10	0	0
T2	2585	25	0	0
T11	2863	44	0	0
T12	1936	21	0	0
T13	5587	1152	0	0
T14	1363	20	0	0
T15	1043	29	0	0
T16	4994	34	0	0
T17	8582	34	0	0
T18	2414	13	0	0