Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5821349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27396104

1

T21

2473

T1

233

T11

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12919665	1			T21	1730		T1	121		T11	11
values[0x0]	9951169	1			T21	884		T1	59		T11	8
values[0x1]	10346619	1			T21	843		T1	53		T11	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4435143	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28782310

1

T21

2652

T1

233

T11

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	127194	1			T21	34		T16	1		T19	2
valid_sources[0x01]	121087	1			T21	29		T16	1		T25	3
valid_sources[0x02]	124307	1			T21	12		T12	2		T25	2
valid_sources[0x03]	114212	1			T21	14		T1	8		T17	2
valid_sources[0x04]	129996	1			T21	12		T1	3		T16	2
valid_sources[0x05]	121980	1			T21	1		T1	3		T16	7
valid_sources[0x06]	123519	1			T21	9		T73	1		T22	3
valid_sources[0x07]	125673	1			T13	1		T16	1		T25	1
valid_sources[0x08]	120657	1			T21	26		T1	6		T11	1
valid_sources[0x09]	124943	1			T21	21		T16	2		T17	1
valid_sources[0x0a]	114356	1			T21	5		T16	4		T17	1
valid_sources[0x0b]	118642	1			T21	16		T1	2		T16	1
valid_sources[0x0c]	128312	1			T21	11		T14	1		T16	2
valid_sources[0x0d]	115970	1			T21	27		T17	1		T25	3
valid_sources[0x0e]	133136	1			T21	5		T1	11		T16	2
valid_sources[0x0f]	119851	1			T21	6		T16	1		T102	2
valid_sources[0x10]	125818	1			T21	16		T13	1		T16	1
valid_sources[0x11]	124406	1			T21	13		T16	1		T25	2
valid_sources[0x12]	130024	1			T21	11		T1	7		T16	1
valid_sources[0x13]	122028	1			T21	10		T16	3		T17	1
valid_sources[0x14]	126488	1			T21	19		T13	2		T16	2
valid_sources[0x15]	121741	1			T21	16		T11	5		T16	3
valid_sources[0x16]	118517	1			T21	24		T1	1		T16	2
valid_sources[0x17]	123195	1			T21	15		T1	1		T16	3
valid_sources[0x18]	116394	1			T21	8		T13	1		T16	2
valid_sources[0x19]	162054	1			T21	20		T16	1		T17	2
valid_sources[0x1a]	118515	1			T21	13		T1	1		T13	1
valid_sources[0x1b]	133671	1			T21	24		T1	6		T16	1
valid_sources[0x1c]	120561	1			T21	11		T16	2		T17	1
valid_sources[0x1d]	122278	1			T21	15		T11	8		T16	5
valid_sources[0x1e]	119527	1			T21	5		T12	2		T13	3
valid_sources[0x1f]	121700	1			T21	5		T17	1		T2	6
valid_sources[0x20]	128628	1			T21	11		T25	1		T2	1
valid_sources[0x21]	118527	1			T21	8		T1	1		T16	6
valid_sources[0x22]	125927	1			T21	23		T16	1		T17	1
valid_sources[0x23]	126394	1			T21	13		T16	2		T25	2
valid_sources[0x24]	136245	1			T21	19		T1	10		T16	1
valid_sources[0x25]	129860	1			T21	20		T16	1		T17	1
valid_sources[0x26]	126835	1			T21	18		T1	4		T13	1
valid_sources[0x27]	120304	1			T21	18		T16	4		T25	1
valid_sources[0x28]	125889	1			T21	5		T16	3		T33	1
valid_sources[0x29]	123352	1			T21	15		T16	2		T17	1
valid_sources[0x2a]	129187	1			T21	10		T16	4		T25	1
valid_sources[0x2b]	121366	1			T21	4		T14	2		T16	2
valid_sources[0x2c]	122139	1			T21	9		T16	4		T25	3
valid_sources[0x2d]	127335	1			T21	12		T1	2		T19	3
valid_sources[0x2e]	129300	1			T21	23		T1	8		T16	2
valid_sources[0x2f]	119522	1			T21	10		T16	1		T25	4
valid_sources[0x30]	343817	1			T21	13		T16	3		T25	3
valid_sources[0x31]	119667	1			T21	7		T11	4		T16	5
valid_sources[0x32]	126932	1			T21	11		T14	2		T16	2
valid_sources[0x33]	134079	1			T21	18		T1	1		T16	1
valid_sources[0x34]	123561	1			T21	7		T14	1		T16	2
valid_sources[0x35]	120950	1			T21	15		T12	1		T16	1
valid_sources[0x36]	123242	1			T21	8		T1	3		T12	1
valid_sources[0x37]	114129	1			T21	14		T13	1		T16	3
valid_sources[0x38]	131222	1			T21	14		T16	3		T25	1
valid_sources[0x39]	127689	1			T21	7		T16	3		T73	2
valid_sources[0x3a]	132338	1			T21	16		T16	2		T25	1
valid_sources[0x3b]	118589	1			T21	29		T13	2		T14	2
valid_sources[0x3c]	122407	1			T21	9		T1	1		T16	1
valid_sources[0x3d]	116851	1			T21	35		T16	2		T25	2
valid_sources[0x3e]	120173	1			T21	13		T16	1		T22	10
valid_sources[0x3f]	250356	1			T21	8		T1	6		T13	1
valid_sources[0x40]	121231	1			T21	16		T25	1		T118	1
valid_sources[0x41]	127565	1			T21	8		T16	3		T17	1
valid_sources[0x42]	123900	1			T21	11		T12	1		T16	1
valid_sources[0x43]	121276	1			T21	28		T13	1		T16	1
valid_sources[0x44]	119552	1			T21	17		T1	3		T16	1
valid_sources[0x45]	123710	1			T21	4		T16	3		T25	2
valid_sources[0x46]	125018	1			T21	13		T16	2		T17	1
valid_sources[0x47]	124034	1			T21	34		T25	3		T23	20
valid_sources[0x48]	119411	1			T21	11		T16	3		T73	2
valid_sources[0x49]	119893	1			T21	7		T16	1		T18	6
valid_sources[0x4a]	186624	1			T21	14		T17	2		T25	2
valid_sources[0x4b]	129857	1			T21	29		T2	5		T100	1
valid_sources[0x4c]	232984	1			T21	13		T12	1		T13	1
valid_sources[0x4d]	132965	1			T21	18		T13	1		T17	1
valid_sources[0x4e]	127591	1			T21	9		T16	4		T25	3
valid_sources[0x4f]	121406	1			T21	19		T1	2		T16	2
valid_sources[0x50]	120823	1			T21	11		T16	1		T17	2
valid_sources[0x51]	201984	1			T21	10		T1	5		T16	1
valid_sources[0x52]	125961	1			T21	11		T16	1		T2	1
valid_sources[0x53]	121917	1			T21	17		T16	1		T18	7
valid_sources[0x54]	126921	1			T21	1		T13	1		T16	2
valid_sources[0x55]	130391	1			T21	20		T16	4		T25	1
valid_sources[0x56]	119440	1			T21	14		T17	1		T25	5
valid_sources[0x57]	124146	1			T21	17		T1	5		T16	4
valid_sources[0x58]	127020	1			T21	17		T1	13		T16	1
valid_sources[0x59]	203698	1			T21	13		T1	5		T16	1
valid_sources[0x5a]	127567	1			T21	21		T13	1		T16	4
valid_sources[0x5b]	135244	1			T21	23		T25	2		T51	1
valid_sources[0x5c]	119621	1			T21	5		T16	3		T73	1
valid_sources[0x5d]	117636	1			T21	5		T13	1		T16	2
valid_sources[0x5e]	125328	1			T21	30		T1	9		T13	1
valid_sources[0x5f]	123961	1			T21	15		T11	1		T16	2
valid_sources[0x60]	126351	1			T21	9		T12	1		T16	6
valid_sources[0x61]	122925	1			T21	5		T16	1		T51	1
valid_sources[0x62]	125927	1			T21	22		T16	1		T17	1
valid_sources[0x63]	120983	1			T21	15		T1	1		T16	3
valid_sources[0x64]	118145	1			T21	19		T16	1		T25	1
valid_sources[0x65]	122624	1			T21	12		T1	4		T16	3
valid_sources[0x66]	132964	1			T21	15		T12	1		T13	1
valid_sources[0x67]	123179	1			T21	11		T17	2		T19	7
valid_sources[0x68]	127477	1			T21	12		T13	1		T16	1
valid_sources[0x69]	119886	1			T21	21		T12	3		T16	2
valid_sources[0x6a]	129337	1			T21	18		T16	3		T17	1
valid_sources[0x6b]	125049	1			T21	11		T16	1		T17	4
valid_sources[0x6c]	158047	1			T21	19		T16	1		T17	1
valid_sources[0x6d]	139432	1			T21	10		T16	2		T25	2
valid_sources[0x6e]	160918	1			T21	20		T12	1		T16	1
valid_sources[0x6f]	189402	1			T21	6		T16	3		T19	4
valid_sources[0x70]	126046	1			T21	18		T51	1		T102	1
valid_sources[0x71]	124063	1			T21	13		T13	1		T16	5
valid_sources[0x72]	117711	1			T21	7		T16	1		T25	3
valid_sources[0x73]	131048	1			T21	7		T13	1		T16	1
valid_sources[0x74]	120770	1			T21	13		T14	4		T16	3
valid_sources[0x75]	121795	1			T21	10		T3	2		T24	1
valid_sources[0x76]	119196	1			T21	4		T16	2		T17	2
valid_sources[0x77]	133679	1			T21	19		T13	1		T16	3
valid_sources[0x78]	123126	1			T21	17		T12	1		T16	2
valid_sources[0x79]	122499	1			T21	8		T13	1		T16	6
valid_sources[0x7a]	120864	1			T21	22		T16	3		T25	3
valid_sources[0x7b]	123604	1			T21	21		T16	3		T17	2
valid_sources[0x7c]	125658	1			T21	10		T1	2		T16	2
valid_sources[0x7d]	120421	1			T21	6		T17	1		T25	1
valid_sources[0x7e]	127475	1			T21	15		T16	4		T2	12
valid_sources[0x7f]	131031	1			T16	3		T17	1		T25	1
valid_sources[0x80]	119618	1			T21	20		T16	4		T25	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7576673

1

T21

881

T1

121

T11

5

values[0x0]

all_enables

biggest_size

9911688

1

T21

829

T1

59

T11

8

values[0x1]

all_enables

biggest_size

9907743

1

T21

763

T1

53

T11

3