Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	322544010	0	0	0
ctrl_en_input_filter_rd_A	322544010	285190	0	0
intr_ctrl_en_falling_rd_A	322544010	303662	0	0
intr_ctrl_en_lvlhigh_rd_A	322544010	285626	0	0
intr_ctrl_en_lvllow_rd_A	322544010	304637	0	0
intr_ctrl_en_rising_rd_A	322544010	286047	0	0
intr_enable_rd_A	322544010	284056	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	285190	0	0
T1	2969	66	0	0
T2	0	16	0	0
T3	0	1	0	0
T4	0	33	0	0
T5	0	72	0	0
T6	0	39	0	0
T7	0	69	0	0
T8	0	25	0	0
T9	0	30	0	0
T10	0	9	0	0
T11	709	0	0	0
T12	1363	0	0	0
T13	1563	0	0	0
T14	1070	0	0	0
T15	1024	0	0	0
T16	2411	0	0	0
T17	1706	0	0	0
T18	1564	0	0	0
T19	1406	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	303662	0	0
T1	2969	26	0	0
T2	0	9	0	0
T3	0	9	0	0
T4	0	16	0	0
T5	0	39	0	0
T6	0	41	0	0
T7	0	97	0	0
T8	0	30	0	0
T9	0	29	0	0
T10	0	3	0	0
T11	709	0	0	0
T12	1363	0	0	0
T13	1563	0	0	0
T14	1070	0	0	0
T15	1024	0	0	0
T16	2411	0	0	0
T17	1706	0	0	0
T18	1564	0	0	0
T19	1406	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	285626	0	0
T1	2969	74	0	0
T3	0	6	0	0
T4	0	46	0	0
T5	0	86	0	0
T6	0	29	0	0
T7	0	72	0	0
T8	0	34	0	0
T9	0	26	0	0
T10	0	1	0	0
T11	709	0	0	0
T12	1363	0	0	0
T13	1563	0	0	0
T14	1070	0	0	0
T15	1024	0	0	0
T16	2411	0	0	0
T17	1706	0	0	0
T18	1564	0	0	0
T19	1406	0	0	0
T20	0	19	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	304637	0	0
T1	2969	28	0	0
T2	0	29	0	0
T3	0	1	0	0
T4	0	53	0	0
T5	0	74	0	0
T6	0	26	0	0
T7	0	71	0	0
T8	0	8	0	0
T9	0	62	0	0
T10	0	14	0	0
T11	709	0	0	0
T12	1363	0	0	0
T13	1563	0	0	0
T14	1070	0	0	0
T15	1024	0	0	0
T16	2411	0	0	0
T17	1706	0	0	0
T18	1564	0	0	0
T19	1406	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	286047	0	0
T1	2969	31	0	0
T2	0	7	0	0
T3	0	10	0	0
T4	0	50	0	0
T5	0	68	0	0
T6	0	29	0	0
T7	0	92	0	0
T8	0	81	0	0
T9	0	57	0	0
T10	0	4	0	0
T11	709	0	0	0
T12	1363	0	0	0
T13	1563	0	0	0
T14	1070	0	0	0
T15	1024	0	0	0
T16	2411	0	0	0
T17	1706	0	0	0
T18	1564	0	0	0
T19	1406	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322544010	284056	0	0
T1	2969	49	0	0
T2	0	2	0	0
T3	0	3	0	0
T4	0	12	0	0
T5	0	81	0	0
T6	0	41	0	0
T7	0	63	0	0
T8	0	47	0	0
T9	0	7	0	0
T11	709	0	0	0
T12	1363	0	0	0
T13	1563	0	0	0
T14	1070	0	0	0
T15	1024	14	0	0
T16	2411	0	0	0
T17	1706	0	0	0
T18	1564	0	0	0
T19	1406	0	0	0