Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6132704	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29397894

1

T23

17

T20

13

T21

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13683565	1			T23	11		T20	9		T21	29
values[0x0]	10697116	1			T23	7		T20	5		T21	14
values[0x1]	11149917	1			T23	4		T20	5		T21	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4659995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30870603

1

T23

18

T20

15

T21

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	136330	1			T12	2		T14	2		T2	1
valid_sources[0x01]	130564	1			T3	16		T80	2		T36	2
valid_sources[0x02]	129914	1			T13	2		T2	3		T3	20
valid_sources[0x03]	134968	1			T1	3		T11	42		T15	9
valid_sources[0x04]	146726	1			T11	10		T14	2		T15	12
valid_sources[0x05]	139626	1			T1	1		T11	36		T2	1
valid_sources[0x06]	134362	1			T15	2		T3	8		T79	60
valid_sources[0x07]	129661	1			T2	2		T72	1		T3	12
valid_sources[0x08]	139118	1			T2	1		T3	7		T28	5
valid_sources[0x09]	152476	1			T12	3		T14	4		T15	1
valid_sources[0x0a]	172271	1			T14	1		T15	4		T2	2
valid_sources[0x0b]	133560	1			T1	1		T15	1		T2	2
valid_sources[0x0c]	130029	1			T12	1		T2	2		T72	7
valid_sources[0x0d]	140959	1			T1	3		T15	5		T2	1
valid_sources[0x0e]	141236	1			T72	1		T74	1		T3	11
valid_sources[0x0f]	137843	1			T21	3		T14	1		T2	2
valid_sources[0x10]	128820	1			T15	11		T2	1		T3	2
valid_sources[0x11]	135767	1			T15	2		T2	3		T18	1
valid_sources[0x12]	131736	1			T15	1		T3	7		T27	1
valid_sources[0x13]	144797	1			T1	1		T11	9		T2	2
valid_sources[0x14]	131971	1			T23	1		T14	2		T2	2
valid_sources[0x15]	125733	1			T1	1		T14	1		T15	6
valid_sources[0x16]	134435	1			T23	1		T1	1		T15	4
valid_sources[0x17]	131518	1			T2	2		T3	4		T36	1
valid_sources[0x18]	137245	1			T14	3		T2	1		T3	4
valid_sources[0x19]	137618	1			T11	20		T74	14		T3	11
valid_sources[0x1a]	144886	1			T1	1		T14	6		T2	1
valid_sources[0x1b]	135500	1			T1	1		T15	4		T3	6
valid_sources[0x1c]	134240	1			T1	4		T11	12		T14	1
valid_sources[0x1d]	131173	1			T14	1		T15	3		T2	1
valid_sources[0x1e]	130040	1			T1	1		T15	1		T2	3
valid_sources[0x1f]	132544	1			T20	3		T14	1		T15	3
valid_sources[0x20]	125932	1			T1	1		T14	3		T2	1
valid_sources[0x21]	142390	1			T1	1		T13	1		T14	2
valid_sources[0x22]	146218	1			T1	3		T12	45		T2	1
valid_sources[0x23]	140603	1			T1	1		T15	1		T2	1
valid_sources[0x24]	134992	1			T12	5		T3	4		T81	1
valid_sources[0x25]	132364	1			T14	3		T15	1		T2	1
valid_sources[0x26]	135323	1			T15	6		T2	1		T3	6
valid_sources[0x27]	135107	1			T14	4		T3	10		T36	3
valid_sources[0x28]	130204	1			T11	9		T3	18		T28	2
valid_sources[0x29]	135817	1			T23	1		T1	1		T15	2
valid_sources[0x2a]	129518	1			T1	2		T2	2		T3	7
valid_sources[0x2b]	176620	1			T14	2		T15	3		T2	2
valid_sources[0x2c]	128941	1			T14	4		T15	1		T2	2
valid_sources[0x2d]	140188	1			T11	20		T14	3		T15	1
valid_sources[0x2e]	137722	1			T1	1		T15	2		T2	3
valid_sources[0x2f]	138584	1			T1	2		T3	18		T36	2
valid_sources[0x30]	126031	1			T12	66		T15	10		T2	1
valid_sources[0x31]	196970	1			T1	3		T2	3		T3	5
valid_sources[0x32]	134012	1			T15	8		T2	1		T3	10
valid_sources[0x33]	136511	1			T1	1		T15	1		T2	1
valid_sources[0x34]	131993	1			T1	3		T12	3		T2	2
valid_sources[0x35]	128557	1			T21	6		T15	4		T3	5
valid_sources[0x36]	139296	1			T20	3		T12	3		T2	2
valid_sources[0x37]	126199	1			T1	2		T14	1		T2	2
valid_sources[0x38]	146923	1			T11	20		T14	3		T2	3
valid_sources[0x39]	123102	1			T21	3		T15	2		T3	7
valid_sources[0x3a]	130557	1			T11	20		T15	3		T3	14
valid_sources[0x3b]	136285	1			T1	1		T14	2		T15	4
valid_sources[0x3c]	132950	1			T14	1		T16	3		T2	1
valid_sources[0x3d]	141736	1			T2	2		T74	8		T3	4
valid_sources[0x3e]	134594	1			T15	3		T3	22		T27	1
valid_sources[0x3f]	127443	1			T1	3		T11	1		T13	1
valid_sources[0x40]	135981	1			T14	2		T15	7		T2	1
valid_sources[0x41]	137354	1			T1	1		T2	2		T17	5
valid_sources[0x42]	134273	1			T23	1		T12	1		T13	1
valid_sources[0x43]	130964	1			T15	2		T2	1		T3	9
valid_sources[0x44]	125283	1			T14	1		T74	21		T3	19
valid_sources[0x45]	136320	1			T1	1		T14	2		T2	1
valid_sources[0x46]	136623	1			T15	2		T2	1		T18	1
valid_sources[0x47]	140258	1			T3	19		T36	5		T28	2
valid_sources[0x48]	133370	1			T2	1		T3	13		T19	1
valid_sources[0x49]	134021	1			T1	2		T14	4		T15	6
valid_sources[0x4a]	132703	1			T1	3		T3	18		T19	1
valid_sources[0x4b]	135771	1			T3	16		T97	1		T28	1
valid_sources[0x4c]	134073	1			T21	10		T15	2		T2	2
valid_sources[0x4d]	139751	1			T1	2		T14	1		T15	4
valid_sources[0x4e]	129602	1			T23	1		T1	1		T12	9
valid_sources[0x4f]	133044	1			T2	1		T3	7		T36	1
valid_sources[0x50]	140072	1			T14	1		T15	1		T2	1
valid_sources[0x51]	138111	1			T1	1		T14	3		T15	7
valid_sources[0x52]	133255	1			T1	1		T14	1		T2	2
valid_sources[0x53]	133864	1			T15	1		T74	6		T3	4
valid_sources[0x54]	131639	1			T23	3		T1	1		T13	1
valid_sources[0x55]	131716	1			T11	8		T14	4		T3	18
valid_sources[0x56]	141957	1			T1	2		T12	4		T15	1
valid_sources[0x57]	137784	1			T21	1		T15	3		T2	2
valid_sources[0x58]	142413	1			T21	3		T1	3		T13	1
valid_sources[0x59]	129946	1			T1	2		T11	5		T15	2
valid_sources[0x5a]	127236	1			T1	1		T15	1		T2	2
valid_sources[0x5b]	125013	1			T2	1		T3	8		T19	1
valid_sources[0x5c]	255193	1			T13	1		T17	10		T3	8
valid_sources[0x5d]	129358	1			T1	1		T15	5		T2	2
valid_sources[0x5e]	304967	1			T1	1		T15	7		T2	1
valid_sources[0x5f]	134969	1			T1	1		T15	7		T72	3
valid_sources[0x60]	142567	1			T14	3		T2	1		T17	33
valid_sources[0x61]	136629	1			T2	3		T3	16		T97	7
valid_sources[0x62]	133175	1			T1	1		T15	2		T2	2
valid_sources[0x63]	134619	1			T1	1		T14	6		T15	1
valid_sources[0x64]	130383	1			T1	1		T15	4		T2	5
valid_sources[0x65]	121592	1			T1	1		T15	7		T3	17
valid_sources[0x66]	133671	1			T1	2		T15	1		T18	1
valid_sources[0x67]	138265	1			T1	2		T15	1		T17	17
valid_sources[0x68]	129667	1			T1	2		T15	4		T2	1
valid_sources[0x69]	137047	1			T1	1		T14	1		T15	1
valid_sources[0x6a]	129374	1			T1	2		T12	7		T15	5
valid_sources[0x6b]	126948	1			T2	1		T3	13		T27	1
valid_sources[0x6c]	127199	1			T1	2		T15	2		T3	11
valid_sources[0x6d]	138602	1			T11	29		T14	3		T16	5
valid_sources[0x6e]	133454	1			T15	3		T16	5		T2	1
valid_sources[0x6f]	134046	1			T21	3		T1	1		T2	3
valid_sources[0x70]	125452	1			T1	2		T13	1		T15	1
valid_sources[0x71]	146074	1			T21	1		T11	9		T14	1
valid_sources[0x72]	137164	1			T20	1		T3	21		T19	1
valid_sources[0x73]	137289	1			T11	9		T14	1		T15	5
valid_sources[0x74]	128781	1			T1	1		T2	1		T3	6
valid_sources[0x75]	139237	1			T1	1		T15	3		T2	1
valid_sources[0x76]	133118	1			T1	1		T15	8		T3	5
valid_sources[0x77]	136248	1			T1	3		T15	10		T3	7
valid_sources[0x78]	160136	1			T1	1		T15	2		T74	3
valid_sources[0x79]	148352	1			T15	5		T2	1		T72	1
valid_sources[0x7a]	133269	1			T2	4		T74	7		T3	9
valid_sources[0x7b]	140397	1			T14	2		T15	2		T2	1
valid_sources[0x7c]	133311	1			T2	2		T3	3		T79	5
valid_sources[0x7d]	129024	1			T15	1		T2	2		T18	1
valid_sources[0x7e]	139344	1			T23	1		T3	12		T105	1
valid_sources[0x7f]	128106	1			T15	3		T2	1		T3	3
valid_sources[0x80]	139022	1			T1	1		T14	1		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8084700

1

T23

6

T20

4

T21

17

values[0x0]

all_enables

biggest_size

10652837

1

T23

7

T20

5

T21

14

values[0x1]

all_enables

biggest_size

10660357

1

T23

4

T20

4

T21

15