Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	357845451	0	0	0
ctrl_en_input_filter_rd_A	357845451	216255	0	0
intr_ctrl_en_falling_rd_A	357845451	224995	0	0
intr_ctrl_en_lvlhigh_rd_A	357845451	214839	0	0
intr_ctrl_en_lvllow_rd_A	357845451	225758	0	0
intr_ctrl_en_rising_rd_A	357845451	215143	0	0
intr_enable_rd_A	357845451	215019	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	216255	0	0
T1	2306	14	0	0
T2	3318	126	0	0
T3	0	516	0	0
T4	0	60	0	0
T5	0	41	0	0
T6	0	30	0	0
T7	0	37	0	0
T8	0	49	0	0
T9	0	15	0	0
T10	0	6	0	0
T11	5745	0	0	0
T12	2110	0	0	0
T13	1548	0	0	0
T14	4173	0	0	0
T15	7819	0	0	0
T16	1856	0	0	0
T17	3729	0	0	0
T18	790	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	224995	0	0
T1	2306	35	0	0
T2	3318	123	0	0
T3	0	462	0	0
T4	0	48	0	0
T5	0	38	0	0
T6	0	12	0	0
T7	0	42	0	0
T8	0	58	0	0
T9	0	3	0	0
T11	5745	0	0	0
T12	2110	0	0	0
T13	1548	0	0	0
T14	4173	0	0	0
T15	7819	0	0	0
T16	1856	0	0	0
T17	3729	0	0	0
T18	790	0	0	0
T19	0	7	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	214839	0	0
T1	2306	24	0	0
T2	0	100	0	0
T3	0	404	0	0
T4	0	64	0	0
T5	0	9	0	0
T6	0	42	0	0
T7	0	45	0	0
T8	0	16	0	0
T11	5745	0	0	0
T12	2110	0	0	0
T13	1548	0	0	0
T14	4173	0	0	0
T15	7819	0	0	0
T16	1856	0	0	0
T19	0	28	0	0
T20	1293	1	0	0
T21	1267	0	0	0
T22	890	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	225758	0	0
T1	2306	28	0	0
T2	0	106	0	0
T3	0	409	0	0
T4	0	69	0	0
T5	0	40	0	0
T6	0	6	0	0
T7	0	46	0	0
T8	0	55	0	0
T11	5745	0	0	0
T12	2110	0	0	0
T13	1548	0	0	0
T14	4173	0	0	0
T15	7819	0	0	0
T16	1856	0	0	0
T19	0	8	0	0
T20	1293	2	0	0
T21	1267	0	0	0
T22	890	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	215143	0	0
T1	2306	38	0	0
T2	0	111	0	0
T3	0	429	0	0
T4	0	71	0	0
T5	0	16	0	0
T6	0	45	0	0
T7	0	52	0	0
T8	0	65	0	0
T11	5745	0	0	0
T12	2110	0	0	0
T13	1548	0	0	0
T14	4173	0	0	0
T15	7819	0	0	0
T16	1856	0	0	0
T19	0	2	0	0
T20	1293	2	0	0
T21	1267	0	0	0
T22	890	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357845451	215019	0	0
T1	2306	22	0	0
T2	0	104	0	0
T3	0	433	0	0
T4	0	35	0	0
T5	0	1	0	0
T6	0	14	0	0
T7	0	56	0	0
T11	5745	0	0	0
T12	2110	0	0	0
T13	1548	10	0	0
T14	4173	0	0	0
T15	7819	0	0	0
T19	0	15	0	0
T20	1293	0	0	0
T21	1267	0	0	0
T22	890	0	0	0
T23	1111	3	0	0