Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6197062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30047340

1

T22

155

T23

239

T24

255

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13899794	1			T22	94		T23	119		T24	90
values[0x0]	10945623	1			T22	48		T23	65		T24	90
values[0x1]	11398985	1			T22	54		T23	55		T24	97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4701918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31542484

1

T22

168

T23

239

T24

262

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138985	1			T11	1		T12	7		T120	3
valid_sources[0x01]	142294	1			T12	16		T120	1		T2	1
valid_sources[0x02]	131496	1			T39	1		T30	5		T3	5
valid_sources[0x03]	137255	1			T24	1		T12	23		T120	12
valid_sources[0x04]	140589	1			T11	1		T120	1		T39	1
valid_sources[0x05]	135118	1			T22	14		T23	14		T12	3
valid_sources[0x06]	145402	1			T1	5		T11	3		T12	5
valid_sources[0x07]	133360	1			T30	7		T75	1		T35	1
valid_sources[0x08]	137262	1			T24	3		T11	1		T12	8
valid_sources[0x09]	137883	1			T16	3		T2	1		T39	1
valid_sources[0x0a]	131533	1			T11	1		T16	1		T2	3
valid_sources[0x0b]	125840	1			T24	1		T11	3		T12	13
valid_sources[0x0c]	137821	1			T11	2		T19	2		T25	1
valid_sources[0x0d]	134432	1			T23	9		T11	3		T12	4
valid_sources[0x0e]	131635	1			T24	3		T120	2		T2	1
valid_sources[0x0f]	126189	1			T11	1		T2	1		T39	1
valid_sources[0x10]	138809	1			T11	5		T2	3		T26	6
valid_sources[0x11]	255147	1			T24	1		T11	1		T39	1
valid_sources[0x12]	143363	1			T11	1		T16	4		T39	1
valid_sources[0x13]	129264	1			T11	9		T26	2		T30	1
valid_sources[0x14]	126854	1			T22	3		T23	6		T12	3
valid_sources[0x15]	135815	1			T18	8		T26	8		T3	1
valid_sources[0x16]	131946	1			T39	3		T3	3		T75	1
valid_sources[0x17]	137302	1			T19	2		T120	2		T26	1
valid_sources[0x18]	141629	1			T24	2		T11	1		T12	1
valid_sources[0x19]	136354	1			T24	15		T1	5		T39	1
valid_sources[0x1a]	142935	1			T13	19		T120	1		T39	1
valid_sources[0x1b]	141012	1			T19	1		T2	1		T39	2
valid_sources[0x1c]	135365	1			T11	2		T16	2		T39	1
valid_sources[0x1d]	140420	1			T24	1		T12	7		T25	1
valid_sources[0x1e]	144565	1			T22	8		T23	15		T11	2
valid_sources[0x1f]	145271	1			T11	3		T12	1		T19	1
valid_sources[0x20]	151093	1			T22	15		T11	2		T13	20
valid_sources[0x21]	124490	1			T11	2		T120	1		T3	1
valid_sources[0x22]	134951	1			T11	3		T12	1		T15	9
valid_sources[0x23]	142628	1			T24	4		T11	2		T39	1
valid_sources[0x24]	134332	1			T11	1		T16	1		T39	2
valid_sources[0x25]	132642	1			T22	13		T11	1		T2	1
valid_sources[0x26]	137060	1			T3	7		T34	8		T9	3
valid_sources[0x27]	128603	1			T18	101		T39	1		T30	1
valid_sources[0x28]	142459	1			T22	5		T12	4		T39	5
valid_sources[0x29]	128715	1			T24	1		T11	2		T2	1
valid_sources[0x2a]	144106	1			T23	10		T11	3		T39	1
valid_sources[0x2b]	145220	1			T24	4		T11	2		T2	1
valid_sources[0x2c]	129328	1			T11	1		T39	2		T26	12
valid_sources[0x2d]	130748	1			T24	5		T12	13		T26	7
valid_sources[0x2e]	144979	1			T15	9		T16	1		T39	1
valid_sources[0x2f]	131569	1			T22	9		T1	5		T11	5
valid_sources[0x30]	128257	1			T22	2		T12	25		T39	1
valid_sources[0x31]	138056	1			T11	1		T12	2		T120	2
valid_sources[0x32]	144815	1			T24	12		T1	22		T11	1
valid_sources[0x33]	129134	1			T12	3		T39	2		T26	1
valid_sources[0x34]	124435	1			T11	4		T39	1		T30	20
valid_sources[0x35]	139998	1			T12	2		T2	2		T75	7
valid_sources[0x36]	140715	1			T24	5		T12	4		T120	4
valid_sources[0x37]	139840	1			T23	2		T24	4		T11	1
valid_sources[0x38]	131746	1			T24	2		T1	5		T11	1
valid_sources[0x39]	127982	1			T23	12		T11	2		T39	1
valid_sources[0x3a]	128856	1			T24	2		T11	1		T16	2
valid_sources[0x3b]	137641	1			T23	28		T11	1		T2	1
valid_sources[0x3c]	132896	1			T2	1		T75	5		T35	1
valid_sources[0x3d]	133486	1			T11	3		T12	1		T39	2
valid_sources[0x3e]	136090	1			T11	1		T12	5		T13	20
valid_sources[0x3f]	124518	1			T24	8		T1	5		T11	3
valid_sources[0x40]	135696	1			T12	8		T39	2		T35	2
valid_sources[0x41]	145301	1			T23	2		T1	1		T12	4
valid_sources[0x42]	139315	1			T24	3		T11	1		T12	9
valid_sources[0x43]	151808	1			T22	17		T16	4		T2	1
valid_sources[0x44]	146701	1			T22	1		T24	1		T1	5
valid_sources[0x45]	143323	1			T24	2		T16	1		T30	2
valid_sources[0x46]	141919	1			T16	3		T120	3		T2	1
valid_sources[0x47]	147977	1			T26	4		T30	4		T35	2
valid_sources[0x48]	254158	1			T11	1		T120	7		T39	1
valid_sources[0x49]	134497	1			T24	5		T11	1		T16	6
valid_sources[0x4a]	137792	1			T22	5		T11	1		T12	2
valid_sources[0x4b]	139307	1			T1	5		T12	8		T16	2
valid_sources[0x4c]	140913	1			T24	2		T14	3		T2	1
valid_sources[0x4d]	129155	1			T24	1		T39	1		T26	1
valid_sources[0x4e]	146720	1			T24	3		T1	5		T11	1
valid_sources[0x4f]	130548	1			T24	1		T11	2		T12	9
valid_sources[0x50]	135609	1			T24	4		T11	3		T26	11
valid_sources[0x51]	124697	1			T11	1		T12	6		T16	2
valid_sources[0x52]	140853	1			T24	1		T39	1		T26	3
valid_sources[0x53]	147716	1			T12	5		T2	3		T39	1
valid_sources[0x54]	128274	1			T120	3		T2	1		T39	3
valid_sources[0x55]	137350	1			T24	4		T39	5		T75	1
valid_sources[0x56]	127593	1			T39	1		T26	12		T3	2
valid_sources[0x57]	140079	1			T11	1		T14	2		T30	5
valid_sources[0x58]	142495	1			T22	4		T16	2		T2	1
valid_sources[0x59]	190609	1			T11	1		T39	4		T3	3
valid_sources[0x5a]	143301	1			T23	10		T24	1		T11	3
valid_sources[0x5b]	140431	1			T11	1		T12	3		T39	2
valid_sources[0x5c]	136633	1			T25	1		T39	4		T26	1
valid_sources[0x5d]	140114	1			T11	3		T16	1		T19	1
valid_sources[0x5e]	134293	1			T11	1		T16	5		T19	2
valid_sources[0x5f]	147758	1			T16	1		T120	3		T2	1
valid_sources[0x60]	131457	1			T24	2		T11	2		T39	3
valid_sources[0x61]	139103	1			T39	1		T30	3		T75	3
valid_sources[0x62]	135421	1			T12	9		T16	1		T39	1
valid_sources[0x63]	134831	1			T11	2		T120	2		T26	1
valid_sources[0x64]	138628	1			T39	1		T3	4		T75	2
valid_sources[0x65]	135699	1			T22	4		T11	3		T2	1
valid_sources[0x66]	130777	1			T24	6		T2	3		T39	1
valid_sources[0x67]	131086	1			T24	3		T1	10		T12	20
valid_sources[0x68]	136330	1			T24	1		T11	3		T12	1
valid_sources[0x69]	122223	1			T16	2		T39	1		T26	2
valid_sources[0x6a]	147784	1			T11	1		T120	1		T2	2
valid_sources[0x6b]	146286	1			T22	3		T11	2		T12	1
valid_sources[0x6c]	133558	1			T12	4		T16	2		T120	7
valid_sources[0x6d]	144934	1			T11	2		T12	5		T14	2
valid_sources[0x6e]	129009	1			T12	3		T16	1		T2	1
valid_sources[0x6f]	139513	1			T11	1		T13	20		T39	1
valid_sources[0x70]	132282	1			T11	1		T39	2		T30	2
valid_sources[0x71]	132609	1			T24	2		T11	3		T14	5
valid_sources[0x72]	140121	1			T1	5		T39	5		T26	15
valid_sources[0x73]	139146	1			T16	1		T120	4		T39	1
valid_sources[0x74]	142938	1			T16	1		T39	4		T75	1
valid_sources[0x75]	136412	1			T11	2		T12	8		T120	7
valid_sources[0x76]	134680	1			T22	7		T11	3		T16	2
valid_sources[0x77]	136005	1			T16	1		T39	3		T3	1
valid_sources[0x78]	137359	1			T24	2		T1	5		T39	1
valid_sources[0x79]	149768	1			T24	3		T12	14		T120	1
valid_sources[0x7a]	125724	1			T24	2		T16	2		T120	12
valid_sources[0x7b]	138753	1			T11	1		T12	7		T16	2
valid_sources[0x7c]	144682	1			T11	2		T12	7		T16	2
valid_sources[0x7d]	135653	1			T24	1		T12	4		T16	1
valid_sources[0x7e]	131810	1			T16	1		T120	1		T2	1
valid_sources[0x7f]	159225	1			T24	3		T11	1		T13	40
valid_sources[0x80]	127995	1			T11	2		T16	3		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8254667

1

T22

60

T23

119

T24

69

values[0x0]

all_enables

biggest_size

10899896

1

T22

47

T23

65

T24

90

values[0x1]

all_enables

biggest_size

10892777

1

T22

48

T23

55

T24

96